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MKL46Z4.s
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MKL46Z4.s
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OPT 2 ;Turn off listing
IF :DEF:MIXED_ASM_C
PRESERVE8
ELSE
PRESERVE8 {FALSE}
ENDIF
;**********************************************************************
;Freescale MKL46Z256xxx4 device values and configuration code
;* Various EQUATES for memory map
;[1] Freescale Semiconductor, <B>Kinetis L Peripheral Module Quick
; Reference</B>, KLQRUG, Rev. 0, 9/2012.
;[2] ARM, <B>Application Note 48 Scatter Loading</B>, ARM DAI 0048A,
; Jan. 1998
;[3] Freescale Semiconductor, <B>KL46 Sub-Family Reference Manual</B>,
; KL46P121M48SF4RM, Rev. 3, 7/2013.
;[4] Freescale Semiconductor, MKL46Z4.h, rev. 2.2, 4/12/2013
;---------------------------------------------------------------
;Author: R. W. Melton
;Date: September 25, 2017
;***************************************************************
;EQUates
;Standard data masks
BYTE_MASK EQU 0xFF
NIBBLE_MASK EQU 0x0F
;Standard data sizes (in bits)
BYTE_BITS EQU 8
NIBBLE_BITS EQU 4
;Architecture data sizes (in bytes)
WORD_SIZE EQU 4 ;Cortex-M0+
HALFWORD_SIZE EQU 2 ;Cortex-M0+
;Architecture data masks
HALFWORD_MASK EQU 0xFFFF
;Return
RET_ADDR_T_MASK EQU 1 ;Bit 0 of ret. addr. must be
;set for BX, BLX, or POP
;mask in thumb
;---------------------------------------------------------------
;Vectors
VECTOR_TABLE_SIZE EQU 0x000000C0 ;KL46
VECTOR_SIZE EQU 4 ;Bytes per vector
;---------------------------------------------------------------
;CPU PSR: Program status register
;Combined APSR, EPSR, and IPSR
;----------------------------------------------------------
;APSR: Application Program Status Register
;31 :N=negative flag
;30 :Z=zero flag
;29 :C=carry flag
;28 :V=overflow flag
;27-0:(reserved)
APSR_MASK EQU 0xF0000000
APSR_SHIFT EQU 28
APSR_N_MASK EQU 0x80000000
APSR_N_SHIFT EQU 31
APSR_Z_MASK EQU 0x40000000
APSR_Z_SHIFT EQU 30
APSR_C_MASK EQU 0x20000000
APSR_C_SHIFT EQU 29
APSR_V_MASK EQU 0x10000000
APSR_V_SHIFT EQU 28
;----------------------------------------------------------
;EPSR
;31-25:(reserved)
; 24:T=thumb state bit
;23- 0:(reserved)
EPSR_MASK EQU 0x01000000
EPSR_SHIFT EQU 24
EPSR_T_MASK EQU 0x01000000
EPSR_T_SHIFT EQU 24
;----------------------------------------------------------
;IPSR
;31-6:(reserved)
; 5-0:Exception number=number of current exception
; 0=thread mode
; 1:(reserved)
; 2=NMI
; 3=hard fault
; 4-10:(reserved)
; 11=SVCall
; 12-13:(reserved)
; 14=PendSV
; 15=SysTick
; 16=IRQ0
; 16-47:IRQ(Exception number - 16)
; 47=IRQ31
; 48-63:(reserved)
IPSR_MASK EQU 0x0000003F
IPSR_SHIFT EQU 0
IPSR_EXCEPTION_MASK EQU 0x0000003F
IPSR_EXCEPTION_SHIFT EQU 0
;----------------------------------------------------------
PSR_N_MASK EQU APSR_N_MASK
PSR_N_SHIFT EQU APSR_N_SHIFT
PSR_Z_MASK EQU APSR_Z_MASK
PSR_Z_SHIFT EQU APSR_Z_SHIFT
PSR_C_MASK EQU APSR_C_MASK
PSR_C_SHIFT EQU APSR_C_SHIFT
PSR_V_MASK EQU APSR_V_MASK
PSR_V_SHIFT EQU APSR_V_SHIFT
PSR_T_MASK EQU EPSR_T_MASK
PSR_T_SHIFT EQU EPSR_T_SHIFT
PSR_EXCEPTION_MASK EQU IPSR_EXCEPTION_MASK
PSR_EXCEPTION_SHIFT EQU IPSR_EXCEPTION_SHIFT
;---------------------------------------------------------------
;Cortex-M0+ Core
__CM0PLUS_REV EQU 0x0000 ;Core revision r0p0
__MPU_PRESENT EQU 0 ;Whether MPU is present
__NVIC_PRIO_BITS EQU 2 ;Number of NVIC priority bits
__Vendor_SysTickConfig EQU 0 ;Whether vendor-specific
;SysTickConfig is defined
__VTOR_PRESENT EQU 1 ;Whether VTOR is present
;---------------------------------------------------------------
;Interrupt numbers
;Core interrupts
NonMaskableInt_IRQn EQU -14 ;Non-maskable interrupt (NMI)
HardFault_IRQn EQU -13 ;Hard fault interrupt
SVCall_IRQn EQU -5 ;Supervisor call interrupt (SVCall)
PendSV_IRQn EQU -2 ;Pendable request for system service interrupt
;(PendableSrvReq)
SysTick_IRQn EQU -1 ;System tick timer interrupt (SysTick)
;--------------------------
;Device specific interrupts
DMA0_IRQn EQU 0 ;DMA channel 0 transfer complete/error interrupt
DMA1_IRQn EQU 1 ;DMA channel 1 transfer complete/error interrupt
DMA2_IRQn EQU 2 ;DMA channel 2 transfer complete/error interrupt
DMA3_IRQn EQU 3 ;DMA channel 3 transfer complete/error interrupt
Reserved20_IRQn EQU 4 ;Reserved interrupt 20
FTFA_IRQn EQU 5 ;FTFA command complete/read collision interrupt
LVD_LVW_IRQn EQU 6 ;Low-voltage detect, low-voltage warning interrupt
LLW_IRQn EQU 7 ;Low leakage wakeup interrupt
I2C0_IRQn EQU 8 ;I2C0 interrupt
I2C1_IRQn EQU 9 ;I2C1 interrupt
SPI0_IRQn EQU 10 ;SPI0 interrupt
SPI1_IRQn EQU 11 ;SPI1 interrupt
UART0_IRQn EQU 12 ;UART0 status/error interrupt
UART1_IRQn EQU 13 ;UART1 status/error interrupt
UART2_IRQn EQU 14 ;UART2 status/error interrupt
ADC0_IRQn EQU 15 ;ADC0 interrupt
CMP0_IRQn EQU 16 ;CMP0 interrupt
TPM0_IRQn EQU 17 ;TPM0 fault, overflow, and channels interrupt
TPM1_IRQn EQU 18 ;TPM1 fault, overflow, and channels interrupt
TPM2_IRQn EQU 19 ;TPM2 fault, overflow, and channels interrupt
RTC_IRQn EQU 20 ;RTC alarm interrupt
RTC_Seconds_IRQn EQU 21 ;RTC seconds interrupt
PIT_IRQn EQU 22 ;PIT interrupt
I2S0_IRQn EQU 23 ;I2S0 interrupt
USB0_IRQn EQU 24 ;USB OTG interrupt
DAC0_IRQn EQU 25 ;DAC0 interrupt
TSI0_IRQn EQU 26 ;TSI0 interrupt
MCG_IRQn EQU 27 ;MCG interrupt
LPTimer_IRQn EQU 28 ;LPTMR0 interrupt
LCD_IRQn EQU 29 ;SLCD interrupt
PORTA_IRQn EQU 30 ;Port A pin detect interrupt
PORTC_PORTD_IRQn EQU 31 ;Port C and Port D pin detectinterrupt
;---------------------------------------------------------------
;Memory map major version
;(Memory maps with equal major version number are compatible)
MCU_MEM_MAP_VERSION EQU 0x0200
;Memory map minor version
MCU_MEM_MAP_VERSION_MINOR EQU 0x0002
;---------------------------------------------------------------
;ADC
ADC0_BASE EQU 0x4003B000
ADC_SC1A_OFFSET EQU 0x00
ADC_SC1B_OFFSET EQU 0x04
ADC_CFG1_OFFSET EQU 0x08
ADC_CFG2_OFFSET EQU 0x0C
ADC_RA_OFFSET EQU 0x10
ADC_RB_OFFSET EQU 0x14
ADC_CV1_OFFSET EQU 0x18
ADC_CV2_OFFSET EQU 0x1C
ADC_SC2_OFFSET EQU 0x20
ADC_SC3_OFFSET EQU 0x24
ADC_OFS_OFFSET EQU 0x28
ADC_PG_OFFSET EQU 0x2C
ADC_MG_OFFSET EQU 0x30
ADC_CLPD_OFFSET EQU 0x34
ADC_CLPS_OFFSET EQU 0x38
ADC_CLP4_OFFSET EQU 0x3C
ADC_CLP3_OFFSET EQU 0x40
ADC_CLP2_OFFSET EQU 0x44
ADC_CLP1_OFFSET EQU 0x48
ADC_CLP0_OFFSET EQU 0x4C
ADC_CLMD_OFFSET EQU 0x54
ADC_CLMS_OFFSET EQU 0x58
ADC_CLM4_OFFSET EQU 0x5C
ADC_CLM3_OFFSET EQU 0x60
ADC_CLM2_OFFSET EQU 0x64
ADC_CLM1_OFFSET EQU 0x68
ADC_CLM0_OFFSET EQU 0x6C
ADC0_CFG1 EQU ( ADC0_BASE + ADC_CFG1_OFFSET)
ADC0_CFG2 EQU ( ADC0_BASE + ADC_CFG2_OFFSET)
ADC0_CLMD EQU ( ADC0_BASE + ADC_CLMD_OFFSET)
ADC0_CLMS EQU ( ADC0_BASE + ADC_CLMS_OFFSET)
ADC0_CLM0 EQU ( ADC0_BASE + ADC_CLM0_OFFSET)
ADC0_CLM1 EQU ( ADC0_BASE + ADC_CLM1_OFFSET)
ADC0_CLM2 EQU ( ADC0_BASE + ADC_CLM2_OFFSET)
ADC0_CLM3 EQU ( ADC0_BASE + ADC_CLM3_OFFSET)
ADC0_CLM4 EQU ( ADC0_BASE + ADC_CLM4_OFFSET)
ADC0_CLPD EQU ( ADC0_BASE + ADC_CLPD_OFFSET)
ADC0_CLPS EQU ( ADC0_BASE + ADC_CLPS_OFFSET)
ADC0_CLP0 EQU ( ADC0_BASE + ADC_CLP0_OFFSET)
ADC0_CLP1 EQU ( ADC0_BASE + ADC_CLP1_OFFSET)
ADC0_CLP2 EQU ( ADC0_BASE + ADC_CLP2_OFFSET)
ADC0_CLP3 EQU ( ADC0_BASE + ADC_CLP3_OFFSET)
ADC0_CLP4 EQU ( ADC0_BASE + ADC_CLP4_OFFSET)
ADC0_CV1 EQU ( ADC0_BASE + ADC_CV1_OFFSET)
ADC0_CV2 EQU ( ADC0_BASE + ADC_CV2_OFFSET)
ADC0_MG EQU ( ADC0_BASE + ADC_MG_OFFSET)
ADC0_OFS EQU ( ADC0_BASE + ADC_OFS_OFFSET)
ADC0_PG EQU ( ADC0_BASE + ADC_PG_OFFSET)
ADC0_RA EQU ( ADC0_BASE + ADC_RA_OFFSET)
ADC0_RB EQU ( ADC0_BASE + ADC_RB_OFFSET)
ADC0_SC1A EQU ( ADC0_BASE + ADC_SC1A_OFFSET)
ADC0_SC1B EQU ( ADC0_BASE + ADC_SC1B_OFFSET)
ADC0_SC2 EQU ( ADC0_BASE + ADC_SC2_OFFSET)
ADC0_SC3 EQU ( ADC0_BASE + ADC_SC3_OFFSET)
;---------------------------------------------------------------
;ADC_CFG1: ADC configuration register 1
;31-8:(reserved):read-only:0
; 7:ADLPC=ADC low-power configuration
; 6-5:ADIV=ADC clock divide select
; Internal ADC clock = input clock / 2^ADIV
; 4:ADLSMP=ADC long sample time configuration
; 0=short
; 1=long
; 3-2:MODE=conversion mode selection
; 00=(DIFF'):single-ended 8-bit conversion
; (DIFF):differential 9-bit 2's complement conversion
; 01=(DIFF'):single-ended 12-bit conversion
; (DIFF):differential 13-bit 2's complement conversion
; 10=(DIFF'):single-ended 10-bit conversion
; (DIFF):differential 11-bit 2's complement conversion
; 11=(DIFF'):single-ended 16-bit conversion
; (DIFF):differential 16-bit 2's complement conversion
; 1-0:ADICLK=ADC input clock select
; 00=bus clock
; 01=bus clock / 2
; 10=alternate clock (ALTCLK)
; 11=asynchronous clock (ADACK)
ADC_CFG1_ADLPC_MASK EQU 0x80
ADC_CFG1_ADLPC_SHIFT EQU 7
ADC_CFG1_ADIV_MASK EQU 0x60
ADC_CFG1_ADIV_SHIFT EQU 5
ADC_CFG1_ADLSMP_MASK EQU 0x10
ADC_CFG1_ADLSMP_SHIFT EQU 4
ADC_CFG1_MODE_MASK EQU 0x0C
ADC_CFG1_MODE_SHIFT EQU 2
ADC_CFG1_ADICLK_MASK EQU 0x03
ADC_CFG1_ADICLK_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CFG2: ADC configuration register 2
;31-8:(reserved):read-only:0
; 7-5:(reserved):read-only:0
; 4:MUXSEL=ADC mux select
; 0=ADxxA channels are selected
; 1=ADxxB channels are selected
; 3:ADACKEN=ADC asynchronous clock output enable
; 0=asynchronous clock determined by ACD0_CFG1.ADICLK
; 1=asynchronous clock enabled
; 2:ADHSC=ADC high-speed configuration
; 0=normal conversion
; 1=high-speed conversion (only 2 additional ADK cycles)
; 1-0:ADLSTS=ADC long sample time select (ADK cycles)
; 00=default longest sample time:
; 24 total ADK cycles (20 extra)
; 01=16 total ADK cycles (12 extra)
; 10=10 total ADK cycles (6 extra)
; 11=6 total ADK cycles (2 extra)
ADC_CFG2_MUXSEL_MASK EQU 0x10
ADC_CFG2_MUXSEL_SHIFT EQU 4
ADC_CFG2_ADACKEN_MASK EQU 0x08
ADC_CFG2_ADACKEN_SHIFT EQU 3
ADC_CFG2_ADHSC_MASK EQU 0x04
ADC_CFG2_ADHSC_SHIFT EQU 2
ADC_CFG2_ADLSTS_MASK EQU 0x03
ADC_CFG2_ADLSTS_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLMD: ADC minus-side general calibration value register D
;31-6:(reserved):read-only:0
; 5-0:CLMD=calibration value
ADC_CLMD_MASK EQU 0x3F
ADC_CLMD_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLMS: ADC minus-side general calibration value register S
;31-6:(reserved):read-only:0
; 5-0:CLMS=calibration value
ADC_CLMS_MASK EQU 0x3F
ADC_CLMS_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLM0: ADC minus-side general calibration value register 0
;31-6:(reserved):read-only:0
; 5-0:CLM0=calibration value
ADC_CLM0_MASK EQU 0x3F
ADC_CLM0_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLM1: ADC minus-side general calibration value register 1
;31-7:(reserved):read-only:0
; 6-0:CLM1=calibration value
ADC_CLM1_MASK EQU 0x7F
ADC_CLM1_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLM2: ADC minus-side general calibration value register 2
;31-8:(reserved):read-only:0
; 7-0:CLM2=calibration value
ADC_CLM2_MASK EQU 0xFF
ADC_CLM2_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLM3: ADC minus-side general calibration value register 3
;31-9:(reserved):read-only:0
; 8-0:CLM3=calibration value
ADC_CLM3_MASK EQU 0x1FF
ADC_CLM3_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLM4: ADC minus-side general calibration value register 4
;31-10:(reserved):read-only:0
; 9- 0:CLM4=calibration value
ADC_CLM4_MASK EQU 0x3FF
ADC_CLM4_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLPD: ADC plus-side general calibration value register D
;31-6:(reserved):read-only:0
; 5-0:CLPD=calibration value
ADC_CLPD_MASK EQU 0x3F
ADC_CLPD_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLPS: ADC plus-side general calibration value register S
;31-6:(reserved):read-only:0
; 5-0:CLPS=calibration value
ADC_CLPS_MASK EQU 0x3F
ADC_CLPS_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLP0: ADC plus-side general calibration value register 0
;31-6:(reserved):read-only:0
; 5-0:CLP0=calibration value
ADC_CLP0_MASK EQU 0x3F
ADC_CLP0_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLP1: ADC plus-side general calibration value register 1
;31-7:(reserved):read-only:0
; 6-0:CLP1=calibration value
ADC_CLP1_MASK EQU 0x7F
ADC_CLP1_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLP2: ADC plus-side general calibration value register 2
;31-8:(reserved):read-only:0
; 7-0:CLP2=calibration value
ADC_CLP2_MASK EQU 0xFF
ADC_CLP2_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLP3: ADC plus-side general calibration value register 3
;31-9:(reserved):read-only:0
; 8-0:CLP3=calibration value
ADC_CLP3_MASK EQU 0x1FF
ADC_CLP3_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CLP4: ADC plus-side general calibration value register 4
;31-10:(reserved):read-only:0
; 9- 0:CLP4=calibration value
ADC_CLP4_MASK EQU 0x3FF
ADC_CLP4_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_CVn: ADC channel n compare value register
;CV1 used to compare result when ADC_SC2.ACFE=1
;CV2 used to compare result when ADC_SC2.ACREN=1
;31-16:(reserved):read-only:0
;15- 0:compare value (sign- or zero-extended if fewer than 16 bits)
ADC_CV_MASK EQU 0xFFFF
ADC_CV_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_MG: ADC minus-side gain register
;31-16:(reserved):read-only:0
;15- 0:MG=minus-side gain
ADC_MG_MASK EQU 0xFFFF
ADC_MG_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_OFS: ADC offset correction register
;31-16:(reserved):read-only:0
;15- 0:OFS=offset error correction value
ADC_OFS_MASK EQU 0xFFFF
ADC_OFS_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_PG: ADC plus-side gain register
;31-16:(reserved):read-only:0
;15- 0:PG=plus-side gain
ADC_PG_MASK EQU 0xFFFF
ADC_PG_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_Rn: ADC channel n data result register
;31-16:(reserved):read-only:0
;15- 0:data result (sign- or zero-extended if fewer than 16 bits)
ADC_D_MASK EQU 0xFFFF
ADC_D_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_SC1n: ADC channel n status and control register 1
;31-8:(reserved):read-only:0
; 7:COCO=conversion complete flag (read-only)
; 6:AIEN=ADC interrupt enabled
; 5:DIFF=differential mode enable
; 4-0:ADCH=ADC input channel select
; 00000=(DIFF'):DADP0;(DIFF):DAD0
; 00001=(DIFF'):DADP1;(DIFF):DAD1
; 00010=(DIFF'):DADP2;(DIFF):DAD2
; 00011=(DIFF'):DADP3;(DIFF):DAD3
; 00100=(DIFF'):AD4;(DIFF):(reserved)
; 00101=(DIFF'):AD5;(DIFF):(reserved)
; 00110=(DIFF'):AD6;(DIFF):(reserved)
; 00111=(DIFF'):AD7;(DIFF):(reserved)
; 01000=(DIFF'):AD8;(DIFF):(reserved)
; 01001=(DIFF'):AD9;(DIFF):(reserved)
; 01010=(DIFF'):AD10;(DIFF):(reserved)
; 01011=(DIFF'):AD11;(DIFF):(reserved)
; 01100=(DIFF'):AD12;(DIFF):(reserved)
; 01101=(DIFF'):AD13;(DIFF):(reserved)
; 01110=(DIFF'):AD14;(DIFF):(reserved)
; 01111=(DIFF'):AD15;(DIFF):(reserved)
; 10000=(DIFF'):AD16;(DIFF):(reserved)
; 10001=(DIFF'):AD17;(DIFF):(reserved)
; 10010=(DIFF'):AD18;(DIFF):(reserved)
; 10011=(DIFF'):AD19;(DIFF):(reserved)
; 10100=(DIFF'):AD20;(DIFF):(reserved)
; 10101=(DIFF'):AD21;(DIFF):(reserved)
; 10110=(DIFF'):AD22;(DIFF):(reserved)
; 10111=(DIFF'):AD23;(DIFF):(reserved)
; 11000 (reserved)
; 11001 (reserved)
; 11010=(DIFF'):temp sensor (single-ended)
; (DIFF):temp sensor (differential)
; 11011=(DIFF'):bandgap (single-ended)
; (DIFF):bandgap (differential)
; 11100 (reserved)
; 11101=(DIFF'):VREFSH (single-ended)
; (DIFF):-VREFSH (differential)
; 11110=(DIFF'):VREFSL (single-ended)
; (DIFF):(reserved)
; 11111=disabled
ADC_COCO_MASK EQU 0x80
ADC_COCO_SHIFT EQU 7
ADC_AIEN_MASK EQU 0x40
ADC_AIEN_SHIFT EQU 6
ADC_DIFF_MASK EQU 0x20
ADC_DIFF_SHIFT EQU 5
ADC_ADCH_MASK EQU 0x1F
ADC_ADCH_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_SC2: ADC status and control register 2
;31-8:(reserved):read-only:0
; 7:ADACT=ADC conversion active
; 6:ADTRG=ADC conversion trigger select
; 0=software trigger
; 1=hardware trigger
; 5:ACFE=ADC compare function enable
; 4:ACFGT=ADC compare function greater than enable
; based on values in ADC_CV1 and ADC_CV2
; 0=configure less than threshold and non-inclusive range
; 1=configure greater than threshold and non-inclusive range
; 3:ACREN=ADC compare function range enable
; 0=disabled; only ADC_CV1 compared
; 1=enabled; both ADC_CV1 and ADC_CV2 compared
; 2:DMAEN=DMA enable
; 1-0:REFSEL=voltage reference selection
; 00=default:VREFH and VREFL
; 01=alterantive:VALTH and VALTL
; 10=(reserved)
; 11=(reserved)
ADC_ADACT_MASK EQU 0x80
ADC_ADACT_SHIFT EQU 7
ADC_ADTRG_MASK EQU 0x40
ADC_ADTRG_SHIFT EQU 6
ADC_ACFE_MASK EQU 0x20
ADC_ACFE_SHIFT EQU 5
ADC_ACFGT_MASK EQU 0x10
ADC_ACFGT_SHIFT EQU 4
ADC_ACREN_MASK EQU 0x08
ADC_ACREN_SHIFT EQU 3
ADC_DMAEN_MASK EQU 0x04
ADC_DMAEN_SHIFT EQU 2
ADC_REFSEL_MASK EQU 0x03
ADC_REFSEL_SHIFT EQU 0
;---------------------------------------------------------------
;ADC_SC3: ADC status and control register 3
;31-8:(reserved):read-only:0
; 7:CAL=calibration
; write:0=(no effect)
; 1=start calibration sequence
; read:0=calibration sequence complete
; 1=calibration sequence in progress
; 6:CALF=calibration failed flag
; 5-4:(reserved):read-only:0
; 3:ADC=ADC continuous conversion enable (if ADC_SC3.AVGE = 1)
; 2:AVGE=hardware average enable
; 1-0:AVGS=hardware average select: 2^(2+AVGS) samples
ADC_CAL_MASK EQU 0x80
ADC_CAL_SHIFT EQU 7
ADC_CALF_MASK EQU 0x40
ADC_CALF_SHIFT EQU 6
ADC_ADCO_MASK EQU 0x08
ADC_ADCO_SHIFT EQU 3
ADC_AVGE_MASK EQU 0x04
ADC_AVGE_SHIFT EQU 2
ADC_AVGS_MASK EQU 0x03
ADC_AVGS_SHIFT EQU 0
;---------------------------------------------------------------
;CMP
CMP0_BASE EQU 0x40073000
CMP0_CR0_OFFSET EQU 0x00
CMP0_CR1_OFFSET EQU 0x01
CMP0_FPR_OFFSET EQU 0x02
CMP0_SCR_OFFSET EQU 0x03
CMP0_DACCR_OFFSET EQU 0x04
CMP0_MUXCR_OFFSET EQU 0x05
CMP0_CR0 EQU (CMP0_BASE + CMP0_CR0_OFFSET)
CMP0_CR1 EQU (CMP0_BASE + CMP0_CR1_OFFSET)
CMP0_FPR EQU (CMP0_BASE + CMP0_FPR_OFFSET)
CMP0_SCR EQU (CMP0_BASE + CMP0_SCR_OFFSET)
CMP0_DACCR EQU (CMP0_BASE + CMP0_DACCR_OFFSET)
CMP0_MUXCR EQU (CMP0_BASE + CMP0_MUXCR_OFFSET)
;---------------------------------------------------------------
;CMP0_CR0: CMP0 control register 0 (0x00)
; 7:(reserved):read-only:0
;6-4:FILTER_CNT=filter sample count (00)
; 3:(reserved):read-only:0
; 2:(reserved):read-only:0
;1-0:HYSTCTR=comparator hard block hysteresis control (00)
CMP_CR0_HYSTCTR_MASK EQU 0x3
CMP_CR0_HYSTCTR_SHIFT EQU 0
CMP_CR0_FILTER_CNT_MASK EQU 0x70
CMP_CR0_FILTER_CNT_SHIFT EQU 4
;---------------------------------------------------------------
;CMP0_CR0: CMP0 control register 1 (0x00)
;7:SE=sample enable (0)
;6:WE=windowing enable (0)
;5:TRIGM=trigger mode enable (0)
;4:PMODE=power mode select (0)
;3:INV=comparator invert (0)
;2:COS=comparator output select (0)
;1:OPE=comparator output pin enable (0)
;0:EN=comparator module enable (0)
CMP_CR1_EN_MASK EQU 0x1
CMP_CR1_EN_SHIFT EQU 0
CMP_CR1_OPE_MASK EQU 0x2
CMP_CR1_OPE_SHIFT EQU 1
CMP_CR1_COS_MASK EQU 0x4
CMP_CR1_COS_SHIFT EQU 2
CMP_CR1_INV_MASK EQU 0x8
CMP_CR1_INV_SHIFT EQU 3
CMP_CR1_PMODE_MASK EQU 0x10
CMP_CR1_PMODE_SHIFT EQU 4
CMP_CR1_TRIGM_MASK EQU 0x20
CMP_CR1_TRIGM_SHIFT EQU 5
CMP_CR1_WE_MASK EQU 0x40
CMP_CR1_WE_SHIFT EQU 6
CMP_CR1_SE_MASK EQU 0x80
CMP_CR1_SE_SHIFT EQU 7
;---------------------------------------------------------------
;CMP0_FPR=CMP filter period register (0x00)
;7-0:FILT_PER=CMP filter period register (0x00)
CMP_FPR_FILT_PER_MASK EQU 0xFF
CMP_FPR_FILT_PER_SHIFT EQU 0
;---------------------------------------------------------------
;CMP0_SCR=CMP status and control register (0x00)
;7:(reserved):read-only:0
;6:DMAEN=DMA enable control (0)
;5:(reserved):read-only:0
;4:IER=comparator interrupt enable rising (0)
;3:IEF=comparator interrupt enable falling (0)
;2:CFR=analog comparator flag rising: w1c (0)
;1:CFF=analog comparator flag falling: w1c (0)
;0:COUT=analog comparator output (0)
CMP_SCR_COUT_MASK EQU 0x1
CMP_SCR_COUT_SHIFT EQU 0
CMP_SCR_CFF_MASK EQU 0x2
CMP_SCR_CFF_SHIFT EQU 1
CMP_SCR_CFR_MASK EQU 0x4
CMP_SCR_CFR_SHIFT EQU 2
CMP_SCR_IEF_MASK EQU 0x8
CMP_SCR_IEF_SHIFT EQU 3
CMP_SCR_IER_MASK EQU 0x10
CMP_SCR_IER_SHIFT EQU 4
CMP_SCR_DMAEN_MASK EQU 0x40
CMP_SCR_DMAEN_SHIFT EQU 6
;---------------------------------------------------------------
;CMP0_DACCR=DAC control register (0x00)
; 7:DACEN=DAC enable (0)
; 6:VRSEL=supply voltage reference source select (0)
;5-0:VOSEL=DAC output voltage select (00000)
; DAC0 = (Vin / 64) x (VOSEL[5:0] + 1)
CMP_DACCR_VOSEL_MASK EQU 0x3F
CMP_DACCR_VOSEL_SHIFT EQU 0
CMP_DACCR_VRSEL_MASK EQU 0x40
CMP_DACCR_VRSEL_SHIFT EQU 6
CMP_DACCR_DACEN_MASK EQU 0x80
CMP_DACCR_DACEN_SHIFT EQU 7
;---------------------------------------------------------------
;CMP0_MUXCR=MUX control register (0x00)
; 7:PSTM=pass through mode enable (0)
;5-3:PSEL=plus input mux control (000)
; selects IN[PSEL]
;2-0:MSEL=minus input mux control (000)
; selects IN[MSEL]
CMP_MUXCR_MSEL_MASK EQU 0x7
CMP_MUXCR_MSEL_SHIFT EQU 0
CMP_MUXCR_PSEL_MASK EQU 0x38
CMP_MUXCR_PSEL_SHIFT EQU 3
CMP_MUXCR_PSTM_MASK EQU 0x80
CMP_MUXCR_PSTM_SHIFT EQU 7
;---------------------------------------------------------------
;DAC
DAC0_BASE EQU 0x4003F000
DAC0_DAT0L_OFFSET EQU 0x00
DAC0_DAT0H_OFFSET EQU 0x01
DAC0_DAT1L_OFFSET EQU 0x02
DAC0_DAT1H_OFFSET EQU 0x03
DAC0_SR_OFFSET EQU 0x20
DAC0_C0_OFFSET EQU 0x21
DAC0_C1_OFFSET EQU 0x22
DAC0_C2_OFFSET EQU 0x23
DAC0_DAT0L EQU (DAC0_BASE + DAC0_DAT0L_OFFSET)
DAC0_DAT0H EQU (DAC0_BASE + DAC0_DAT0H_OFFSET)
DAC0_DAT1L EQU (DAC0_BASE + DAC0_DAT1L_OFFSET)
DAC0_DAT1H EQU (DAC0_BASE + DAC0_DAT1H_OFFSET)
DAC0_SR EQU (DAC0_BASE + DAC0_SR_OFFSET)
DAC0_C0 EQU (DAC0_BASE + DAC0_C0_OFFSET)
DAC0_C1 EQU (DAC0_BASE + DAC0_C1_OFFSET)
DAC0_C2 EQU (DAC0_BASE + DAC0_C2_OFFSET)
;---------------------------------------------------------------
;DAC_DAT0H: DAC data high register 0
;If buffer not enabled, Vout = Vin * (1 + DATA[11:0])/4096.
;7-4:(reserved):read-only:0
;3-0:DATA1=DATA[11:8]
DAC_DAT0H_MASK EQU 0x0F
DAC_DAT0H_SHIFT EQU 0
;---------------------------------------------------------------
;DAC_DAT0L: DAC data low register 0
;If buffer not enabled, Vout = Vin * (1 + DATA[11:0])/4096.
;7-0:DATA0=DATA[7:0]
;---------------------------------------------------------------
;DAC_DAT1H: DAC data high register 1
;If buffer not enabled, Vout = Vin * (1 + DATA[11:0])/4096.
;7-4:(reserved):read-only:0
;3-0:DATA1=DATA[11:8]
DAC_DAT1H_MASK EQU 0x0F
DAC_DAT1H_SHIFT EQU 0
;---------------------------------------------------------------
;DAC_DAT1L: DAC data low register 1
;If buffer not enabled, Vout = Vin * (1 + DATA[11:0])/4096.
;7-0:DATA0=DATA[7:0]
;---------------------------------------------------------------
;DAC_C0: DAC control register 0
;7:DACEN=DAC enable
;6:DACRFS=DAC reference select
; 0:DACREF_1=VREFH
; 1:DACREF_2=VDDA (best for ADC operation)
;5:DACTRGSEL=DAC trigger select
; 0:HW
; 1:SW
;4:DACSWTRG=DAC software trigger
; active-high write-only field that reads 0
; DACBFEN & DACTRGSEL: writing 1 advances buffer pointer
;3:LPEN=DAC low power control
; 0:high-power mode
; 1:low-power mode
;2:(reserved):read-only:0
;1:DACBTIEN=DAC buffer read pointer top flag interrupt enable
;0:DACBBIEN=DAC buffer read pointer bottom flag interrupt enable
DAC_C0_DACEN_MASK EQU 0x80
DAC_C0_DACEN_SHIFT EQU 7
DAC_C0_DACRFS_MASK EQU 0x40
DAC_C0_DACRFS_SHIFT EQU 6
DAC_C0_DACTRGSEL_MASK EQU 0x20
DAC_C0_DACTRGSEL_SHIFT EQU 5
DAC_C0_DACSWTRG_MASK EQU 0x10
DAC_C0_DACSWTRG_SHIFT EQU 4
DAC_C0_LPEN_MASK EQU 0x08
DAC_C0_LPEN_SHIFT EQU 3
DAC_C0_DACBTIEN_MASK EQU 0x02
DAC_C0_DACBTIEN_SHIFT EQU 1
DAC_C0_DACBBIEN_MASK EQU 0x01
DAC_C0_DACBBIEN_SHIFT EQU 0
;---------------------------------------------------------------
;DAC_C1: DAC control register 1
; 7:DMAEN=DMA enable select
;6-3:(reserved)
; 2:DACBFMD=DAC buffer work mode select
; 0:normal
; 1:one-time scan
; 1:(reserved)
; 0:DACBFEN=DAC buffer enable
; 0:disabled:data in first word of buffer
; 1:enabled:read pointer points to data
DAC_C1_DMAEN_MASK EQU 0x80
DAC_C1_DMAEN_SHIFT EQU 7
DAC_C1_DACBFMD_MASK EQU 0x04
DAC_C1_DACBFMD_SHIFT EQU 2
DAC_C1_DACBFEN_MASK EQU 0x01
DAC_C1_DACBFEN_SHIFT EQU 0
;---------------------------------------------------------------
;DAC_C2: DAC control register 2
;7-5:(reserved):read-only:0
; 4:DACBFRP=DAC buffer read pointer
;3-1:(reserved):read-only:0
; 0:DACBFUP=DAC buffer read upper limit
DAC_C2_DACBFRP_MASK EQU 0x10
DAC_C2_DACBFRP_SHIFT EQU 4
DAC_C2_DACBFUP_MASK EQU 0x01
DAC_C2_DACBFUP_SHIFT EQU 0
;---------------------------------------------------------------
;DAC_SR: DAC status register
;Writing 0 clears a field; writing 1 has no effect.
;7-2:(reserved):read-only:0
;1:DACBFRPTF=DAC buffer read pointer top position flag
; Indicates whether pointer is zero
;0:DACBFRPBF=DAC buffer read pointer bottom position flag
; Indicates whether pointer is equal to DAC0_C2.DACBFUP.
DAC_SR_DACBFRPTF_MASK EQU 0x02
DAC_SR_DACBFRPTF_SHIFT EQU 1
DAC_SR_DACBFRPBF_MASK EQU 0x01
DAC_SR_DACBFRPBF_SHIFT EQU 0
;---------------------------------------------------------------
;Fast (zero wait state) GPIO (FGPIO) or (IOPORT)
;FGPIOx_PDD: Port x Data Direction Register
;Bit n: 0=Port x pin n configured as input
; 1=Port x pin n configured as output
FGPIO_BASE EQU 0xF80FF000
;offsets for PDOR, PSOR, PCOR, PTOR, PDIR, and PDDR defined
; with GPIO EQUates
;offsets for Ports A-E defined with GPIO EQUates
;Port A
FGPIOA_BASE EQU 0xF80FF000
FGPIOA_PDOR EQU (FGPIOA_BASE + GPIO_PDOR_OFFSET)
FGPIOA_PSOR EQU (FGPIOA_BASE + GPIO_PSOR_OFFSET)
FGPIOA_PCOR EQU (FGPIOA_BASE + GPIO_PCOR_OFFSET)
FGPIOA_PTOR EQU (FGPIOA_BASE + GPIO_PTOR_OFFSET)
FGPIOA_PDIR EQU (FGPIOA_BASE + GPIO_PDIR_OFFSET)
FGPIOA_PDDR EQU (FGPIOA_BASE + GPIO_PDDR_OFFSET)
;Port B
FGPIOB_BASE EQU 0xF80FF040
FGPIOB_PDOR EQU (FGPIOB_BASE + GPIO_PDOR_OFFSET)
FGPIOB_PSOR EQU (FGPIOB_BASE + GPIO_PSOR_OFFSET)
FGPIOB_PCOR EQU (FGPIOB_BASE + GPIO_PCOR_OFFSET)
FGPIOB_PTOR EQU (FGPIOB_BASE + GPIO_PTOR_OFFSET)
FGPIOB_PDIR EQU (FGPIOB_BASE + GPIO_PDIR_OFFSET)
FGPIOB_PDDR EQU (FGPIOB_BASE + GPIO_PDDR_OFFSET)
;Port C
FGPIOC_BASE EQU 0xF80FF080
FGPIOC_PDOR EQU (FGPIOC_BASE + GPIO_PDOR_OFFSET)
FGPIOC_PSOR EQU (FGPIOC_BASE + GPIO_PSOR_OFFSET)
FGPIOC_PCOR EQU (FGPIOC_BASE + GPIO_PCOR_OFFSET)
FGPIOC_PTOR EQU (FGPIOC_BASE + GPIO_PTOR_OFFSET)
FGPIOC_PDIR EQU (FGPIOC_BASE + GPIO_PDIR_OFFSET)
FGPIOC_PDDR EQU (FGPIOC_BASE + GPIO_PDDR_OFFSET)
;Port D
FGPIOD_BASE EQU 0xF80FF0C0
FGPIOD_PDOR EQU (FGPIOD_BASE + GPIO_PDOR_OFFSET)
FGPIOD_PSOR EQU (FGPIOD_BASE + GPIO_PSOR_OFFSET)
FGPIOD_PCOR EQU (FGPIOD_BASE + GPIO_PCOR_OFFSET)
FGPIOD_PTOR EQU (FGPIOD_BASE + GPIO_PTOR_OFFSET)
FGPIOD_PDIR EQU (FGPIOD_BASE + GPIO_PDIR_OFFSET)
FGPIOD_PDDR EQU (FGPIOD_BASE + GPIO_PDDR_OFFSET)
;Port E
FGPIOE_BASE EQU 0xF80FF100
FGPIOE_PDOR EQU (FGPIOE_BASE + GPIO_PDOR_OFFSET)
FGPIOE_PSOR EQU (FGPIOE_BASE + GPIO_PSOR_OFFSET)
FGPIOE_PCOR EQU (FGPIOE_BASE + GPIO_PCOR_OFFSET)
FGPIOE_PTOR EQU (FGPIOE_BASE + GPIO_PTOR_OFFSET)
FGPIOE_PDIR EQU (FGPIOE_BASE + GPIO_PDIR_OFFSET)
FGPIOE_PDDR EQU (FGPIOE_BASE + GPIO_PDDR_OFFSET)
;---------------------------------------------------------------
;Flash Configuration Field (FCF) 0x400-0x40F
;Following Freescale startup_MKL46Z4.s
; CMSIS Cortex-M0plus Core Device Startup File for the MKL64Z4
; v2.2, 4/12/2013
;16-byte flash configuration field that stores default protection settings
;(loaded on reset) and security information that allows the MCU to
;restrict acces to the FTFL module.
;FCF Backdoor Comparison Key
;8 bytes from 0x400-0x407
;-----------------------------------------------------
;FCF Backdoor Comparison Key 0
;7-0:Backdoor Key 0
FCF_BACKDOOR_KEY0 EQU 0xFF
;-----------------------------------------------------
;FCF Backdoor Comparison Key 1
;7-0:Backdoor Key 1
FCF_BACKDOOR_KEY1 EQU 0xFF
;-----------------------------------------------------
;FCF Backdoor Comparison Key 2
;7-0:Backdoor Key 2
FCF_BACKDOOR_KEY2 EQU 0xFF
;-----------------------------------------------------
;FCF Backdoor Comparison Key 3
;7-0:Backdoor Key 3
FCF_BACKDOOR_KEY3 EQU 0xFF
;-----------------------------------------------------
;FCF Backdoor Comparison Key 4
;7-0:Backdoor Key 4
FCF_BACKDOOR_KEY4 EQU 0xFF
;-----------------------------------------------------
;FCF Backdoor Comparison Key 5
;7-0:Backdoor Key 5
FCF_BACKDOOR_KEY5 EQU 0xFF
;-----------------------------------------------------
;FCF Backdoor Comparison Key 6
;7-0:Backdoor Key 6
FCF_BACKDOOR_KEY6 EQU 0xFF
;-----------------------------------------------------
;FCF Backdoor Comparison Key 7
;7-0:Backdoor Key 7
FCF_BACKDOOR_KEY7 EQU 0xFF
;-----------------------------------------------------
;FCF Flash nonvolatile option byte (FCF_FOPT)
;Allows user to customize operation of the MCU at boot time.
;7-6:11:(reserved)
; 5: 1:FAST_INIT=fast initialization
;4,0:11:LPBOOT=core and system clock divider: 2^(3-LPBOOT)
; 3: 1:RESET_PIN_CFG=enable reset pin following POR
; 2: 1:NMI_DIS=Enable NMI
; 1: 1:(reserved)
; 0:(see bit 4 above)
FCF_FOPT EQU 0xFF
;-----------------------------------------------------
;FCF Program flash protection bytes (FCF_FPROT)
;Each program flash region can be protected from program and erase
;operation by setting the associated PROT bit. Each bit protects a
;1/32 region of the program flash memory.
;FCF FPROT0
;7:1:FCF_PROT7=Program flash region 7/32 not protected
;6:1:FCF_PROT6=Program flash region 6/32 not protected
;5:1:FCF_PROT5=Program flash region 5/32 not protected
;4:1:FCF_PROT4=Program flash region 4/32 not protected
;3:1:FCF_PROT3=Program flash region 3/32 not protected
;2:1:FCF_PROT2=Program flash region 2/32 not protected
;1:1:FCF_PROT1=Program flash region 1/32 not protected
;0:1:FCF_PROT0=Program flash region 0/32 not protected
FCF_FPROT0 EQU 0xFF
;-----------------------------------------------------
;FCF FPROT1
;7:1:FCF_PROT15=Program flash region 15/32 not protected
;6:1:FCF_PROT14=Program flash region 14/32 not protected
;5:1:FCF_PROT13=Program flash region 13/32 not protected
;4:1:FCF_PROT12=Program flash region 12/32 not protected
;3:1:FCF_PROT11=Program flash region 11/32 not protected
;2:1:FCF_PROT10=Program flash region 10/32 not protected
;1:1:FCF_PROT9=Program flash region 9/32 not protected
;0:1:FCF_PROT8=Program flash region 8/32 not protected
FCF_FPROT1 EQU 0xFF
;-----------------------------------------------------
;FCF FPROT2
;7:1:FCF_PROT23=Program flash region 23/32 not protected
;6:1:FCF_PROT22=Program flash region 22/32 not protected
;5:1:FCF_PROT21=Program flash region 21/32 not protected
;4:1:FCF_PROT20=Program flash region 20/32 not protected
;3:1:FCF_PROT19=Program flash region 19/32 not protected
;2:1:FCF_PROT18=Program flash region 18/32 not protected
;1:1:FCF_PROT17=Program flash region 17/32 not protected
;0:1:FCF_PROT16=Program flash region 16/32 not protected
FCF_FPROT2 EQU 0xFF
;-----------------------------------------------------
;FCF FPROT3
;7:1:FCF_PROT31=Program flash region 31/32 not protected
;6:1:FCF_PROT30=Program flash region 30/32 not protected
;5:1:FCF_PROT29=Program flash region 29/32 not protected
;4:1:FCF_PROT28=Program flash region 28/32 not protected
;3:1:FCF_PROT27=Program flash region 27/32 not protected
;2:1:FCF_PROT26=Program flash region 26/32 not protected
;1:1:FCF_PROT25=Program flash region 25/32 not protected
;0:1:FCF_PROT24=Program flash region 24/32 not protected
FCF_FPROT3 EQU 0xFF
;-----------------------------------------------------
;FCF Flash security byte (FCF_FSEC)
;WARNING: If SEC field is configured as "MCU security status is
;secure" and MEEN field is configured as "Mass erase is disabled",
;MCU's security status cannot be set back to unsecure state since
;mass erase via the debugger is blocked !!!
;7-6:01:KEYEN=backdoor key security enable
; :00=Backdoor key access disabled
; :01=Backdoor key access disabled (preferred value)
; :10=Backdoor key access enabled
; :11=Backdoor key access disabled
;5-4:11:MEEN=mass erase enable bits
; (does not matter if SEC unsecure)
; :00=mass erase enabled
; :01=mass erase enabled
; :10=mass erase disabled
; :11=mass erase enabled
;3-2:11:FSLACC=Freescale failure analysis access code
; (does not matter if SEC unsecure)
; :00=Freescale factory access granted
; :01=Freescale factory access denied
; :10=Freescale factory access denied
; :11=Freescale factory access granted
;1-0:10:SEC=flash security
; :00=MCU secure
; :01=MCU secure
; :10=MCU unsecure (standard value)
; :11=MCU secure
FCF_FSEC EQU 0x7E
;---------------------------------------------------------------
;General-purpose input and output (GPIO)
;GPIOx_PDD: Port x Data Direction Register
;Bit n: 0=Port x pin n configured as input
; 1=Port x pin n configured as output
GPIO_BASE EQU 0x400FF000
GPIO_PDOR_OFFSET EQU 0x00
GPIO_PSOR_OFFSET EQU 0x04
GPIO_PCOR_OFFSET EQU 0x08
GPIO_PTOR_OFFSET EQU 0x0C
GPIO_PDIR_OFFSET EQU 0x10
GPIO_PDDR_OFFSET EQU 0x14
GPIOA_OFFSET EQU 0x00
GPIOB_OFFSET EQU 0x40
GPIOC_OFFSET EQU 0x80
GPIOD_OFFSET EQU 0xC0
GPIOE_OFFSET EQU 0x0100
;Port A
GPIOA_BASE EQU 0x400FF000
GPIOA_PDOR EQU (GPIOA_BASE + GPIO_PDOR_OFFSET)
GPIOA_PSOR EQU (GPIOA_BASE + GPIO_PSOR_OFFSET)
GPIOA_PCOR EQU (GPIOA_BASE + GPIO_PCOR_OFFSET)
GPIOA_PTOR EQU (GPIOA_BASE + GPIO_PTOR_OFFSET)
GPIOA_PDIR EQU (GPIOA_BASE + GPIO_PDIR_OFFSET)
GPIOA_PDDR EQU (GPIOA_BASE + GPIO_PDDR_OFFSET)
;Port B
GPIOB_BASE EQU 0x400FF040
GPIOB_PDOR EQU (GPIOB_BASE + GPIO_PDOR_OFFSET)
GPIOB_PSOR EQU (GPIOB_BASE + GPIO_PSOR_OFFSET)
GPIOB_PCOR EQU (GPIOB_BASE + GPIO_PCOR_OFFSET)
GPIOB_PTOR EQU (GPIOB_BASE + GPIO_PTOR_OFFSET)
GPIOB_PDIR EQU (GPIOB_BASE + GPIO_PDIR_OFFSET)
GPIOB_PDDR EQU (GPIOB_BASE + GPIO_PDDR_OFFSET)
;Port C
GPIOC_BASE EQU 0x400FF080
GPIOC_PDOR EQU (GPIOC_BASE + GPIO_PDOR_OFFSET)
GPIOC_PSOR EQU (GPIOC_BASE + GPIO_PSOR_OFFSET)
GPIOC_PCOR EQU (GPIOC_BASE + GPIO_PCOR_OFFSET)
GPIOC_PTOR EQU (GPIOC_BASE + GPIO_PTOR_OFFSET)
GPIOC_PDIR EQU (GPIOC_BASE + GPIO_PDIR_OFFSET)
GPIOC_PDDR EQU (GPIOC_BASE + GPIO_PDDR_OFFSET)
;Port D
GPIOD_BASE EQU 0x400FF0C0
GPIOD_PDOR EQU (GPIOD_BASE + GPIO_PDOR_OFFSET)
GPIOD_PSOR EQU (GPIOD_BASE + GPIO_PSOR_OFFSET)
GPIOD_PCOR EQU (GPIOD_BASE + GPIO_PCOR_OFFSET)
GPIOD_PTOR EQU (GPIOD_BASE + GPIO_PTOR_OFFSET)
GPIOD_PDIR EQU (GPIOD_BASE + GPIO_PDIR_OFFSET)
GPIOD_PDDR EQU (GPIOD_BASE + GPIO_PDDR_OFFSET)
;Port E
GPIOE_BASE EQU 0x400FF100
GPIOE_PDOR EQU (GPIOE_BASE + GPIO_PDOR_OFFSET)
GPIOE_PSOR EQU (GPIOE_BASE + GPIO_PSOR_OFFSET)
GPIOE_PCOR EQU (GPIOE_BASE + GPIO_PCOR_OFFSET)
GPIOE_PTOR EQU (GPIOE_BASE + GPIO_PTOR_OFFSET)
GPIOE_PDIR EQU (GPIOE_BASE + GPIO_PDIR_OFFSET)
GPIOE_PDDR EQU (GPIOE_BASE + GPIO_PDDR_OFFSET)
;---------------------------------------------------------------
;IOPORT: GPIO alias for zero wait state access to GPIO
;See FGPIO
;---------------------------------------------------------------
;LCD Controller (SLCD)
LCD_BASE EQU 0x40053000
LCD_GCR_OFFSET EQU 0x00
LCD_AR_OFFSET EQU 0x04
LCD_FDCR_OFFSET EQU 0x08
LCD_FDSR_OFFSET EQU 0x0C
LCD_PENL_OFFSET EQU 0x10
LCD_PENH_OFFSET EQU 0x14
LCD_BPENL_OFFSET EQU 0x18
LCD_BPENH_OFFSET EQU 0x1C
LCD_WF_OFFSET EQU 0x20 ;WF.D[16] or WF.B[64]
LCD_WF3TO0_OFFSET EQU 0x20
LCD_WF7TO4_OFFSET EQU 0x24
LCD_WF11TO8_OFFSET EQU 0x28
LCD_WF15TO12_OFFSET EQU 0x2C
LCD_WF19TO16_OFFSET EQU 0x30
LCD_WF23TO20_OFFSET EQU 0x34
LCD_WF27TO24_OFFSET EQU 0x38
LCD_WF31TO28_OFFSET EQU 0x3C
LCD_WF35TO32_OFFSET EQU 0x40
LCD_WF39TO36_OFFSET EQU 0x44
LCD_WF43TO40_OFFSET EQU 0x48
LCD_WF47TO44_OFFSET EQU 0x4C
LCD_WF51TO48_OFFSET EQU 0x50
LCD_WF55TO52_OFFSET EQU 0x54
LCD_WF59TO56_OFFSET EQU 0x58
LCD_WF63TO60_OFFSET EQU 0x5C
LCD_GCR EQU (LCD_BASE + LCD_GCR_OFFSET)
LCD_AR EQU (LCD_BASE + LCD_AR_OFFSET)
LCD_FDCR EQU (LCD_BASE + LCD_FDCR_OFFSET)
LCD_FDSR EQU (LCD_BASE + LCD_FDSR_OFFSET)
LCD_PENL EQU (LCD_BASE + LCD_PENL_OFFSET)
LCD_PENH EQU (LCD_BASE + LCD_PENH_OFFSET)
LCD_BPENL EQU (LCD_BASE + LCD_BPENL_OFFSET)
LCD_BPENH EQU (LCD_BASE + LCD_BPENH_OFFSET)
LCD_WF EQU (LCD_BASE + LCD_WF_OFFSET) ;WF.D[16] or WF.B[64]
LCD_WF3TO0 EQU (LCD_BASE + LCD_WF3TO0_OFFSET)
LCD_WF7TO4 EQU (LCD_BASE + LCD_WF7TO4_OFFSET)
LCD_WF11TO8 EQU (LCD_BASE + LCD_WF11TO8_OFFSET)
LCD_WF15TO12 EQU (LCD_BASE + LCD_WF15TO12_OFFSET)
LCD_WF19TO16 EQU (LCD_BASE + LCD_WF19TO16_OFFSET)
LCD_WF23TO20 EQU (LCD_BASE + LCD_WF23TO20_OFFSET)