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Experiment timing limited by slow component #112
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I suspect that understanding/advice is still generally accurate, with two minor additions. The first point is only approximately correct. Labscript has a concept of gated clocks to help ease this problem. You can have multiple clocklines attached to a single pseudoclock (generally how the pulseblaster functions) and if nothing is happening on one clockline, labscript will gate it even though other clocklines on the pseudoclock are ticking. This feature is largely responsible for why most experiments don't see these issues all day every day. The tricky bit here is likely that the direct outputs of the pulseblaster don't get gated in the same way. Second, I would now much more strongly suggest you just replace the pulseblaster with a prawnblaster/prawndo set. The prawnblaster provides 4 completely independent pseudoclocks (ie not clocklines) and the prawndo is a simple addition board to provide those easy digital outputs at the same timing resolution. We wrote an RSI detailing the usage if you are interested in more info before committing. |
Okay, thanks for the clarification, and apologies for the late reply. I didn't really find a lot of documentation on the scheme of gated clocks (though I recall seeing this in some discussion threads) on the official labscript docs, so perhaps that would be a useful addition. We'll look into the prawnblaster/prawndo combination for an upcoming setup we are building. At the moment, we're not quite ready to make this switch in our existing setup. Is there an easy way to get the PulseBlaster digital-outs treated in the exact same manner? This seem a purely software limitation that shouldn't be too bad to resolve, but I'm not too familiar with the PulseBlaster code in Labscript. |
Famous last words, to be sure. Honestly, given how clocklines are implemented, I wouldn't be surprised if the gating feature was already working for the direct outputs (at least I can't think of a reason it would have been excepted from the functionality). I'm not familiar with the gated clocks logic for how the code decides to gate some pulses but not others, but I suspect it may not have the granularity required to accomplish your goal easily. Put another way, I think the clock gating may actually already be working, but activity nearby your trouble point may be circumventing it. More specific advice would require example scripts that others can compile easily, and I'm not sure I have the time at the moment anyway. That said, I try hard to assist new contributors so if you take a stab keep me in the loop. |
Indeed! |
In our lab, we are trying to run a sequence in which we set an analog output at time$t$ (on an NI 6739 card) followed by a digital output (on a PulseBlaster) at a short time $\Delta t$ later. The PulseBlaster is our primary pseudoclock.
On compiling, labscript complains as follows:
This even though the 6739 does not need to receive the trigger at$t + \Delta t$ .
I came across this discussion from 2022 suggesting that:
Is all this still accurate / timely — still the best way to get the desired timing?
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