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DCC_V_33.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
# Date created = 19:32:42 April 04, 2015
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# DCC_V_33_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV GX"
set_global_assignment -name DEVICE EP4CGX150DF31C7
set_global_assignment -name TOP_LEVEL_ENTITY DCC_V_33
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:32:42 APRIL 04, 2015"
set_global_assignment -name LAST_QUARTUS_VERSION 14.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_AJ16 -to OSC_50[0]
set_location_assignment PIN_A15 -to OSC_50[1]
set_location_assignment PIN_V11 -to OSC_50[2]
set_location_assignment PIN_T23 -to LEDR[0]
set_location_assignment PIN_T24 -to LEDR[1]
set_location_assignment PIN_V27 -to LEDR[2]
set_location_assignment PIN_W25 -to LEDR[3]
set_location_assignment PIN_T21 -to LEDR[4]
set_location_assignment PIN_T26 -to LEDR[5]
set_location_assignment PIN_R25 -to LEDR[6]
set_location_assignment PIN_T27 -to LEDR[7]
set_location_assignment PIN_P25 -to LEDR[8]
set_location_assignment PIN_R24 -to LEDR[9]
set_location_assignment PIN_P21 -to LEDR[10]
set_location_assignment PIN_N24 -to LEDR[11]
set_location_assignment PIN_N21 -to LEDR[12]
set_location_assignment PIN_M25 -to LEDR[13]
set_location_assignment PIN_K24 -to LEDR[14]
set_location_assignment PIN_L25 -to LEDR[15]
set_location_assignment PIN_M21 -to LEDR[16]
set_location_assignment PIN_M22 -to LEDR[17]
set_location_assignment PIN_AA25 -to LEDG[0]
set_location_assignment PIN_AB25 -to LEDG[1]
set_location_assignment PIN_F27 -to LEDG[2]
set_location_assignment PIN_F26 -to LEDG[3]
set_location_assignment PIN_W26 -to LEDG[4]
set_location_assignment PIN_Y22 -to LEDG[5]
set_location_assignment PIN_Y25 -to LEDG[6]
set_location_assignment PIN_AA22 -to LEDG[7]
set_location_assignment PIN_J25 -to LEDG[8]
set_location_assignment PIN_AA26 -to KEY[0]
set_location_assignment PIN_AE25 -to KEY[1]
set_location_assignment PIN_AF30 -to KEY[2]
set_location_assignment PIN_AE26 -to KEY[3]
set_location_assignment PIN_V28 -to SW[0]
set_location_assignment PIN_U30 -to SW[1]
set_location_assignment PIN_V21 -to SW[2]
set_location_assignment PIN_C2 -to SW[3]
set_location_assignment PIN_AB30 -to SW[4]
set_location_assignment PIN_U21 -to SW[5]
set_location_assignment PIN_T28 -to SW[6]
set_location_assignment PIN_R30 -to SW[7]
set_location_assignment PIN_P30 -to SW[8]
set_location_assignment PIN_R29 -to SW[9]
set_location_assignment PIN_R26 -to SW[10]
set_location_assignment PIN_N26 -to SW[11]
set_location_assignment PIN_M26 -to SW[12]
set_location_assignment PIN_N25 -to SW[13]
set_location_assignment PIN_J26 -to SW[14]
set_location_assignment PIN_K25 -to SW[15]
set_location_assignment PIN_C30 -to SW[16]
set_location_assignment PIN_H25 -to SW[17]
set_location_assignment PIN_G6 -to CLKOUT0
set_location_assignment PIN_K15 -to CLKIN1
set_location_assignment PIN_AC25 -to ADA_D[13]
set_location_assignment PIN_E27 -to ADB_D[13]
set_location_assignment PIN_AB26 -to ADA_D[12]
set_location_assignment PIN_E28 -to ADB_D[12]
set_location_assignment PIN_J28 -to ADA_D[11]
set_location_assignment PIN_G26 -to ADB_D[11]
set_location_assignment PIN_H28 -to ADA_D[10]
set_location_assignment PIN_G27 -to ADB_D[10]
set_location_assignment PIN_F28 -to ADA_D[9]
set_location_assignment PIN_G28 -to ADB_D[9]
set_location_assignment PIN_F29 -to ADA_D[8]
set_location_assignment PIN_G29 -to ADB_D[8]
set_location_assignment PIN_D29 -to ADA_D[7]
set_location_assignment PIN_J27 -to ADB_D[7]
set_location_assignment PIN_D30 -to ADA_D[6]
set_location_assignment PIN_H27 -to ADB_D[6]
set_location_assignment PIN_F30 -to ADA_D[5]
set_location_assignment PIN_K28 -to ADB_D[5]
set_location_assignment PIN_E30 -to ADA_D[4]
set_location_assignment PIN_K29 -to ADB_D[4]
set_location_assignment PIN_H30 -to ADA_D[3]
set_location_assignment PIN_L27 -to ADB_D[3]
set_location_assignment PIN_G30 -to ADA_D[2]
set_location_assignment PIN_L28 -to ADB_D[2]
set_location_assignment PIN_J29 -to ADA_D[1]
set_location_assignment PIN_M27 -to ADB_D[1]
set_location_assignment PIN_J30 -to ADA_D[0]
set_location_assignment PIN_M28 -to ADB_D[0]
set_location_assignment PIN_K26 -to ADA_OR
set_location_assignment PIN_N29 -to ADB_OR
set_location_assignment PIN_K27 -to ADA_OE
set_location_assignment PIN_N30 -to ADB_OE
set_location_assignment PIN_L30 -to ADA_SPI_CS
set_location_assignment PIN_P27 -to ADB_SPI_CS
set_location_assignment PIN_K30 -to AD_SDIO
set_location_assignment PIN_P28 -to AD_SCLK
set_location_assignment PIN_AB27 -to FPGA_CLK_A_P
set_location_assignment PIN_V29 -to XT_IN_P
set_location_assignment PIN_AB28 -to FPGA_CLK_A_N
set_location_assignment PIN_V30 -to XT_IN_N
set_location_assignment PIN_U25 -to DA[13]
set_location_assignment PIN_R27 -to DB[13]
set_location_assignment PIN_T25 -to DA[12]
set_location_assignment PIN_R28 -to DB[12]
set_location_assignment PIN_N27 -to DA[11]
set_location_assignment PIN_U27 -to DB[11]
set_location_assignment PIN_N28 -to DA[10]
set_location_assignment PIN_U28 -to DB[10]
set_location_assignment PIN_V25 -to DA[9]
set_location_assignment PIN_W27 -to DB[9]
set_location_assignment PIN_V26 -to DA[8]
set_location_assignment PIN_W28 -to DB[8]
set_location_assignment PIN_AA30 -to DA[7]
set_location_assignment PIN_W29 -to DB[7]
set_location_assignment PIN_Y30 -to DA[6]
set_location_assignment PIN_W30 -to DB[6]
set_location_assignment PIN_AC27 -to DA[5]
set_location_assignment PIN_M29 -to DB[5]
set_location_assignment PIN_AC28 -to DA[4]
set_location_assignment PIN_M30 -to DB[4]
set_location_assignment PIN_AD29 -to DA[3]
set_location_assignment PIN_AA27 -to DB[3]
set_location_assignment PIN_AD30 -to DA[2]
set_location_assignment PIN_Y27 -to DB[2]
set_location_assignment PIN_AE29 -to DA[1]
set_location_assignment PIN_AB29 -to DB[1]
set_location_assignment PIN_AE30 -to DA[0]
set_location_assignment PIN_AA29 -to DB[0]
set_location_assignment PIN_AJ30 -to AIC_DIN
set_location_assignment PIN_AD27 -to AIC_DOUT
set_location_assignment PIN_AH30 -to AIC_LRCIN
set_location_assignment PIN_AD28 -to AIC_LRCOUT
set_location_assignment PIN_AH29 -to AIC_BCLK
set_location_assignment PIN_AE27 -to AIC_XCLK
set_location_assignment PIN_AG29 -to AIC_SPI_CS
set_location_assignment PIN_AE28 -to J1_152
set_location_assignment PIN_AA28 -to FPGA_CLK_B_P
set_location_assignment PIN_T29 -to ADA_DCO
set_location_assignment PIN_Y28 -to FPGA_CLK_B_N
set_location_assignment PIN_T30 -to ADB_DCO
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS64
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_FILE src/FIR_LMS_33_Parallel.v
set_global_assignment -name VERILOG_FILE matlab/FIR_HAM_V_33.v
set_global_assignment -name VERILOG_FILE src/DCC_V_33.v
set_global_assignment -name QIP_FILE src/ip/add.qip
set_global_assignment -name QIP_FILE src/ip/pll.qip
set_global_assignment -name SDC_FILE src/DCC_V_33.sdc
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top