diff --git a/examples/test_simple_alu.py b/examples/test_simple_alu.py
index ec14277b..81fe74c6 100644
--- a/examples/test_simple_alu.py
+++ b/examples/test_simple_alu.py
@@ -1,5 +1,4 @@
 import magma as m
-# import mantle
 import operator
 import fault
 import pytest
@@ -11,7 +10,7 @@ class ConfigReg(m.Circuit):
     io = m.IO(D=m.In(m.Bits[2]), Q=m.Out(m.Bits[2])) + \
         m.ClockIO(has_ce=True)
 
-    reg = mantle.Register(2, has_ce=True, name="conf_reg")
+    reg = m.Register(m.Bits[2], has_enable=True)(name="conf_reg")
     io.Q @= reg(io.D, CE=io.CE)
 
 
@@ -24,7 +23,7 @@ class SimpleALU(m.Circuit):
               ) + m.ClockIO()
 
     opcode = ConfigReg(name="config_reg")(io.config_data, CE=io.config_en)
-    io.c @= mantle.mux(
+    io.c @= m.mux(
         [io.a + io.b, io.a - io.b, io.a * io.b, io.a ^ io.b], opcode)