From 1c08e42ebd0e3621858dab6e8ce6bb05dc750006 Mon Sep 17 00:00:00 2001
From: Lenny Truong <leonardtruong@meta.com>
Date: Wed, 6 Dec 2023 19:38:55 -0800
Subject: [PATCH] Update code

---
 tutorial/exercise_1.py |  5 ++---
 tutorial/exercise_2.py | 11 +++++------
 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/tutorial/exercise_1.py b/tutorial/exercise_1.py
index ef0e73a0..89a823a5 100644
--- a/tutorial/exercise_1.py
+++ b/tutorial/exercise_1.py
@@ -1,12 +1,11 @@
 import magma as m
-# import mantle
 
 
 class ConfigReg(m.Circuit):
     io = m.IO(D=m.In(m.Bits[2]), Q=m.Out(m.Bits[2])) + \
         m.ClockIO(has_ce=True)
 
-    reg = mantle.Register(2, has_ce=True, name="config_reg")
+    reg = m.Register(m.Bits[2], has_enable=True)(name="config_reg")
     io.Q <= reg(io.D, CE=io.CE)
 
 
@@ -19,5 +18,5 @@ class SimpleALU(m.Circuit):
               ) + m.ClockIO()
 
     opcode = ConfigReg(name="opcode_reg")(io.config_data, CE=io.config_en)
-    io.c <= mantle.mux(
+    io.c <= m.mux(
         [io.a + io.b, io.a - io.b, io.a * io.b, io.b - io.a], opcode)
diff --git a/tutorial/exercise_2.py b/tutorial/exercise_2.py
index c21d2e1e..bc14f876 100644
--- a/tutorial/exercise_2.py
+++ b/tutorial/exercise_2.py
@@ -1,5 +1,4 @@
 import magma as m
-# import mantle
 import fault
 from reset_tester import ResetTester
 
@@ -18,11 +17,11 @@ class ROM(m.Circuit):
         CLK=m.In(m.Clock)
     )
 
-    regs = [mantle.Register(data_width, init=int(init[i]))
+    regs = [m.Register(m.Bits[data_width], init=int(init[i]))()
             for i in range(1 << addr_width)]
     for reg in regs:
         reg.I <= reg.O
-    io.RDATA <= mantle.mux([reg.O for reg in regs], io.RADDR)
+    io.RDATA <= m.mux([reg.O for reg in regs], io.RADDR)
 
 
 class RAM(m.Circuit):
@@ -36,10 +35,10 @@ class RAM(m.Circuit):
         RESET=m.In(m.Reset)
     )
 
-    regs = [mantle.Register(data_width, init=int(init[i]), has_ce=True,
-                            has_reset=True)
+    regs = [m.Register(m.Bits[data_width], init=int(init[i]), has_enable=True,
+                       reset_type=m.Reset)
             for i in range(1 << addr_width)]
     for i, reg in enumerate(regs):
         reg.I <= io.WDATA
         reg.CE <= (io.WADDR == m.bits(i, addr_width)) & io.WE
-    io.RDATA <= mantle.mux([reg.O for reg in regs], io.RADDR)
+    io.RDATA <= m.mux([reg.O for reg in regs], io.RADDR)