From 417d2137392f256dd2b4644b1c13bf20c5b16e0f Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 22 Nov 2023 08:21:22 -0800 Subject: [PATCH] Try setting magma opts --- tests/test_property.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/test_property.py b/tests/test_property.py index e4948679..ee7dd30f 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -917,6 +917,8 @@ class Main(m.Circuit): tester.compile_and_run("system-verilog", simulator="ncsim", magma_output="mlir-verilog", flags=["-sv"], skip_compile=True, disp_type="realtime", + magma_opts={"sv": True, + "disable_initial_blocks": True}, coverage=True) out, _ = capsys.readouterr() @@ -933,6 +935,8 @@ class Main(m.Circuit): tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], skip_compile=True, + magma_opts={"sv": True, + "disable_initial_blocks": True}, disp_type="realtime", coverage=True) out, _ = capsys.readouterr() @@ -953,6 +957,8 @@ class Main(m.Circuit): flags=["-sv"], skip_compile=True, disp_type="realtime", + magma_opts={"sv": True, + "disable_initial_blocks": True}, coverage=True) out, _ = capsys.readouterr()