MEGA65: implement hardware errata register/levels and its effects

[lgblgblgb]

MEGA65 has the "HWERRATA" (hardware errata) register which tries to provide bug-to-bug compatibility for older software when something in mega65-core is changed meanwhile which found problematic for older software. As far as I can tell, currently there is three different hardware errata levels (every next level also carries the fixes from the previous levels!):

Level	Meaning	Xemu status
0	Most compatible with C65 and with older mega65-core versions, no fixes	OK
1	$D016 bug in H640mode is fixed at this level, ie already on C65 value of "2" meant zero, now zero is zero VHDL designation: bug_compat_vic_iii_d016_delta	OK-ish in dae4fa2
2	Char attribute fix VHDL designation: bug_compat_char_attr	TODO

HWERRATA register is at $D08F. Writing any value greater than the max supported will cause the max supported value is used. The used value can be read back in the same register. However there is also an older way for this errata story, VIC-IV register $D07A.5, a single bit, though this is a deprecated feature. When it is changed, the "real" HWERRATA register is set to the max supported value (bit is set) or zero (bit is cleared). It seems there is no feedback from $D08F to this bit though, only setting that, won't effect this bit when read back.