rust-libp2p on an FPGA with RISC-V core (WIP)

[elenaf9]

I have been putting some effort towards the implementation of a p2p-network with rust-libp2p on an Field Programmable Gate Away (FPGA). At the current point in time, I did not succeed at running the application on actual hardware. However, I have done some first steps and collected research that I'd like to share and discuss, in case that anybody is interested in it.

The idea is to build on existing open-source projects that implement the RISC-V Instruction Set Architecture on an FPGA.
Since Rust supports some RISC-V targets, the goal is to implement a system on the FPGA that meets all the requirement from the Rust target, and execute a PoC for the P2P-Network on it.

Relevant Rust Targets:

• [std] riscv64gc-unknown-linux-gnu: Requires 64-bit RISC-V core with Linux kernel v4.20 and glibc v2.29
• [no_std] riscv32imc-unknown-none-elf: Bare RISC-V (RV32IMC ISA)
• riscv32gc-unknown-linux-gnu: only initial Tier 3 support, so far no support for std

Cross-compiling rust-libp2p for RISC-V

Rust-libp2p requires Rust Standard library, hence only works for riscv64gc-unknown-linux-gnu.
I managed to build rust-libp2p for the riscv64gc-unknown-linux-gnu target by setting cfg flags for arch = "riscv64" in the code analogous to how it is also done for arch = wasm32.
The problem is that the ring crate currently does not support the riscv64 arch, the best long-term solution would be to add a PR for that, but so far I haven't looked into that. I am not sure whether my current solution is sufficient enough to add a PR to upstream rust-libp2p, but this is the commit with the changes: elenaf9@3212aa5.

RISC-V on FPGA

I have been looking into two soft-CPUs ( = CPUs that are written in Software with a Hardware Description Language, yet behave the same way as a hardwired implementation would) that both implement the RISC-V ISA.
As hardware, I used the IOTA Crypto Core FPGA for initial testing of a baremetal app, as its core already includes a VexRiscv implementation. I then switched to using the Xilinx Arty A7 development board since it is a common board supported by e.g. the Linux-on-Litex-VexRiscv project.

VexRiscv:

• RV32I(M)(A)(F)(D)(C) ISA
• I wrote/ tested a baremetal rust program for it with target riscv32imc-unknown-none-elf, to verify that it is possible to execute cross-compiled rust code on a RISC-V soft-cpu (based on an blogpost from Craig Bishop). This was successful and might be relevant in case that libp2p would ever support no_std, but I know this is currently not a priority.
• Linux-on-Litex-VexRiscv project supports running Linux on it by using it as core within the LiteX SoC builder. I was able to test this and establish a connection between by host computer and the board, but executing the P2P app failed since it is 32-bit instead of the required 64-bit. It would be interesting to test this again once Rust supports the Standard library also for the riscv32gc-unknown-linux-gnu target

Rocket Chip:

• RV32/ RV64G ISA
• embedded into a System-on-Chip that can be generated with the Rocket Chip Generator
• Linux-on-Litex-Rocket project supports running Linux on it, but not for the Arty A7-35T (though it recently received supported for the Arty A7-100T), hence I was not able to test it.
• I tested a Renode simulation of the SiFive Highfive Unleashed with an implementation of the SiFive Freedom Unleashed Platform (supports Linux on a SoC with 64-bit Rocket Chip), this only failed because the script from Renode that runs this simulation uses an version of glibc older than the required v2.29.

---

---

While I know that this work is more a niche-thing, i'd love to hear if anybody else has been working on adopting rust-libp2p for RISC-V, or any other platform.

Repository with the collected research: https://github.com/elenaf9/p2p-on-fpga