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Issues synthesizing bitstream #411

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No-0n3 opened this issue Dec 9, 2024 · 3 comments
Open

Issues synthesizing bitstream #411

No-0n3 opened this issue Dec 9, 2024 · 3 comments

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@No-0n3
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No-0n3 commented Dec 9, 2024

Hi,

Been trying to synthesize a bitstream for ulx3s (85F) with "./make --board=ulx3s --device=LFE5U-85F --build" using the recompiled linux images.

I run into an error that I run out of "TRELLIS_SLICE" (180% approx. According to console) and it can't fulfill the syntezisis can't be fulfilled as resources aren't enough.

Tried to restrict the cpu-count but still the same issue that it uses more resources than it should it seems. The board is a ulx3s v3.0.8 with 32Mb sdram.

Resources used:

  1. Executing JSON backend.

Warnings: 2 unique messages, 2 total
End of script. Logfile hash: 22ad2087f1, CPU: user 496.62s system 23.62s, MEM: 3331.66 MB peak
Yosys 0.9+3619 (git sha1 c8f052bb, g++ 8.3.0 -Os)
Time spent: 38% 1x autoname (223 sec), 10% 30x opt_reduce (61 sec),
Info: constraining clock net 'clk25' to 25.00 MHz

Info: Logic utilisation before packing:
Info: Total LUT4s: 150617/83640 180%
Info: logic LUTs: 73033/83640 87%
Info: carry LUTs: 1504/83640 1%
Info: RAM LUTs: 50720/41820 121%
Info: RAMW LUTs: 25360/20910 121%

Info: Total DFFs: 14072/83640 16%

Error:

Info: Device utilisation:
Info: TRELLIS_SLICE: 84170/41820 201%
Info: TRELLIS_IO: 62/ 365 16%
Info: DCCA: 4/ 56 7%
Info: DP16KD: 43/ 208 20%
Info: MULT18X18D: 4/ 156 2%
Info: ALU54B: 0/ 78 0%
Info: EHXPLLL: 2/ 4 50%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 45/ 224 20%
Info: SIOLOGIC: 4/ 141 2%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 14 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%

Info: Placed 113 cells based on constraints.
ERROR: Unable to place cell 'storage_10.0.571.0_WRE_LUT4_Z_SLICE', no Bels remaining of type 'TRELLIS_SLICE'
0 warnings, 1 error
Traceback (most recent call last):
File "/home/isaac/linux-on-litex-vexriscv/./make.py", line 199, in
main()
File "/home/isaac/linux-on-litex-vexriscv/./make.py", line 172, in main
builder.build(run=args.build, build_name=board_name)
File "/home/isaac/litex/litex/litex/soc/integration/builder.py", line 415, in build
vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/isaac/litex/litex/litex/soc/integration/soc.py", line 1497, in build
return self.platform.build(self, *args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/isaac/litex/litex/litex/build/lattice/platform.py", line 63, in build
return self.toolchain.build(self, *args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/isaac/litex/litex/litex/build/lattice/trellis.py", line 67, in build
return YosysNextPNRToolchain.build(self, platform, fragment, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/isaac/litex/litex/litex/build/yosys_nextpnr_toolchain.py", line 127, in build
return GenericToolchain.build(self, platform, fragment, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/isaac/litex/litex/litex/build/generic_toolchain.py", line 123, in build
self.run_script(script)
File "/home/isaac/litex/litex/litex/build/yosys_nextpnr_toolchain.py", line 234, in run_script
raise OSError("Error occured during Yosys/Nextpnr's script execution.")
OSError: Error occured during Yosys/Nextpnr's script execution.

@Dolu1990
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Dolu1990 commented Dec 9, 2024

Hi,

This is realy weird, because when this kind of LUT explosion comes, it is because of some memories not being infered as memory blocks.
That comes with the symptom of which flipflop utilisation.

But in your case, it isn't the case XD :
Info: Total DFFs: 14072/83640 16%

So, i realy have no idea what can have happened there.
Info: Total LUT4s: 150617/83640 180% realy look crazy.

Could it be a ROM ? the being inferred as block ram but in logic instead ?

@No-0n3
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No-0n3 commented Dec 9, 2024

After some debugging of the compilation, commented out the soc_capabilities in boards.py file for ulx3s (sdcard and framebuffer). Could build with sdcard but when building with framebuffer the issue comes up. Can boot into Linux without any problems if I build with the framebuffer soc capability is commented out. Is there any earlier bugs with the HDMI and video?

@Dolu1990
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No idea.

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