From 88ab3eca6fa07a8464fc0616a62fa8baa9232c94 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 17 Jul 2024 11:01:34 +0200 Subject: [PATCH] targets: Map SPRAM to SRAM when use as SRAM. --- litex_boards/targets/lattice_ice40up5k_evn.py | 2 +- litex_boards/targets/muselab_icesugar.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/lattice_ice40up5k_evn.py b/litex_boards/targets/lattice_ice40up5k_evn.py index 68be67bca..4d0bb9ddc 100755 --- a/litex_boards/targets/lattice_ice40up5k_evn.py +++ b/litex_boards/targets/lattice_ice40up5k_evn.py @@ -69,7 +69,7 @@ def __init__(self, bios_flash_offset, sys_clk_freq=12e6, # 128KB SPRAM (used as SRAM) --------------------------------------------------------------- self.spram = Up5kSPRAM(size=128 * KILOBYTE) - self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128 * KILOBYTE)) + self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE)) # SPI Flash -------------------------------------------------------------------------------- # 4x mode is not possible on this board since WP and HOLD pins are not connected to the FPGA diff --git a/litex_boards/targets/muselab_icesugar.py b/litex_boards/targets/muselab_icesugar.py index e532222da..b030d59c9 100755 --- a/litex_boards/targets/muselab_icesugar.py +++ b/litex_boards/targets/muselab_icesugar.py @@ -73,7 +73,7 @@ def __init__(self, bios_flash_offset, sys_clk_freq=24e6, # 128KB SPRAM (used as SRAM) --------------------------------------------------------------- self.spram = Up5kSPRAM(size=64 * KILOBYTE) - self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64 * KILOBYTE)) + self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=64 * KILOBYTE)) # SPI Flash -------------------------------------------------------------------------------- from litespi.modules import W25Q64FV