Numato Tagus PCIe pin constraints not working properly

[davidv1992]

When building the Numato Tagus board target using

python3 numato_tagus.py --with-pcie --cpu-type None --build

the resulting bitstream doesn't function on device correctly (the pcie endpoint is not visible from the OS), and a dig through the IO report indicates why: The constraints for the PCIe port are not properly applied for some reason and instead of the intended pins (A4,B4,A8,B8) for the TX/RX pins of the PCIe x1 slot, the vivado toolchain uses the pins (C7, D7, C9, D9)

This was observed building using the Vivado 2024.1 software. I have gotten the numato pcie sample project working with the same software, so it seems unlikely to be a bug in Vivado.

If this is not the correct place to report this bug (which probably is likely, given that the board files themselves look fine to me) please let me know where I should report it.

[enjoy-digital]

Hi @davidv1992,

sorry for the delay, that's the right place to report the issue yes and thanks for the feedback. The issue is probably similar to what is observed on the Mini baseboard/Acorn when configured for PCIe X1 where Vivado does a switch of the PCIe pins. To avoid this, you'll have to use constraints similar to these.

To find the correct GTPE2_CHANNEL, you can open your routed design checkpoint and use the floorplan editor to locate it based on the pinout.