Regression with LiteX USB OHCI, segfaults

[mntmn]

Hi,

I'm working on a release system for MNT RKX7 based on Kintex-7, and everything was working nicely until I updated pythondata-cpu-vexriscv-smp to the newest version from Git (b360267). I'm using linux-on-litex-vexriscv and the integration with USBOHCI from SpinalHDL which also requires coherent DMA. With the newest vexriscv-smp, USB broke and the kernel constantly spits out errors and resets on the USB ports. Also, there are random segfaults running executables and an oops in a bridge driver (harmless, but does not appear with older vexriscv-smp build).

I tried to bisect. Version 4306ae2 does not build:

[error] /home/mntmn/code/litex/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/ext/SpinalHDL/lib/src/main/scala/spinal/lib/bus/bmb/BmbInterconnectGenerator.scala:173:61: reference to Lock is ambiguous;
[error] it is imported twice in the same scope by
[error] import spinal.lib.generator._
[error] and import spinal.core.fiber._
[error]   case class SlaveModel(@dontName bus : Handle[Bmb], lock : Lock) extends Area{
[error]
...

The next oldest version is 60c32b1. This builds fine and works fine—the system is stable.

Unfortunately I don't have the time/resources to dig into the root of the problem at the moment, but I thought I'd notify you just in case.

Thanks for all the good work on these cores btw!