From 027343e79d0c1ec55eebdf4590fd57b12ecf086b Mon Sep 17 00:00:00 2001 From: jofrn Date: Wed, 4 Dec 2024 13:00:33 -0500 Subject: [PATCH] Add tests for double,half,bfloat,fp128 --- llvm/test/CodeGen/X86/atomicvec-float.ll | 96 ++++++++++++++++--- .../AtomicExpand/atomicvec-float.ll | 83 +++++++++++++--- 2 files changed, 153 insertions(+), 26 deletions(-) diff --git a/llvm/test/CodeGen/X86/atomicvec-float.ll b/llvm/test/CodeGen/X86/atomicvec-float.ll index 248dec1ee6acce..39e6772c8fd01b 100644 --- a/llvm/test/CodeGen/X86/atomicvec-float.ll +++ b/llvm/test/CodeGen/X86/atomicvec-float.ll @@ -1,26 +1,81 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc < %s --mtriple=x86_64 | FileCheck %s -define float @load_atomic_float(ptr %src) { -; CHECK-LABEL: load_atomic_float: +define <1 x float> @load_atomic_vector1_float(ptr %src) { +; CHECK-LABEL: load_atomic_vector1_float: ; CHECK: # %bb.0: ; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: retq - %ret = load atomic float, ptr %src acquire, align 4 - ret float %ret + %ret = load atomic <1 x float>, ptr %src acquire, align 4 + ret <1 x float> %ret } -define <1 x float> @load_atomic_vector_float1(ptr %src) { -; CHECK-LABEL: load_atomic_vector_float1: +define <2 x float> @load_atomic_vector2_float(ptr %src) { +; CHECK-LABEL: load_atomic_vector2_float: ; CHECK: # %bb.0: -; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: movq %rdi, %rsi +; CHECK-NEXT: movq %rsp, %rdx +; CHECK-NEXT: movl $8, %edi +; CHECK-NEXT: movl $2, %ecx +; CHECK-NEXT: callq __atomic_load@PLT +; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: retq - %ret = load atomic <1 x float>, ptr %src acquire, align 4 - ret <1 x float> %ret + %ret = load atomic <2 x float>, ptr %src acquire, align 4 + ret <2 x float> %ret } -define <2 x float> @load_atomic_vector_float2(ptr %src) { -; CHECK-LABEL: load_atomic_vector_float2: +define <1 x double> @load_atomic_vector1_double(ptr %src) { +; CHECK-LABEL: load_atomic_vector1_double: +; CHECK: # %bb.0: +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: movq %rdi, %rsi +; CHECK-NEXT: movq %rsp, %rdx +; CHECK-NEXT: movl $8, %edi +; CHECK-NEXT: movl $2, %ecx +; CHECK-NEXT: callq __atomic_load@PLT +; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: retq + %ret = load atomic <1 x double>, ptr %src acquire, align 4 + ret <1 x double> %ret +} + +define <2 x double> @load_atomic_vector2_double(ptr %src) { +; CHECK-LABEL: load_atomic_vector2_double: +; CHECK: # %bb.0: +; CHECK-NEXT: subq $24, %rsp +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: movq %rdi, %rsi +; CHECK-NEXT: movq %rsp, %rdx +; CHECK-NEXT: movl $16, %edi +; CHECK-NEXT: movl $2, %ecx +; CHECK-NEXT: callq __atomic_load@PLT +; CHECK-NEXT: movaps (%rsp), %xmm0 +; CHECK-NEXT: addq $24, %rsp +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: retq + %ret = load atomic <2 x double>, ptr %src acquire, align 4 + ret <2 x double> %ret +} + +define <2 x half> @load_atomic_vector_half(ptr %src) { +; CHECK-LABEL: load_atomic_vector_half: +; CHECK: # %bb.0: +; CHECK-NEXT: movl (%rdi), %eax +; CHECK-NEXT: movd %eax, %xmm0 +; CHECK-NEXT: retq + %ret = load atomic <2 x half>, ptr %src acquire, align 4 + ret <2 x half> %ret +} + +define <2 x float> @load_atomic_vector_bfloat(ptr %src) { +; CHECK-LABEL: load_atomic_vector_bfloat: ; CHECK: # %bb.0: ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 @@ -36,3 +91,22 @@ define <2 x float> @load_atomic_vector_float2(ptr %src) { %ret = load atomic <2 x float>, ptr %src acquire, align 4 ret <2 x float> %ret } + +define <2 x fp128> @load_atomic_vector_fp128(ptr %src) { +; CHECK-LABEL: load_atomic_vector_fp128: +; CHECK: # %bb.0: +; CHECK-NEXT: subq $40, %rsp +; CHECK-NEXT: .cfi_def_cfa_offset 48 +; CHECK-NEXT: movq %rdi, %rsi +; CHECK-NEXT: movq %rsp, %rdx +; CHECK-NEXT: movl $32, %edi +; CHECK-NEXT: movl $2, %ecx +; CHECK-NEXT: callq __atomic_load@PLT +; CHECK-NEXT: movaps (%rsp), %xmm0 +; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 +; CHECK-NEXT: addq $40, %rsp +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: retq + %ret = load atomic <2 x fp128>, ptr %src acquire, align 4 + ret <2 x fp128> %ret +} diff --git a/llvm/test/Transforms/AtomicExpand/atomicvec-float.ll b/llvm/test/Transforms/AtomicExpand/atomicvec-float.ll index 61a78f8c5cf769..b2a32178d6780c 100644 --- a/llvm/test/Transforms/AtomicExpand/atomicvec-float.ll +++ b/llvm/test/Transforms/AtomicExpand/atomicvec-float.ll @@ -1,19 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 ; RUN: opt < %s --mtriple=x86_64 --passes=atomic-expand -S -o - | FileCheck %s -define float @load_atomic_float(ptr %src) { -; CHECK-LABEL: define float @load_atomic_float( -; CHECK-SAME: ptr [[SRC:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i32, ptr [[SRC]] acquire, align 4 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float -; CHECK-NEXT: ret float [[TMP2]] -; - %ret = load atomic float, ptr %src acquire, align 4 - ret float %ret -} - -define <1 x float> @load_atomic_vector_float1(ptr %src) { -; CHECK-LABEL: define <1 x float> @load_atomic_vector_float1( +define <1 x float> @load_atomic_vector1_float(ptr %src) { +; CHECK-LABEL: define <1 x float> @load_atomic_vector1_float( ; CHECK-SAME: ptr [[SRC:%.*]]) { ; CHECK-NEXT: [[TMP1:%.*]] = load atomic i32, ptr [[SRC]] acquire, align 4 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to <1 x float> @@ -23,8 +12,8 @@ define <1 x float> @load_atomic_vector_float1(ptr %src) { ret <1 x float> %ret } -define <2 x float> @load_atomic_vector_float2(ptr %src) { -; CHECK-LABEL: define <2 x float> @load_atomic_vector_float2( +define <2 x float> @load_atomic_vector2_float(ptr %src) { +; CHECK-LABEL: define <2 x float> @load_atomic_vector2_float( ; CHECK-SAME: ptr [[SRC:%.*]]) { ; CHECK-NEXT: [[TMP1:%.*]] = alloca <2 x float>, align 8 ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr [[TMP1]]) @@ -36,3 +25,67 @@ define <2 x float> @load_atomic_vector_float2(ptr %src) { %ret = load atomic <2 x float>, ptr %src acquire, align 4 ret <2 x float> %ret } + +define <1 x double> @load_atomic_vector1_double(ptr %src) { +; CHECK-LABEL: define <1 x double> @load_atomic_vector1_double( +; CHECK-SAME: ptr [[SRC:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <1 x double>, align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr [[TMP1]]) +; CHECK-NEXT: call void @__atomic_load(i64 8, ptr [[SRC]], ptr [[TMP1]], i32 2) +; CHECK-NEXT: [[TMP2:%.*]] = load <1 x double>, ptr [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 8, ptr [[TMP1]]) +; CHECK-NEXT: ret <1 x double> [[TMP2]] +; + %ret = load atomic <1 x double>, ptr %src acquire, align 4 + ret <1 x double> %ret +} + +define <2 x double> @load_atomic_vector2_double(ptr %src) { +; CHECK-LABEL: define <2 x double> @load_atomic_vector2_double( +; CHECK-SAME: ptr [[SRC:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <2 x double>, align 16 +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[TMP1]]) +; CHECK-NEXT: call void @__atomic_load(i64 16, ptr [[SRC]], ptr [[TMP1]], i32 2) +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[TMP1]], align 16 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[TMP1]]) +; CHECK-NEXT: ret <2 x double> [[TMP2]] +; + %ret = load atomic <2 x double>, ptr %src acquire, align 4 + ret <2 x double> %ret +} + +define <2 x half> @load_atomic_vector_half(ptr %src) { +; CHECK-LABEL: define <2 x half> @load_atomic_vector_half( +; CHECK-SAME: ptr [[SRC:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = load atomic i32, ptr [[SRC]] acquire, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to <2 x half> +; CHECK-NEXT: ret <2 x half> [[TMP2]] +; + %ret = load atomic <2 x half>, ptr %src acquire, align 4 + ret <2 x half> %ret +} + +define <2 x bfloat> @load_atomic_vector_bfloat(ptr %src) { +; CHECK-LABEL: define <2 x bfloat> @load_atomic_vector_bfloat( +; CHECK-SAME: ptr [[SRC:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = load atomic i32, ptr [[SRC]] acquire, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to <2 x bfloat> +; CHECK-NEXT: ret <2 x bfloat> [[TMP2]] +; + %ret = load atomic <2 x bfloat>, ptr %src acquire, align 4 + ret <2 x bfloat> %ret +} + +define <2 x fp128> @load_atomic_vector_fp128(ptr %src) { +; CHECK-LABEL: define <2 x fp128> @load_atomic_vector_fp128( +; CHECK-SAME: ptr [[SRC:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <2 x fp128>, align 16 +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 32, ptr [[TMP1]]) +; CHECK-NEXT: call void @__atomic_load(i64 32, ptr [[SRC]], ptr [[TMP1]], i32 2) +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x fp128>, ptr [[TMP1]], align 16 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 32, ptr [[TMP1]]) +; CHECK-NEXT: ret <2 x fp128> [[TMP2]] +; + %ret = load atomic <2 x fp128>, ptr %src acquire, align 4 + ret <2 x fp128> %ret +}