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[SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic <1 x T>` is not valid. This change legalizes vector types of atomic load via scalarization in SelectionDAG so that it can, for example, translate from `v1i32` to `i32`. commit-id:5c36cc8c
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3 files changed

+135
-2
lines changed

3 files changed

+135
-2
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -874,6 +874,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
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SDValue ScalarizeVecRes_UnaryOpWithExtraInput(SDNode *N);
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SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
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SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
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SDValue ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N);
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SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
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SDValue ScalarizeVecRes_VSELECT(SDNode *N);
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SDValue ScalarizeVecRes_SELECT(SDNode *N);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -64,6 +64,9 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
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R = ScalarizeVecRes_UnaryOpWithExtraInput(N);
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break;
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case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
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case ISD::ATOMIC_LOAD:
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R = ScalarizeVecRes_ATOMIC_LOAD(cast<AtomicSDNode>(N));
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break;
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case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
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case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
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case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
@@ -458,6 +461,18 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
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return Op;
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_ATOMIC_LOAD(AtomicSDNode *N) {
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SDValue Result = DAG.getAtomicLoad(
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ISD::NON_EXTLOAD, SDLoc(N), N->getMemoryVT().getVectorElementType(),
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N->getValueType(0).getVectorElementType(), N->getChain(), N->getBasePtr(),
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N->getMemOperand());
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// Legalize the chain result - switch anything that used the old chain to
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// use the new one.
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ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
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return Result;
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
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assert(N->isUnindexed() && "Indexed vector load?");
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‎llvm/test/CodeGen/X86/atomic-load-store.ll‎

Lines changed: 119 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK3
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; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 | FileCheck %s --check-prefixes=CHECK,CHECK0
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55
define void @test1(ptr %ptr, i32 %val1) {
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; CHECK-LABEL: test1:
@@ -28,3 +28,120 @@ define i32 @test3(ptr %ptr) {
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%val = load atomic i32, ptr %ptr seq_cst, align 4
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ret i32 %val
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}
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define <1 x i32> @atomic_vec1_i32(ptr %x) {
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; CHECK-LABEL: atomic_vec1_i32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: retq
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%ret = load atomic <1 x i32>, ptr %x acquire, align 4
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ret <1 x i32> %ret
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}
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define <1 x i8> @atomic_vec1_i8(ptr %x) {
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; CHECK3-LABEL: atomic_vec1_i8:
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; CHECK3: ## %bb.0:
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; CHECK3-NEXT: movzbl (%rdi), %eax
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; CHECK3-NEXT: retq
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;
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; CHECK0-LABEL: atomic_vec1_i8:
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; CHECK0: ## %bb.0:
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; CHECK0-NEXT: movb (%rdi), %al
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; CHECK0-NEXT: retq
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%ret = load atomic <1 x i8>, ptr %x acquire, align 1
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ret <1 x i8> %ret
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}
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define <1 x i16> @atomic_vec1_i16(ptr %x) {
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; CHECK3-LABEL: atomic_vec1_i16:
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; CHECK3: ## %bb.0:
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; CHECK3-NEXT: movzwl (%rdi), %eax
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; CHECK3-NEXT: retq
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;
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; CHECK0-LABEL: atomic_vec1_i16:
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; CHECK0: ## %bb.0:
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; CHECK0-NEXT: movw (%rdi), %ax
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; CHECK0-NEXT: retq
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%ret = load atomic <1 x i16>, ptr %x acquire, align 2
66+
ret <1 x i16> %ret
67+
}
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69+
define <1 x i32> @atomic_vec1_i8_zext(ptr %x) {
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; CHECK3-LABEL: atomic_vec1_i8_zext:
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; CHECK3: ## %bb.0:
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; CHECK3-NEXT: movzbl (%rdi), %eax
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; CHECK3-NEXT: movzbl %al, %eax
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; CHECK3-NEXT: retq
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;
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; CHECK0-LABEL: atomic_vec1_i8_zext:
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; CHECK0: ## %bb.0:
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; CHECK0-NEXT: movb (%rdi), %al
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; CHECK0-NEXT: movzbl %al, %eax
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; CHECK0-NEXT: retq
81+
%ret = load atomic <1 x i8>, ptr %x acquire, align 1
82+
%zret = zext <1 x i8> %ret to <1 x i32>
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ret <1 x i32> %zret
84+
}
85+
86+
define <1 x i64> @atomic_vec1_i16_sext(ptr %x) {
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; CHECK3-LABEL: atomic_vec1_i16_sext:
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; CHECK3: ## %bb.0:
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; CHECK3-NEXT: movzwl (%rdi), %eax
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; CHECK3-NEXT: movswq %ax, %rax
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; CHECK3-NEXT: retq
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;
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; CHECK0-LABEL: atomic_vec1_i16_sext:
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; CHECK0: ## %bb.0:
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; CHECK0-NEXT: movw (%rdi), %ax
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; CHECK0-NEXT: movswq %ax, %rax
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; CHECK0-NEXT: retq
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%ret = load atomic <1 x i16>, ptr %x acquire, align 2
99+
%sret = sext <1 x i16> %ret to <1 x i64>
100+
ret <1 x i64> %sret
101+
}
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103+
define <1 x ptr addrspace(270)> @atomic_vec1_ptr270(ptr %x) {
104+
; CHECK-LABEL: atomic_vec1_ptr270:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: retq
108+
%ret = load atomic <1 x ptr addrspace(270)>, ptr %x acquire, align 4
109+
ret <1 x ptr addrspace(270)> %ret
110+
}
111+
112+
define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
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; CHECK3-LABEL: atomic_vec1_bfloat:
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; CHECK3: ## %bb.0:
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; CHECK3-NEXT: movzwl (%rdi), %eax
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; CHECK3-NEXT: pinsrw $0, %eax, %xmm0
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; CHECK3-NEXT: retq
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;
119+
; CHECK0-LABEL: atomic_vec1_bfloat:
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; CHECK0: ## %bb.0:
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; CHECK0-NEXT: movw (%rdi), %cx
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; CHECK0-NEXT: ## implicit-def: $eax
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; CHECK0-NEXT: movw %cx, %ax
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; CHECK0-NEXT: ## implicit-def: $xmm0
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; CHECK0-NEXT: pinsrw $0, %eax, %xmm0
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; CHECK0-NEXT: retq
127+
%ret = load atomic <1 x bfloat>, ptr %x acquire, align 2
128+
ret <1 x bfloat> %ret
129+
}
130+
131+
define <1 x ptr> @atomic_vec1_ptr_align(ptr %x) nounwind {
132+
; CHECK-LABEL: atomic_vec1_ptr_align:
133+
; CHECK: ## %bb.0:
134+
; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: retq
136+
%ret = load atomic <1 x ptr>, ptr %x acquire, align 8
137+
ret <1 x ptr> %ret
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}
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140+
define <1 x i64> @atomic_vec1_i64_align(ptr %x) nounwind {
141+
; CHECK-LABEL: atomic_vec1_i64_align:
142+
; CHECK: ## %bb.0:
143+
; CHECK-NEXT: movq (%rdi), %rax
144+
; CHECK-NEXT: retq
145+
%ret = load atomic <1 x i64>, ptr %x acquire, align 8
146+
ret <1 x i64> %ret
147+
}

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