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[GlobalISel] Support saturated truncate
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9 files changed

+306
-7
lines changed

9 files changed

+306
-7
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -726,6 +726,25 @@ class CombinerHelper {
726726
bool matchUMulHToLShr(MachineInstr &MI) const;
727727
void applyUMulHToLShr(MachineInstr &MI) const;
728728

729+
// Combine trunc(smin(smax(x, C1), C2)) -> truncssat_s(x)
730+
// or trunc(smax(smin(x, C2), C1)) -> truncssat_s(x).
731+
bool matchTruncSSatS(MachineInstr &MI, Register &MatchInfo) const;
732+
void applyTruncSSatS(MachineInstr &MI, Register &MatchInfo) const;
733+
734+
// Combine trunc(smin(smax(x, 0), C)) -> truncssat_u(x)
735+
// or trunc(smax(smin(x, C), 0)) -> truncssat_u(x)
736+
// or trunc(umin(smax(x, 0), C)) -> truncssat_u(x)
737+
bool matchTruncSSatU(MachineInstr &MI, Register &MatchInfo) const;
738+
void applyTruncSSatU(MachineInstr &MI, Register &MatchInfo) const;
739+
740+
// Combine trunc(umin(x, C)) -> truncusat_u(x).
741+
bool matchTruncUSatU(MachineInstr &MI, Register &MatchInfo) const;
742+
void applyTruncUSatU(MachineInstr &MI, Register &MatchInfo) const;
743+
744+
// Combine truncusat_u(fptoui(x)) -> fptoui_sat(x)
745+
bool matchTruncUSatUToFPTOUISat(MachineInstr &MI, Register &MatchInfo) const;
746+
void applyTruncUSatUToFPTOUISat(MachineInstr &MI, Register &MatchInfo) const;
747+
729748
/// Try to transform \p MI by using all of the above
730749
/// combine functions. Returns true if changed.
731750
bool tryCombine(MachineInstr &MI) const;

‎llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -874,6 +874,9 @@ class GCastOp : public GenericMachineInstr {
874874
case TargetOpcode::G_SEXT:
875875
case TargetOpcode::G_SITOFP:
876876
case TargetOpcode::G_TRUNC:
877+
case TargetOpcode::G_TRUNC_SSAT_S:
878+
case TargetOpcode::G_TRUNC_SSAT_U:
879+
case TargetOpcode::G_TRUNC_USAT_U:
877880
case TargetOpcode::G_UITOFP:
878881
case TargetOpcode::G_ZEXT:
879882
case TargetOpcode::G_ANYEXT:
@@ -916,6 +919,30 @@ class GTrunc : public GCastOp {
916919
};
917920
};
918921

922+
/// Represents a saturated trunc from a signed input to a signed result.
923+
class GTruncSSatS : public GCastOp {
924+
public:
925+
static bool classof(const MachineInstr *MI) {
926+
return MI->getOpcode() == TargetOpcode::G_TRUNC_SSAT_S;
927+
};
928+
};
929+
930+
/// Represents a saturated trunc from a signed input to an unsigned result.
931+
class GTruncSSatU : public GCastOp {
932+
public:
933+
static bool classof(const MachineInstr *MI) {
934+
return MI->getOpcode() == TargetOpcode::G_TRUNC_SSAT_U;
935+
};
936+
};
937+
938+
/// Represents a saturated trunc from an unsigned input to an unsigned result.
939+
class GTruncUSatU : public GCastOp {
940+
public:
941+
static bool classof(const MachineInstr *MI) {
942+
return MI->getOpcode() == TargetOpcode::G_TRUNC_USAT_U;
943+
};
944+
};
945+
919946
/// Represents a vscale.
920947
class GVScale : public GenericMachineInstr {
921948
public:

‎llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -709,6 +709,18 @@ m_GFPTrunc(const SrcTy &Src) {
709709
return UnaryOp_match<SrcTy, TargetOpcode::G_FPTRUNC>(Src);
710710
}
711711

712+
template <typename SrcTy>
713+
inline UnaryOp_match<SrcTy, TargetOpcode::G_FPTOSI>
714+
m_GFPToSI(const SrcTy &Src) {
715+
return UnaryOp_match<SrcTy, TargetOpcode::G_FPTOSI>(Src);
716+
}
717+
718+
template <typename SrcTy>
719+
inline UnaryOp_match<SrcTy, TargetOpcode::G_FPTOUI>
720+
m_GFPToUI(const SrcTy &Src) {
721+
return UnaryOp_match<SrcTy, TargetOpcode::G_FPTOUI>(Src);
722+
}
723+
712724
template <typename SrcTy>
713725
inline UnaryOp_match<SrcTy, TargetOpcode::G_FABS> m_GFabs(const SrcTy &Src) {
714726
return UnaryOp_match<SrcTy, TargetOpcode::G_FABS>(Src);

‎llvm/include/llvm/Target/GlobalISel/Combine.td

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1242,6 +1242,32 @@ def mulh_to_lshr : GICombineRule<
12421242

12431243
def mulh_combines : GICombineGroup<[mulh_to_lshr]>;
12441244

1245+
def trunc_ssats : GICombineRule<
1246+
(defs root:$root, register_matchinfo:$matchinfo),
1247+
(match (G_TRUNC $dst, $src):$root,
1248+
[{ return Helper.matchTruncSSatS(*${root}, ${matchinfo}); }]),
1249+
(apply [{ Helper.applyTruncSSatS(*${root}, ${matchinfo}); }])>;
1250+
1251+
def trunc_ssatu : GICombineRule<
1252+
(defs root:$root, register_matchinfo:$matchinfo),
1253+
(match (G_TRUNC $dst, $src):$root,
1254+
[{ return Helper.matchTruncSSatU(*${root}, ${matchinfo}); }]),
1255+
(apply [{ Helper.applyTruncSSatU(*${root}, ${matchinfo}); }])>;
1256+
1257+
def trunc_usatu : GICombineRule<
1258+
(defs root:$root, register_matchinfo:$matchinfo),
1259+
(match (G_TRUNC $dst, $src):$root,
1260+
[{ return Helper.matchTruncUSatU(*${root}, ${matchinfo}); }]),
1261+
(apply [{ Helper.applyTruncUSatU(*${root}, ${matchinfo}); }])>;
1262+
1263+
def truncusatu_to_fptouisat : GICombineRule<
1264+
(defs root:$root, register_matchinfo:$matchinfo),
1265+
(match (G_TRUNC_USAT_U $dst, $src):$root,
1266+
[{ return Helper.matchTruncUSatUToFPTOUISat(*${root}, ${matchinfo}); }]),
1267+
(apply [{ Helper.applyTruncUSatUToFPTOUISat(*${root}, ${matchinfo}); }])>;
1268+
1269+
def truncsat_combines : GICombineGroup<[trunc_ssats, trunc_ssatu, trunc_usatu, truncusatu_to_fptouisat]>;
1270+
12451271
def redundant_neg_operands: GICombineRule<
12461272
(defs root:$root, build_fn_matchinfo:$matchinfo),
12471273
(match (wip_match_opcode G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMAD, G_FMA):$root,
@@ -2066,7 +2092,7 @@ def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
20662092
fsub_to_fneg, commute_constant_to_rhs, match_ands, match_ors,
20672093
simplify_neg_minmax, combine_concat_vector,
20682094
sext_trunc, zext_trunc, prefer_sign_combines, shuffle_combines,
2069-
combine_use_vector_truncate, merge_combines, overflow_combines]>;
2095+
combine_use_vector_truncate, merge_combines, overflow_combines, truncsat_combines]>;
20702096

20712097
// A combine group used to for prelegalizer combiners at -O0. The combines in
20722098
// this group have been selected based on experiments to balance code size and

‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,9 @@ def : GINodeEquiv<G_SEXT, sext>;
5151
def : GINodeEquiv<G_SEXT_INREG, sext_inreg>;
5252
def : GINodeEquiv<G_ZEXT, zext>;
5353
def : GINodeEquiv<G_TRUNC, trunc>;
54+
def : GINodeEquiv<G_TRUNC_SSAT_S, truncssat_s>;
55+
def : GINodeEquiv<G_TRUNC_SSAT_U, truncssat_u>;
56+
def : GINodeEquiv<G_TRUNC_USAT_U, truncusat_u>;
5457
def : GINodeEquiv<G_BITCAST, bitconvert>;
5558
// G_INTTOPTR - SelectionDAG has no equivalent.
5659
// G_PTRTOINT - SelectionDAG has no equivalent.

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 128 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5844,6 +5844,134 @@ void CombinerHelper::applyUMulHToLShr(MachineInstr &MI) const {
58445844
MI.eraseFromParent();
58455845
}
58465846

5847+
bool CombinerHelper::matchTruncSSatS(MachineInstr &MI,
5848+
Register &MatchInfo) const {
5849+
Register Dst = MI.getOperand(0).getReg();
5850+
Register Src = MI.getOperand(1).getReg();
5851+
LLT DstTy = MRI.getType(Dst);
5852+
LLT SrcTy = MRI.getType(Src);
5853+
unsigned NumDstBits = DstTy.getScalarSizeInBits();
5854+
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
5855+
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
5856+
5857+
APInt MinConst, MaxConst;
5858+
APInt SignedMax = APInt::getSignedMaxValue(NumDstBits).sext(NumSrcBits);
5859+
APInt SignedMin = APInt::getSignedMinValue(NumDstBits).sext(NumSrcBits);
5860+
5861+
if (isLegal({TargetOpcode::G_TRUNC_SSAT_S, {DstTy, SrcTy}})) {
5862+
if (mi_match(Src, MRI,
5863+
m_GSMin(m_GSMax(m_Reg(MatchInfo), m_ICstOrSplat(MinConst)),
5864+
m_ICstOrSplat(MaxConst))) &&
5865+
APInt::isSameValue(MinConst, SignedMin) &&
5866+
APInt::isSameValue(MaxConst, SignedMax))
5867+
return true;
5868+
if (mi_match(Src, MRI,
5869+
m_GSMax(m_GSMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst)),
5870+
m_ICstOrSplat(MinConst))) &&
5871+
APInt::isSameValue(MinConst, SignedMin) &&
5872+
APInt::isSameValue(MaxConst, SignedMax))
5873+
return true;
5874+
}
5875+
return false;
5876+
}
5877+
5878+
void CombinerHelper::applyTruncSSatS(MachineInstr &MI,
5879+
Register &MatchInfo) const {
5880+
Register Dst = MI.getOperand(0).getReg();
5881+
Builder.buildTruncSSatS(Dst, MatchInfo);
5882+
MI.eraseFromParent();
5883+
}
5884+
5885+
bool CombinerHelper::matchTruncSSatU(MachineInstr &MI,
5886+
Register &MatchInfo) const {
5887+
Register Dst = MI.getOperand(0).getReg();
5888+
Register Src = MI.getOperand(1).getReg();
5889+
LLT DstTy = MRI.getType(Dst);
5890+
LLT SrcTy = MRI.getType(Src);
5891+
unsigned NumDstBits = DstTy.getScalarSizeInBits();
5892+
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
5893+
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
5894+
5895+
APInt MaxConst;
5896+
APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
5897+
5898+
if (isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
5899+
if (mi_match(Src, MRI,
5900+
m_GSMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
5901+
m_ICstOrSplat(MaxConst))) &&
5902+
APInt::isSameValue(MaxConst, UnsignedMax))
5903+
return true;
5904+
if (mi_match(Src, MRI,
5905+
m_GSMax(m_GSMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst)),
5906+
m_SpecificICstOrSplat(0))) &&
5907+
APInt::isSameValue(MaxConst, UnsignedMax))
5908+
return true;
5909+
if (mi_match(Src, MRI,
5910+
m_GUMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
5911+
m_ICstOrSplat(MaxConst))) &&
5912+
APInt::isSameValue(MaxConst, UnsignedMax))
5913+
return true;
5914+
}
5915+
return false;
5916+
}
5917+
5918+
void CombinerHelper::applyTruncSSatU(MachineInstr &MI,
5919+
Register &MatchInfo) const {
5920+
Register Dst = MI.getOperand(0).getReg();
5921+
Builder.buildTruncSSatU(Dst, MatchInfo);
5922+
MI.eraseFromParent();
5923+
}
5924+
5925+
bool CombinerHelper::matchTruncUSatU(MachineInstr &MI,
5926+
Register &MatchInfo) const {
5927+
Register Dst = MI.getOperand(0).getReg();
5928+
Register Src = MI.getOperand(1).getReg();
5929+
LLT DstTy = MRI.getType(Dst);
5930+
LLT SrcTy = MRI.getType(Src);
5931+
unsigned NumDstBits = DstTy.getScalarSizeInBits();
5932+
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
5933+
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
5934+
5935+
APInt MaxConst;
5936+
APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
5937+
5938+
if (isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
5939+
if (mi_match(Src, MRI,
5940+
m_GUMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst))) &&
5941+
APInt::isSameValue(MaxConst, UnsignedMax))
5942+
return true;
5943+
}
5944+
return false;
5945+
}
5946+
5947+
void CombinerHelper::applyTruncUSatU(MachineInstr &MI,
5948+
Register &MatchInfo) const {
5949+
Register Dst = MI.getOperand(0).getReg();
5950+
Builder.buildTruncUSatU(Dst, MatchInfo);
5951+
MI.eraseFromParent();
5952+
}
5953+
5954+
bool CombinerHelper::matchTruncUSatUToFPTOUISat(MachineInstr &MI,
5955+
Register &MatchInfo) const {
5956+
Register Dst = MI.getOperand(0).getReg();
5957+
Register Src = MI.getOperand(1).getReg();
5958+
LLT DstTy = MRI.getType(Dst);
5959+
LLT SrcTy = MRI.getType(Src);
5960+
5961+
if (isLegalOrBeforeLegalizer({TargetOpcode::G_FPTOUI_SAT, {DstTy, SrcTy}})) {
5962+
if (mi_match(Src, MRI, m_GFPToUI((m_Reg(MatchInfo)))))
5963+
return true;
5964+
}
5965+
return false;
5966+
}
5967+
5968+
void CombinerHelper::applyTruncUSatUToFPTOUISat(MachineInstr &MI,
5969+
Register &MatchInfo) const {
5970+
Register Dst = MI.getOperand(0).getReg();
5971+
Builder.buildFPTOUI_SAT(Dst, MatchInfo);
5972+
MI.eraseFromParent();
5973+
}
5974+
58475975
bool CombinerHelper::matchRedundantNegOperands(MachineInstr &MI,
58485976
BuildFnTy &MatchInfo) const {
58495977
unsigned Opc = MI.getOpcode();

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -797,6 +797,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
797797
.clampMinNumElements(0, s16, 4)
798798
.alwaysLegal();
799799

800+
getActionDefinitionsBuilder({G_TRUNC_SSAT_S, G_TRUNC_SSAT_U, G_TRUNC_USAT_U})
801+
.legalFor({{v8s8, v8s16}, {v4s16, v4s32}, {v2s32, v2s64}});
802+
800803
getActionDefinitionsBuilder(G_SEXT_INREG)
801804
.legalFor({s32, s64})
802805
.legalFor(PackedVectorAllTypeList)

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -321,14 +321,16 @@
321321
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
322322
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
323323
# DEBUG-NEXT: G_TRUNC_SSAT_S (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
324-
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
325-
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
324+
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
325+
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
326326
# DEBUG-NEXT: G_TRUNC_SSAT_U (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
327-
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
328-
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
327+
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
328+
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
329+
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
329330
# DEBUG-NEXT: G_TRUNC_USAT_U (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
330-
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
331-
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
331+
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
332+
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
333+
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
332334
# DEBUG-NEXT: G_CONSTANT (opcode {{[0-9]+}}): 1 type index, 0 imm indices
333335
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
334336
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK

‎llvm/test/CodeGen/AArch64/truncsat.ll

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4+
5+
6+
define <4 x i16> @ssats_1(<4 x i32> %x) {
7+
; CHECK-LABEL: ssats_1:
8+
; CHECK: // %bb.0: // %entry
9+
; CHECK-NEXT: sqxtn v0.4h, v0.4s
10+
; CHECK-NEXT: ret
11+
entry:
12+
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %x, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
13+
%spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
14+
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
15+
ret <4 x i16> %conv6
16+
}
17+
18+
define <4 x i16> @ssats_2(<4 x i32> %x) {
19+
; CHECK-LABEL: ssats_2:
20+
; CHECK: // %bb.0: // %entry
21+
; CHECK-NEXT: sqxtn v0.4h, v0.4s
22+
; CHECK-NEXT: ret
23+
entry:
24+
%spec.store.select = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
25+
%spec.store.select7 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
26+
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
27+
ret <4 x i16> %conv6
28+
}
29+
30+
define <4 x i16> @ssatu_1(<4 x i32> %x) {
31+
; CHECK-LABEL: ssatu_1:
32+
; CHECK: // %bb.0: // %entry
33+
; CHECK-NEXT: sqxtun v0.4h, v0.4s
34+
; CHECK-NEXT: ret
35+
entry:
36+
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %x, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
37+
%spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer)
38+
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
39+
ret <4 x i16> %conv6
40+
}
41+
42+
define <4 x i16> @ssatu_2(<4 x i32> %x) {
43+
; CHECK-LABEL: ssatu_2:
44+
; CHECK: // %bb.0: // %entry
45+
; CHECK-NEXT: sqxtun v0.4h, v0.4s
46+
; CHECK-NEXT: ret
47+
entry:
48+
%spec.store.select = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> zeroinitializer)
49+
%spec.store.select7 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
50+
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
51+
ret <4 x i16> %conv6
52+
}
53+
54+
define <4 x i16> @ssatu_3(<4 x i32> %x) {
55+
; CHECK-LABEL: ssatu_3:
56+
; CHECK: // %bb.0: // %entry
57+
; CHECK-NEXT: sqxtun v0.4h, v0.4s
58+
; CHECK-NEXT: ret
59+
entry:
60+
%spec.store.select = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> zeroinitializer)
61+
%spec.store.select7 = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
62+
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
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ret <4 x i16> %conv6
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}
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define <4 x i16> @usatu(<4 x i32> %x) {
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; CHECK-LABEL: usatu:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: uqxtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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entry:
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%spec.store.select = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %x, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
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%conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>
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ret <4 x i16> %conv6
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK-GI: {{.*}}
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; CHECK-SD: {{.*}}

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