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[InstCombine] Add missing patterns for scmp and ucmp
Fixes: #146178
1 parent 8e5536a commit 7ca8041

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2 files changed

+176
-20
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2 files changed

+176
-20
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

Lines changed: 130 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3635,6 +3635,12 @@ static Instruction *foldBitCeil(SelectInst &SI, IRBuilderBase &Builder,
36353635
// (x < y) ? -1 : zext(x > y)
36363636
// (x > y) ? 1 : sext(x != y)
36373637
// (x > y) ? 1 : sext(x < y)
3638+
// (x == y) ? 0 : (x > y ? 1 : -1)
3639+
// (x == y) ? 0 : (x < y ? -1 : 1)
3640+
// Special cases: x == C ? 0 : (x > C - 1 ? 1 : -1) and
3641+
// Special cases: x == C ? 0 : (x < C - 1 ? -1 : 1) and
3642+
// Special cases: x == C ? 0 : (x > C + 1 ? 1 : -1) and
3643+
// Special cases: x == C ? 0 : (x < C + 1 ? -1 : 1)
36383644
// Into ucmp/scmp(x, y), where signedness is determined by the signedness
36393645
// of the comparison in the original sequence.
36403646
Instruction *InstCombinerImpl::foldSelectToCmp(SelectInst &SI) {
@@ -3680,10 +3686,12 @@ Instruction *InstCombinerImpl::foldSelectToCmp(SelectInst &SI) {
36803686
Pred = ICmpInst::getSwappedPredicate(Pred);
36813687
std::swap(LHS, RHS);
36823688
}
3689+
36833690
bool IsSigned = ICmpInst::isSigned(Pred);
36843691

36853692
bool Replace = false;
36863693
CmpPredicate ExtendedCmpPredicate;
3694+
36873695
// (x < y) ? -1 : zext(x != y)
36883696
// (x < y) ? -1 : zext(x > y)
36893697
if (ICmpInst::isLT(Pred) && match(TV, m_AllOnes()) &&
@@ -3703,34 +3711,134 @@ Instruction *InstCombinerImpl::foldSelectToCmp(SelectInst &SI) {
37033711
Replace = true;
37043712

37053713
// (x == y) ? 0 : (x > y ? 1 : -1)
3714+
// (x == y) ? 0 : (x < y ? -1 : 1)
37063715
CmpPredicate FalseBranchSelectPredicate;
37073716
const APInt *InnerTV, *InnerFV;
37083717
if (Pred == ICmpInst::ICMP_EQ && match(TV, m_Zero()) &&
37093718
match(FV, m_Select(m_c_ICmp(FalseBranchSelectPredicate, m_Specific(LHS),
37103719
m_Specific(RHS)),
37113720
m_APInt(InnerTV), m_APInt(InnerFV)))) {
3712-
if (!ICmpInst::isGT(FalseBranchSelectPredicate)) {
3713-
FalseBranchSelectPredicate =
3714-
ICmpInst::getSwappedPredicate(FalseBranchSelectPredicate);
3715-
std::swap(LHS, RHS);
3721+
3722+
// Check if we need to canonicalize the comparison predicate
3723+
bool PredicateSwapped = false;
3724+
if (!ICmpInst::isGT(FalseBranchSelectPredicate) && !ICmpInst::isLT(FalseBranchSelectPredicate)) {
3725+
// Not a GT or LT, nothing to do
3726+
} else if (!ICmpInst::isGT(FalseBranchSelectPredicate)) {
3727+
// We have LT, see if swapping gives us GT
3728+
CmpPredicate SwappedPred = ICmpInst::getSwappedPredicate(FalseBranchSelectPredicate);
3729+
if (ICmpInst::isGT(SwappedPred)) {
3730+
FalseBranchSelectPredicate = SwappedPred;
3731+
PredicateSwapped = true;
3732+
}
37163733
}
37173734

3718-
if (!InnerTV->isOne()) {
3735+
// Check if we need to canonicalize the select values
3736+
bool ValuesSwapped = false;
3737+
if (!InnerTV->isOne() && InnerFV->isOne()) {
37193738
std::swap(InnerTV, InnerFV);
3720-
std::swap(LHS, RHS);
3739+
ValuesSwapped = true;
37213740
}
37223741

3742+
// Handle (x == y) ? 0 : (x > y ? 1 : -1) or its equivalent forms
37233743
if (ICmpInst::isGT(FalseBranchSelectPredicate) && InnerTV->isOne() &&
37243744
InnerFV->isAllOnes()) {
37253745
IsSigned = ICmpInst::isSigned(FalseBranchSelectPredicate);
3746+
// If we swapped the predicate XOR swapped the values, we need to swap LHS/RHS for scmp
3747+
if (PredicateSwapped != ValuesSwapped) {
3748+
std::swap(LHS, RHS);
3749+
}
3750+
Replace = true;
3751+
}
3752+
// Handle (x == y) ? 0 : (x < y ? -1 : 1) or its equivalent forms
3753+
else if (ICmpInst::isLT(FalseBranchSelectPredicate) && InnerTV->isAllOnes() &&
3754+
InnerFV->isOne()) {
3755+
IsSigned = ICmpInst::isSigned(FalseBranchSelectPredicate);
3756+
// For LT pattern, operand order is already correct
37263757
Replace = true;
37273758
}
37283759
}
37293760

3761+
3762+
3763+
// Special cases: x == C ? 0 : (x > C-1 ? 1 : -1), etc.
3764+
if (Pred == ICmpInst::ICMP_EQ && match(TV, m_Zero())) {
3765+
Value *X;
3766+
const APInt *C;
3767+
if (match(LHS, m_Value(X)) && match(RHS, m_APInt(C))) {
3768+
3769+
// Match the nested select - no canonicalization, match each pattern
3770+
// directly
3771+
CmpPredicate InnerPred;
3772+
Value *InnerLHS, *InnerRHS;
3773+
const APInt *InnerTV, *InnerFV;
3774+
if (match(FV, m_Select(
3775+
m_ICmp(InnerPred, m_Value(InnerLHS), m_Value(InnerRHS)),
3776+
m_APInt(InnerTV), m_APInt(InnerFV)))) {
3777+
3778+
// x == C ? 0 : (x > C-1 ? 1 : -1)
3779+
if (ICmpInst::isGT(InnerPred) && InnerTV->isOne() &&
3780+
InnerFV->isAllOnes()) {
3781+
IsSigned = ICmpInst::isSigned(InnerPred);
3782+
bool CanSubOne = IsSigned ? !C->isMinSignedValue() : !C->isMinValue();
3783+
if (CanSubOne) {
3784+
APInt Cminus1 = *C - 1;
3785+
if ((InnerLHS == X && match(InnerRHS, m_SpecificInt(Cminus1))) ||
3786+
(InnerRHS == X && match(InnerLHS, m_SpecificInt(Cminus1)))) {
3787+
Replace = true;
3788+
}
3789+
}
3790+
}
3791+
3792+
// x == C ? 0 : (x < C-1 ? -1 : 1)
3793+
if (ICmpInst::isLT(InnerPred) && InnerTV->isAllOnes() &&
3794+
InnerFV->isOne()) {
3795+
IsSigned = ICmpInst::isSigned(InnerPred);
3796+
bool CanSubOne = IsSigned ? !C->isMinSignedValue() : !C->isMinValue();
3797+
if (CanSubOne) {
3798+
APInt Cminus1 = *C - 1;
3799+
if ((InnerLHS == X && match(InnerRHS, m_SpecificInt(Cminus1))) ||
3800+
(InnerRHS == X && match(InnerLHS, m_SpecificInt(Cminus1)))) {
3801+
Replace = true;
3802+
}
3803+
}
3804+
}
3805+
3806+
// x == C ? 0 : (x > C+1 ? 1 : -1)
3807+
if (ICmpInst::isGT(InnerPred) && InnerTV->isOne() &&
3808+
InnerFV->isAllOnes()) {
3809+
IsSigned = ICmpInst::isSigned(InnerPred);
3810+
bool CanAddOne = IsSigned ? !C->isMaxSignedValue() : !C->isMaxValue();
3811+
if (CanAddOne) {
3812+
APInt Cplus1 = *C + 1;
3813+
if ((InnerLHS == X && match(InnerRHS, m_SpecificInt(Cplus1))) ||
3814+
(InnerRHS == X && match(InnerLHS, m_SpecificInt(Cplus1)))) {
3815+
Replace = true;
3816+
}
3817+
}
3818+
}
3819+
3820+
// x == C ? 0 : (x < C+1 ? -1 : 1)
3821+
if (ICmpInst::isLT(InnerPred) && InnerTV->isAllOnes() &&
3822+
InnerFV->isOne()) {
3823+
IsSigned = ICmpInst::isSigned(InnerPred);
3824+
bool CanAddOne = IsSigned ? !C->isMaxSignedValue() : !C->isMaxValue();
3825+
if (CanAddOne) {
3826+
APInt Cplus1 = *C + 1;
3827+
if ((InnerLHS == X && match(InnerRHS, m_SpecificInt(Cplus1))) ||
3828+
(InnerRHS == X && match(InnerLHS, m_SpecificInt(Cplus1)))) {
3829+
Replace = true;
3830+
}
3831+
}
3832+
}
3833+
}
3834+
}
3835+
}
3836+
37303837
Intrinsic::ID IID = IsSigned ? Intrinsic::scmp : Intrinsic::ucmp;
37313838
if (Replace)
37323839
return replaceInstUsesWith(
37333840
SI, Builder.CreateIntrinsic(SI.getType(), IID, {LHS, RHS}));
3841+
37343842
return nullptr;
37353843
}
37363844

@@ -4496,5 +4604,21 @@ Instruction *InstCombinerImpl::visitSelectInst(SelectInst &SI) {
44964604
return replaceOperand(SI, 2, ConstantInt::get(FalseVal->getType(), 0));
44974605
}
44984606

4607+
// Canonicalize sign function ashr pattern: select (icmp slt X, 1), ashr X, bitwidth-1, 1 -> scmp(X, 0)
4608+
Value *X;
4609+
unsigned BitWidth = SI.getType()->getScalarSizeInBits();
4610+
CmpPredicate Pred;
4611+
if (match(&SI,
4612+
m_Select(
4613+
m_ICmp(Pred, m_Value(X), m_One()),
4614+
m_AShr(m_Deferred(X), m_SpecificInt(BitWidth - 1)),
4615+
m_One())) &&
4616+
Pred == ICmpInst::ICMP_SLT) {
4617+
4618+
Function *Scmp = Intrinsic::getOrInsertDeclaration(
4619+
SI.getModule(), Intrinsic::scmp, {SI.getType(), SI.getType()});
4620+
return CallInst::Create(Scmp, {X, ConstantInt::get(SI.getType(), 0)});
4621+
}
4622+
44994623
return nullptr;
45004624
}

‎llvm/test/Transforms/InstCombine/scmp.ll

Lines changed: 46 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -439,9 +439,7 @@ define <3 x i2> @scmp_unary_shuffle_ops(<3 x i8> %x, <3 x i8> %y) {
439439
define i32 @scmp_ashr(i32 %a) {
440440
; CHECK-LABEL: define i32 @scmp_ashr(
441441
; CHECK-SAME: i32 [[A:%.*]]) {
442-
; CHECK-NEXT: [[A_LOBIT:%.*]] = ashr i32 [[A]], 31
443-
; CHECK-NEXT: [[CMP_INV:%.*]] = icmp slt i32 [[A]], 1
444-
; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[CMP_INV]], i32 [[A_LOBIT]], i32 1
442+
; CHECK-NEXT: [[RETVAL_0:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[A]], i32 0)
445443
; CHECK-NEXT: ret i32 [[RETVAL_0]]
446444
;
447445
%a.lobit = ashr i32 %a, 31
@@ -453,9 +451,7 @@ define i32 @scmp_ashr(i32 %a) {
453451
define i32 @scmp_sgt_slt(i32 %a) {
454452
; CHECK-LABEL: define i32 @scmp_sgt_slt(
455453
; CHECK-SAME: i32 [[A:%.*]]) {
456-
; CHECK-NEXT: [[A_LOBIT:%.*]] = ashr i32 [[A]], 31
457-
; CHECK-NEXT: [[CMP_INV:%.*]] = icmp slt i32 [[A]], 1
458-
; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[CMP_INV]], i32 [[A_LOBIT]], i32 1
454+
; CHECK-NEXT: [[RETVAL_0:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[A]], i32 0)
459455
; CHECK-NEXT: ret i32 [[RETVAL_0]]
460456
;
461457
%cmp = icmp sgt i32 %a, 0
@@ -468,10 +464,7 @@ define i32 @scmp_sgt_slt(i32 %a) {
468464
define i32 @scmp_zero_slt(i32 %a) {
469465
; CHECK-LABEL: define i32 @scmp_zero_slt(
470466
; CHECK-SAME: i32 [[A:%.*]]) {
471-
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A]], 0
472-
; CHECK-NEXT: [[CMP1_INV:%.*]] = icmp slt i32 [[A]], 1
473-
; CHECK-NEXT: [[DOT:%.*]] = select i1 [[CMP1_INV]], i32 -1, i32 1
474-
; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[CMP]], i32 0, i32 [[DOT]]
467+
; CHECK-NEXT: [[RETVAL_0:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[A]], i32 0)
475468
; CHECK-NEXT: ret i32 [[RETVAL_0]]
476469
;
477470
%cmp = icmp eq i32 %a, 0
@@ -484,10 +477,7 @@ define i32 @scmp_zero_slt(i32 %a) {
484477
define i32 @scmp_zero_sgt(i32 %a) {
485478
; CHECK-LABEL: define i32 @scmp_zero_sgt(
486479
; CHECK-SAME: i32 [[A:%.*]]) {
487-
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A]], 0
488-
; CHECK-NEXT: [[CMP1_INV:%.*]] = icmp sgt i32 [[A]], -1
489-
; CHECK-NEXT: [[DOT:%.*]] = select i1 [[CMP1_INV]], i32 1, i32 -1
490-
; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[CMP]], i32 0, i32 [[DOT]]
480+
; CHECK-NEXT: [[RETVAL_0:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[A]], i32 0)
491481
; CHECK-NEXT: ret i32 [[RETVAL_0]]
492482
;
493483
%cmp = icmp eq i32 %a, 0
@@ -498,6 +488,48 @@ define i32 @scmp_zero_sgt(i32 %a) {
498488
}
499489

500490

491+
define i32 @ucmp_sgt_slt_neg(i32 %a) {
492+
; CHECK-LABEL: define i32 @ucmp_sgt_slt_neg(
493+
; CHECK-SAME: i32 [[A:%.*]]) {
494+
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp ne i32 [[A]], 0
495+
; CHECK-NEXT: [[RETVAL_0:%.*]] = zext i1 [[CMP_NOT]] to i32
496+
; CHECK-NEXT: ret i32 [[RETVAL_0]]
497+
;
498+
%cmp = icmp ugt i32 %a, 0
499+
%cmp1 = icmp ult i32 %a, 0
500+
%. = select i1 %cmp1, i32 -1, i32 0
501+
%retval.0 = select i1 %cmp, i32 1, i32 %.
502+
ret i32 %retval.0
503+
}
504+
505+
define i32 @ucmp_zero_slt_neg(i32 %a) {
506+
; CHECK-LABEL: define i32 @ucmp_zero_slt_neg(
507+
; CHECK-SAME: i32 [[A:%.*]]) {
508+
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[A]], 0
509+
; CHECK-NEXT: [[RETVAL_0:%.*]] = zext i1 [[CMP]] to i32
510+
; CHECK-NEXT: ret i32 [[RETVAL_0]]
511+
;
512+
%cmp = icmp eq i32 %a, 0
513+
%cmp1.inv = icmp ult i32 %a, 1
514+
%. = select i1 %cmp1.inv, i32 -1, i32 1
515+
%retval.0 = select i1 %cmp, i32 0, i32 %.
516+
ret i32 %retval.0
517+
}
518+
519+
define i32 @ucmp_zero_sgt_neg(i32 %a) {
520+
; CHECK-LABEL: define i32 @ucmp_zero_sgt_neg(
521+
; CHECK-SAME: i32 [[A:%.*]]) {
522+
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[A]], 0
523+
; CHECK-NEXT: [[RETVAL_0:%.*]] = sext i1 [[CMP]] to i32
524+
; CHECK-NEXT: ret i32 [[RETVAL_0]]
525+
;
526+
%cmp = icmp eq i32 %a, 0
527+
%cmp1.inv = icmp ugt i32 %a, -1
528+
%. = select i1 %cmp1.inv, i32 1, i32 -1
529+
%retval.0 = select i1 %cmp, i32 0, i32 %.
530+
ret i32 %retval.0
531+
}
532+
501533
define i32 @scmp_sgt_slt_ab(i32 %a, i32 %b) {
502534
; CHECK-LABEL: define i32 @scmp_sgt_slt_ab(
503535
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {

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