error in simulation

[YazanBaddour]

hello!!

i am trying to implement this rtl

when simulating the fabric generated by OpenFPGA i get the following :

the output doesn't change on negative edge reset(like the ref ) and the value is updated only on the following posedge of the clk
note i added constant_net_method route for earlier mismatches but i still have this issue that output doesn't change on negative edge
i am using the write_full_testbench_example_script.openfpga for the script and for the architecture
xmlarch.txt
openfpgaarch.txt

any help would be appreciated how can i make my fabric outputs sensitive to negative edge signals ?
thank you

[tangxifan]

@YazanBaddour

Please refer to the example: https://github.com/lnis-uofu/OpenFPGA/tree/master/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config

[YazanBaddour]

thank you!
i tried running another design into the openfpga flow which is a finite state machine and the openfpga gives me error (only rising edges latches are supported )

is there anyway to fix this error
thank you