Merge branch 'devel'

Author: guilhermerc

hdl/syn/afcv4_ref_design/Manifest.py

@@ -19,11 +19,13 @@
     ["steps.synth_design.args.retiming", "1"],
     ["steps.synth_design.args.assert", "1"],
     ["steps.opt_design.args.verbose", "1"],
+    ["steps.opt_design.args.directive", "ExploreWithRemap"],
     ["steps.opt_design.is_enabled", "1"],
     ["steps.phys_opt_design.args.directive", "Explore"],
     ["steps.phys_opt_design.args.more options", "-verbose"],
     ["steps.phys_opt_design.is_enabled", "1"],
-    ["steps.place_design.args.directive", "ExtraTimingOpt"],
+    ["steps.route_design.args.directive", "NoTimingRelaxation"],
+    ["steps.route_design.args.more options", "-tns_cleanup"],
     ["steps.post_route_phys_opt_design.args.directive", "Explore"],
     ["steps.post_route_phys_opt_design.args.more options", "-verbose"],
     ["steps.post_route_phys_opt_design.is_enabled", "1"],

hdl/syn/afcv4_ref_design/build_bitstream_remote.sh

@@ -8,7 +8,7 @@ set -u
 # Maximum of 16 chars
 SYNTH_INFO_PROJECT="afcv4_fofb_ctrl"
 SYNTH_INFO_TOOL="VIVADO"
-SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2)
+SYNTH_INFO_VER=$(vivado -version | grep 'Vivado v[0-9]\{4\}.*' -m 1 | cut -d' ' -f2 | cut -d 'v' -f2)
 
 SYNTH_INFO_COMMAND="../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}"
 

hdl/syn/afcv4_ref_design/build_synthesis_sdb.sh

@@ -0,0 +1,3 @@
+#!/bin/sh
+
+vivado afcv4_ref_fofb_ctrl.xpr -mode batch -source check_timing.tcl

hdl/syn/afcv4_ref_design/check_timing.sh

@@ -0,0 +1,13 @@
+set wns [get_property STATS.WNS [get_runs impl_1]]
+set whs [get_property STATS.WHS [get_runs impl_1]]
+
+puts "WNS: ${wns}"
+puts "WHS: ${whs}"
+
+if {($wns < 0) || ($whs < 0)} {
+	puts "Failed timing!"
+	exit 1
+} else {
+	puts "Passed timing."
+	exit 0
+}

hdl/syn/afcv4_ref_design/check_timing.tcl

@@ -763,12 +763,6 @@ architecture top of afc_ref_fofb_ctrl_gen is
     atom_width                               => to_unsigned(16, c_ACQ_ATOM_WIDTH_LOG2)
   );
 
-  constant c_FACQ_PARAMS_DCC                 : t_facq_chan_param := (
-    width                                    => to_unsigned(256, c_ACQ_CHAN_CMPLT_WIDTH_LOG2),
-    num_atoms                                => to_unsigned(8, c_ACQ_NUM_ATOMS_WIDTH_LOG2),
-    atom_width                               => to_unsigned(32, c_ACQ_ATOM_WIDTH_LOG2)
-  );
-
   constant c_FACQ_PARAMS_SYS_ID              : t_facq_chan_param := (
     -- NOTE: Altough 768 bits would be enough, using this value as width somehow
     --       causes ACQ samples to be weirdly misaligned (see https://github.com/lnls-dig/infra-cores/issues/18).