diff --git a/README.md b/README.md index a3aa9bd2..ab6d9417 100644 --- a/README.md +++ b/README.md @@ -466,6 +466,17 @@ repository root: fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:demo_system ``` +To build for other support development boards such as the NewAE CW305, NewAE CW312-A35, or the TUL PYNQ-Z2, use the command + +``` +# NewAE CW305 +fusesoc --cores-root=. run --target=synth_cw305 --setup --build lowrisc:ibex:demo_system +# NewAE CW312-A35 +fusesoc --cores-root=. run --target=synth_cw312a35 --setup --build lowrisc:ibex:demo_system +# TUL PYNQ-Z2 +fusesoc --cores-root=. run --target=synth_pynqz2 --setup --build lowrisc:ibex:demo_system +``` + ## Programming FPGA To program the FPGA, either use FuseSoC again @@ -485,11 +496,11 @@ debugger. ```bash # Run demo -./util/load_demo_system.sh run ./sw/build/demo/hello_world/demo -./util/load_demo_system.sh run ./sw/build/demo/lcd_st7735/lcd_st7735 +./util/load_demo_system.sh run ./sw/build/demo/hello_world/demo +./util/load_demo_system.sh run ./sw/build/demo/lcd_st7735/lcd_st7735 # Load demo and start halted awaiting a debugger -./util/load_demo_system.sh halt ./sw/build/demo/hello_world/demo +./util/load_demo_system.sh halt ./sw/build/demo/hello_world/demo ``` To view terminal output use screen: @@ -504,6 +515,14 @@ In this case, you may try using `sudo`. To exit from the `screen` command, you should press control and a together, then release these two keys and press d. +### Note on the UART connection of the PYNQ-Z2 development board + +There is no direct connection between the FTDI chip and the programming logic (PL) side of the Zynq 7020 SOC used in the PYNQ-Z2 development board. However, we may attach a 2.54mm pin header to J13 (pin 1: UART RX, pin 2: UART TX) on the board, route the UART signals to any available I/O pins, and make a connection using jumper wires. + +The following image shows a one-way connection between the TX pin of the Ibex and the RX pin of the FTDI chip. + +![PYNQ-Z2 UART jumper wire connection](doc/PynqZ2UARTConnection.jpg) + ## Debugging an application Either load an application and halt (see above) or start a new OpenOCD instance diff --git a/data/pins_pynqz2.xdc b/data/pins_pynqz2.xdc new file mode 100644 index 00000000..f3c8392d --- /dev/null +++ b/data/pins_pynqz2.xdc @@ -0,0 +1,194 @@ +## Based on https://dpoauwgwqsy2x.cloudfront.net/Download/pynq-z2_v1.0.xdc.zip +## This file is a general .xdc for the PYNQ-Z2 board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal 125 MHz + +set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { IO_CLK }]; #IO_L13P_T2_MRCC_35 Sch=sysclk +create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { IO_CLK }]; + +##Switches + +set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L7N_T1_AD2N_35 Sch=sw[0] +set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L7P_T1_AD2P_35 Sch=sw[1] + +##RGB LEDs + +set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[0] }]; #IO_L22N_T3_AD7N_35 Sch=led4_b +set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[1] }]; #IO_L16P_T2_35 Sch=led4_g +set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[2] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led4_r +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[3] }]; #IO_0_35 Sch=led5_b +set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[4] }]; #IO_L22P_T3_AD7P_35 Sch=led5_g +set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[5] }]; #IO_L23N_T3_35 Sch=led5_r + +##LEDs + +set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L6N_T0_VREF_34 Sch=led[0] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L6P_T0_34 Sch=led[1] +set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=led[2] +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L23P_T3_35 Sch=led[3] + +##Buttons + +set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { BTN[0] }]; #IO_L4P_T0_35 Sch=btn[0] +set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { BTN[1] }]; #IO_L4N_T0_35 Sch=btn[1] +set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { BTN[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=btn[2] +set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { IO_RST }]; #IO_L9P_T1_DQS_AD3P_35 Sch=btn[3] + +##PmodA + +set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { GPIOS[0] }]; #IO_L17P_T2_34 Sch=ja_p[1] +set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { GPIOS[1] }]; #IO_L17N_T2_34 Sch=ja_n[1] +set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { GPIOS[2] }]; #IO_L7P_T1_34 Sch=ja_p[2] +set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { GPIOS[3] }]; #IO_L7N_T1_34 Sch=ja_n[2] +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3] +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3] +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22P_T3_34 Sch=ja_p[4] +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22N_T3_34 Sch=ja_n[4] + +##PmodB + +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1] +#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1] +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_T0_34 Sch=jb_p[2] +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L1N_T0_34 Sch=jb_n[2] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3] +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4] +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4] + +##Audio + +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { adr0 }]; #IO_L8P_T1_AD10P_35 Sch=adr0 +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { adr1 }]; #IO_L8N_T1_AD10N_35 Sch=adr1 + +#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { au_mclk_r }]; #IO_L19N_T3_VREF_13 Sch=au_mclk_r +#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { au_sda_r }]; #IO_L12P_T1_MRCC_13 Sch=au_sda_r +#set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVCMOS33 } [get_ports { au_scl_r }]; #IO_L17P_T2_13 Sch= au_scl_r +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { au_dout_r }]; #IO_L6N_T0_VREF_35 Sch=au_dout_r +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { au_din_r }]; #IO_L16N_T2_35 Sch=au_din_r +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { au_wclk_r }]; #IO_L20P_T3_34 Sch=au_wclk_r +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { au_bclk_r }]; #IO_L20N_T3_34 Sch=au_bclk_r + + +## Single Ended Analog Inputs +##NOTE: The ar_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Arduino Analog pins a[0]-a[5]). +## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins a[0]-a[5]. + +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ar_an0_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ar_an0_p +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ar_an0_n }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ar_an0_n +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ar_an1_p }]; #IO_L5N_T0_AD9P_35 Sch=ar_an1_p +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { ar_an1_n }]; #IO_L5N_T0_AD9N_35 Sch=ar_an1_n +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ar_an2_p }]; #IO_L20P_T3_AD6P_35 Sch=ar_an2_p +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ar_an2_n }]; #IO_L20P_T3_AD6N_35 Sch=ar_an2_n +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ar_an3_p }]; #IO_L24P_T3_AD15P_35 Sch=ar_an3_p +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ar_an3_n }]; #IO_L24P_T3_AD15N_35 Sch=ar_an3_n +#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { ar_an4_p }]; #IO_L17P_T2_AD5P_35 Sch=ar_an4_p +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { ar_an4_n }]; #IO_L17P_T2_AD5P_35 Sch=ar_an4_n +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { ar_an5_p }]; #IO_L18P_T2_AD13P_35 Sch=ar_an5_p +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { ar_an5_n }]; #IO_L18P_T2_AD13P_35 Sch=ar_an5_n + +##Arduino Digital I/O + +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { UART_RX }]; #IO_L5P_T0_34 Sch=ar[0] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { UART_TX }]; #IO_L2N_T0_34 Sch=ar[1] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ar[2] }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ar[2] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ar[3] }]; #IO_L3N_T0_DQS_34 Sch=ar[3] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ar[4] }]; #IO_L10P_T1_34 Sch=ar[4] +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ar[5] }]; #IO_L5N_T0_34 Sch=ar[5] +#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ar[6] }]; #IO_L19P_T3_34 Sch=ar[6] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ar[7] }]; #IO_L9N_T1_DQS_34 Sch=ar[7] +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ar[8] }]; #IO_L21P_T3_DQS_34 Sch=ar[8] +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ar[9] }]; #IO_L21N_T3_DQS_34 Sch=ar[9] +#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ar[10] }]; #IO_L9P_T1_DQS_34 Sch=ar[10] +#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ar[11] }]; #IO_L19N_T3_VREF_34 Sch=ar[11] +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ar[12] }]; #IO_L23N_T3_34 Sch=ar[12] +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ar[13] }]; #IO_L23P_T3_34 Sch=ar[13] +#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { a }]; #IO_L20N_T3_13 Sch=a + +##Arduino Digital I/O On Outer Analog Header +##NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O + +#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { a[0] }]; #IO_L18N_T2_13 Sch=a[0] +#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { a[1] }]; #IO_L20P_T3_13 Sch=a[1] +#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { a[2] }]; #IO_L18P_T2_13 Sch=a[2] +#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { a[3] }]; #IO_L21P_T3_DQS_13 Sch=a[3] +#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { a[4] }]; #IO_L19P_T3_13 Sch=a[4] +#set_property -dict { PACKAGE_PIN U10 IOSTANDARD LVCMOS33 } [get_ports { a[5] }]; #IO_L12N_T1_MRCC_13 Sch=a[5] + +## Arduino SPI + +set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { SPI_RX }]; #IO_L10N_T1_34 Sch=miso +set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { SPI_TX }]; #IO_L2P_T0_34 Sch=ar_mosi_r +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { SPI_SCK }]; #IO_L19P_T3_35 Sch=sck +# set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ss + +## Arduino I2C + +#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ar_scl }]; #IO_L24N_T3_34 Sch=ar_scl +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ar_sda }]; #IO_L24P_T3_34 Sch=ar_sda + +##Raspberry Digital I/O + +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { rpio_02_r }]; #IO_L22P_T3_34 Sch=rpio_02_r +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { rpio_03_r }]; #IO_L22N_T3_34 Sch=rpio_03_r +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { rpio_04_r }]; #IO_L17P_T2_34 Sch=rpio_04_r +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { rpio_05_r }]; #IO_L17N_T2_34 Sch=rpio_05_r +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { rpio_06_r }]; #IO_L22P_T3_13 Sch=rpio_06_r +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { rpio_07_r }]; #IO_L12P_T1_MRCC_34 Sch=rpio_07_r +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { rpio_08_r }]; #IO_L12N_T1_MRCC_34 Sch=rpio_08_r +#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { rpio_09_r }]; #IO_L21N_T3_DQS_13 Sch=rpio_09_r +#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { rpio_10_r }]; #IO_L15P_T2_DQS_13 Sch=rpio_10_r +#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS33 } [get_ports { rpio_11_r }]; #IO_L16P_T2_13 Sch=rpio_11_r +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { rpio_12_r }]; #IO_L1N_T0_AD0N_35 Sch=rpio_12_r +#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { rpio_13_r }]; #IO_L15N_T2_DQS_13 Sch=rpio_13_r +#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { rpio_14_r }]; #IO_L22P_T3_13 Sch=rpio_14_r +#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { rpio_15_r }]; #IO_L13N_T2_MRCC_13 Sch=rpio_15_r +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { rpio_16_r }]; #IO_L2P_T0_AD8P_35 Sch=rpio_16_r +#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { rpio_17_r }]; #IO_L11P_T1_SRCC_13 Sch=rpio_17_r +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { rpio_18_r }]; #IO_L1P_T0_AD0P_35 Sch=rpio_18_r +#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { rpio_19_r }]; #IO_L14N_T2_SRCC_13 Sch=rpio_19_r +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { rpio_20_r }]; #IO_L2N_T0_AD8N_35 Sch=rpio_20_r +#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { rpio_21_r }]; #IO_L14P_T2_SRCC_13 Sch=rpio_21_r +#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { rpio_22_r }]; #IO_L17N_T2_13 Sch=rpio_22_r +#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { rpio_23_r }]; #IO_IO_L22N_T3_13 Sch=rpio_23_r +#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { rpio_24_r }]; #IO_L13P_T2_MRCC_13 Sch=rpio_24_r +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { rpio_25_r }]; #IO_L15N_T2_DQS_AD12N_35 Sch=rpio_25_r +#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { rpio_26_r }]; #IO_L16N_T2_13 Sch=rpio_26_r +#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { rpio_sd_r }]; #IO_L7P_T1_34 Sch=rpio_sd_r +#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { rpio_sc_r }]; #IO_L7N_T1_34 Sch=rpio_sc_r + +##HDMI Rx + +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_rx_cec +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=hdmi_rx_clk_n +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=hdmi_rx_clk_p +#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_d_n[0] +#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_d_p[0] +#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_d_n[1] +#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_d_p[1] +#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_d_n[2] +#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_d_p[2] +#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_25_34 Sch=hdmi_rx_hpd +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_rx_sda + +##HDMI Tx + +#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=hdmi_tx_cec +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=hdmi_tx_clk_n +#set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=hdmi_tx_clk_p +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=hdmi_tx_d_n[0] +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=hdmi_tx_d_p[0] +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=hdmi_tx_d_n[1] +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=hdmi_tx_d_p[1] +#set_property -dict { PACKAGE_PIN H18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=hdmi_tx_d_n[2] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=hdmi_tx_d_p[2] +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpdn }]; #IO_0_34 Sch=hdmi_tx_hpdn + + +##Crypto SDA + +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=crypto_sda \ No newline at end of file diff --git a/doc/PynqZ2UARTConnection.jpg b/doc/PynqZ2UARTConnection.jpg new file mode 100644 index 00000000..93add942 Binary files /dev/null and b/doc/PynqZ2UARTConnection.jpg differ diff --git a/ibex_demo_system.core b/ibex_demo_system.core index dc54e386..cdb69587 100644 --- a/ibex_demo_system.core +++ b/ibex_demo_system.core @@ -33,6 +33,15 @@ filesets: - rtl/fpga/top_cw312a35.sv file_type: systemVerilogSource + files_xilinx_pynqz2: + depend: + - lowrisc:ibex:rv_timer + - lowrisc:ibex:fpga_xilinx_shared + files: + - rtl/fpga/top_pynqz2.sv + - rtl/fpga/clkgen_pynqz2.sv + file_type: systemVerilogSource + files_verilator: depend: - lowrisc:ibex:sim_shared @@ -60,6 +69,10 @@ filesets: - data/pins_cw312a35.xdc file_type: xdc + files_constraints_pynqz2: + files: + - data/pins_pynqz2.xdc + file_type: xdc parameters: @@ -125,6 +138,19 @@ targets: parameters: - SRAMInitFile - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx + synth_pynqz2: + <<: *default_target + default_tool: vivado + filesets_append: + - files_xilinx_pynqz2 + - files_constraints_pynqz2 + toplevel: top_pynqz2 + tools: + vivado: + part: "xc7z020clg400-1" + parameters: + - SRAMInitFile + - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx sim: <<: *default_target diff --git a/rtl/fpga/clkgen_pynqz2.sv b/rtl/fpga/clkgen_pynqz2.sv new file mode 100644 index 00000000..400bb1f0 --- /dev/null +++ b/rtl/fpga/clkgen_pynqz2.sv @@ -0,0 +1,80 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module clkgen_pynqz2 ( + input IO_CLK, + input IO_RST_N, + output clk_sys, + output rst_sys_n +); + logic locked_pll; + logic io_clk_buf; + logic clk_50_buf; + logic clk_50_unbuf; + logic clk_fb_buf; + logic clk_fb_unbuf; + + // input buffer + IBUF io_clk_ibuf( + .I (IO_CLK), + .O (io_clk_buf) + ); + + PLLE2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (5), + .CLKFBOUT_MULT (34), + .CLKFBOUT_PHASE (0.000), + .CLKOUT0_DIVIDE (17), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKIN1_PERIOD (8.000) + ) pll ( + .CLKFBOUT (clk_fb_unbuf), + .CLKOUT0 (clk_50_unbuf), + .CLKOUT1 (), + .CLKOUT2 (), + .CLKOUT3 (), + .CLKOUT4 (), + .CLKOUT5 (), + // Input clock control + .CLKFBIN (clk_fb_buf), + .CLKIN1 (io_clk_buf), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Other control and status signals + .LOCKED (locked_pll), + .PWRDWN (1'b0), + // Do not reset PLL on external reset, otherwise ILA disconnects at a reset + .RST (1'b0)); + + // output buffering + BUFG clk_fb_bufg ( + .I (clk_fb_unbuf), + .O (clk_fb_buf) + ); + + BUFG clk_50_bufg ( + .I (clk_50_unbuf), + .O (clk_50_buf) + ); + + // outputs + // clock + assign clk_sys = clk_50_buf; + + // reset + assign rst_sys_n = locked_pll & IO_RST_N; +endmodule diff --git a/rtl/fpga/top_pynqz2.sv b/rtl/fpga/top_pynqz2.sv new file mode 100644 index 00000000..5d7e105a --- /dev/null +++ b/rtl/fpga/top_pynqz2.sv @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This is the top level SystemVerilog file that connects the IO on the board to the Ibex Demo System. +module top_pynqz2 ( + // These inputs are defined in data/pins_pynqz2.xdc + input IO_CLK, + input IO_RST, + input [1:0] SW, + input [2:0] BTN, + output [3:0] LED, + output [3:0] GPIOS, + output [5:0] RGB_LED, + input UART_RX, + output UART_TX, + input SPI_RX, + output SPI_TX, + output SPI_SCK +); + parameter SRAMInitFile = ""; + + logic clk_sys, rst_sys_n; + + // Instantiating the Ibex Demo System. + ibex_demo_system #( + .GpiWidth(5), + .GpoWidth(8), + .PwmWidth(6), + .SRAMInitFile(SRAMInitFile) + ) u_ibex_demo_system ( + //input + .clk_sys_i(clk_sys), + .rst_sys_ni(rst_sys_n), + .gp_i({SW, BTN}), + .uart_rx_i(UART_RX), + + //output + .gp_o({LED, GPIOS}), + .pwm_o(RGB_LED), + .uart_tx_o(UART_TX), + + .spi_rx_i(SPI_RX), + .spi_tx_o(SPI_TX), + .spi_sck_o(SPI_SCK) + ); + + logic IO_RST_N; + assign IO_RST_N = ~IO_RST; + + // Generating the system clock and reset for the FPGA. + clkgen_pynqz2 clkgen( + .IO_CLK, + .IO_RST_N, + .clk_sys, + .rst_sys_n + ); + +endmodule diff --git a/util/load_demo_system.sh b/util/load_demo_system.sh index c47fe195..19c23e58 100755 --- a/util/load_demo_system.sh +++ b/util/load_demo_system.sh @@ -3,31 +3,42 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -if [ $# -ne 2 ]; then - echo "Usage $0 run|halt elf_file" +if [ $# -ne 3 ]; then + echo "Usage $0 artya7|pynqz2 run|halt elf_file" exit 1 fi -if [ ! -f $2 ]; then - echo "$2 does not exist" +if [ ! -f $3 ]; then + echo "$3 does not exist" exit 1 fi -if [ $1 != "halt" ] && [ $1 != "run" ]; then - echo "First argument must be halt or run" +if [ $2 != "halt" ] && [ $2 != "run" ]; then + echo "Second argument must be halt or run" + exit 1 +fi + +if [ $1 != "artya7" ] && [ $1 != "pynqz2" ]; then + echo "First argument must be artya7 or pynqz2" exit 1 fi EXIT_CMD='' -if [ $1 = "run" ]; then +if [ $2 = "run" ]; then EXIT_CMD='-c "exit"' fi SCRIPT_DIR="$(dirname "$(readlink -e "$0")")" -openocd -f $SCRIPT_DIR/arty-a7-openocd-cfg.tcl -c "load_image $2 0x0" \ - -c "verify_image $2 0x0" \ +if [ $1 = "artya7" ]; then + SCRIPT_FILENAME="arty-a7-openocd-cfg.tcl" +elif [ $1 = "pynqz2" ]; then + SCRIPT_FILENAME="pynq-z2-openocd-cfg.tcl" +fi + +openocd -f $SCRIPT_DIR/$SCRIPT_FILENAME -c "load_image $3 0x0" \ + -c "verify_image $3 0x0" \ -c "echo \"Doing reset\"" \ - -c "reset $1" \ + -c "reset $2" \ $EXIT_CMD diff --git a/util/pynq-z2-openocd-cfg.tcl b/util/pynq-z2-openocd-cfg.tcl new file mode 100644 index 00000000..041bf4ff --- /dev/null +++ b/util/pynq-z2-openocd-cfg.tcl @@ -0,0 +1,43 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +adapter driver ftdi +transport select jtag + +ftdi_device_desc "TUL" +ftdi_vid_pid 0x0403 0x6010 +ftdi_channel 0 +ftdi_layout_init 0x0088 0x008b +reset_config none + +# Configure JTAG chain and the target processor +set _CHIPNAME riscv + +# Configure JTAG expected ID +set _EXPECTED_ID 0x23727093 + +jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_EXPECTED_ID -ignore-version + +# just to avoid a warning about the auto-detected arm core +# see: https://github.com/pulp-platform/riscv-dbg/blob/master/doc/debug-system.md +jtag newtap arm_unused tap -irlen 4 -expected-id 0x4ba00477 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +riscv set_ir idcode 0x09 +riscv set_ir dtmcs 0x22 +riscv set_ir dmi 0x23 + +adapter speed 10000 + +riscv set_prefer_sba on +gdb_report_data_abort enable +gdb_report_register_access_error enable +gdb_breakpoint_override hard + +reset_config none + +init +halt