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[kalabYibeltal]

I tried running Ibex small configuration with different workload by turning the Icache parameter on and off (assigning it 0 and 1) this is what I got in the Simulation statistics

Without Cache

Simulation statistics

Executed cycles: 167525
Wallclock time: 8.708 s
Simulation speed: 19238.1 cycles/s (19.2381 kHz)
Trace file size: 5758073 B

With cache

Simulation statistics

Executed cycles: 167525
Wallclock time: 14.255 s
Simulation speed: 11752 cycles/s (11.752 kHz)
Trace file size: 7273683 B

I tested it with different workloads and different configurations available in ibex. it seems like the Executed cycles should be smaller if a cache exists. On top of that it seems the wallclock time takes longer for a configuration with cache.

I also tried decreasing the clock from 0.5 to 0.05 in ibex_simple_system.sv but still the Executed cycles do not change.

My Environment

I am using wsl on windows and I am running ibex simple system on bare metal
I am using ubuntu Ubuntu 22.04.4 LTS

EDA tool and version:

Operating system:

Version of the Ibex source code:

[a-will]

Did you actually enable the cache in software? The Verilog parameter affects whether the cache is present in hardware. The default state of the CPU still leaves the cache inactive.

https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html#cpu-control-and-status-register-cpuctrlsts

[kalabYibeltal]

Did you actually enable the cache in software? The Verilog parameter affects whether the cache is present in hardware. The default state of the CPU still leaves the cache inactive.

https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html#cpu-control-and-status-register-cpuctrlsts

Yes, I manually passed 1b'1 values to the initialization of the Icache of for ibex_top.sv before I build it and also I checked ibex_icache is being instantiated by printing values in the ibex_icache.sv file

[GregAC]

Enabling the icache requires a specific bit to be set by software in the CPUCTRLSTS CSR. We have a function that can enable/disable it:

ibex/examples/sw/simple_system/common/simple_system_common.h

Lines 99 to 114 in 84232a5

	* Enables/disables the instruction cache. This has no effect on Ibex
	* configurations that do not have an instruction cache and in particular is
	* safe to execute on those configurations.
	*
	* @param enable if non-zero enables, otherwise disables
	*/
	static inline void icache_enable(int enable) {
	if (enable) {
	// Set icache enable bit in CPUCTRLSTS
	asm volatile("csrs 0x7c0, 1");
	} else {
	// Clear icache enable bit in CPUCTRLSTS
	asm volatile("csrc 0x7c0, 1");
	}
	}

Also note that in simple system the memory is dual ported with single cycle response (i.e. the most ideal possible memory from a performance perspective) and the icache won't actually have an effect. Indeed you may observe a small decrease in performance. The icache is useful in scenarios where a fetch from instruction memory can take multiple cycles (e.g. if you're fetching from flash).