[entropy_src] Factor distr FIFO errors into ERR_CODE.FIFO_[STATE,READ,WRITE]_ERR

[vogelpi]

Description

Currently, errors triggered inside the distribution FIFO aren't factored into the ERR_CODE.FIFO_[STATE,READ,WRITE]_ERR fields. They still lead to a fatal alert and they still show up as error in the ERR_CODE CSR, but the type of error isn't reflected. This is an RTL bug but it's obviously not very critical.

The reason is simply that I forgot to include that signals into the fifo_[write,read,status]_err_sum signals. So it's very easy to fix. From entropy_src_core.sv:

  assign fifo_write_err_sum =
         sfifo_esrng_err[2] ||
         sfifo_observe_err[2] ||
         sfifo_esfinal_err[2] ||
         err_code_test_bit[28];
  assign fifo_read_err_sum =
         sfifo_esrng_err[1] ||
         sfifo_observe_err[1] ||
         sfifo_esfinal_err[1] ||
         err_code_test_bit[29];
  assign fifo_status_err_sum =
         sfifo_esrng_err[0] ||
         sfifo_observe_err[0] ||
         sfifo_esfinal_err[0] ||
         err_code_test_bit[30];

[vogelpi]

Related to this, I also noted that the signaling of errors via ERR_CODE CSR is handled a bit differently between ENTROPY_SRC and CSRNG/EDN:

• CSRNG only signals errors via ERR_CODE if the module is enabled

opentitan/hw/ip/csrng/rtl/csrng_core.sv

Lines 632 to 635 in e087179

	// set the err code source bits
	assign hw2reg.err_code.sfifo_cmd_err.d = 1'b1;
	assign hw2reg.err_code.sfifo_cmd_err.de = cs_enable_fo[2] &&
	(|cmd_stage_sfifo_cmd_err_sum);

• EDN signals the FIFO errors when the module is enabled, FSM errors are always signaled

opentitan/hw/ip/edn/rtl/edn_core.sv

Lines 345 to 359 in e087179

	// set the err code source bits
	assign hw2reg.err_code.sfifo_rescmd_err.d = 1'b1;
	assign hw2reg.err_code.sfifo_rescmd_err.de = edn_enable_fo[ReseedCmdErr] && sfifo_rescmd_err_sum;
	assign hw2reg.err_code.sfifo_gencmd_err.d = 1'b1;
	assign hw2reg.err_code.sfifo_gencmd_err.de = edn_enable_fo[GenCmdErr] && sfifo_gencmd_err_sum;
	assign hw2reg.err_code.edn_ack_sm_err.d = 1'b1;
	assign hw2reg.err_code.edn_ack_sm_err.de = edn_ack_sm_err_sum;
	assign hw2reg.err_code.edn_main_sm_err.d = 1'b1;
	assign hw2reg.err_code.edn_main_sm_err.de = edn_main_sm_err_sum;
	assign hw2reg.err_code.edn_cntr_err.d = 1'b1;
	assign hw2reg.err_code.edn_cntr_err.de = edn_cntr_err_sum;

• ENTROPY_SRC always signals errors via ERR_CODE register

opentitan/hw/ip/entropy_src/rtl/entropy_src_core.sv

Lines 961 to 963 in e087179

	// set the err code source bits
	assign hw2reg.err_code.sfifo_esrng_err.d = 1'b1;
	assign hw2reg.err_code.sfifo_esrng_err.de = sfifo_esrng_err_sum;

I think it would be better aligning ENTROPY_SRC with the other two blocks to ease integrations in the future.