From 3fec1e64891d74dc1845f8e9fc391669857d46a5 Mon Sep 17 00:00:00 2001 From: Emmanuel Blot Date: Tue, 21 Nov 2023 14:07:31 +0100 Subject: [PATCH] [ot] target/riscv: cpu: add a reset exit function to update resetvec and mtvec. These vectors may be updated while hart is held in reset, so they should be updated on reset exit, since reset_hold is only invoked on reset enter (Resettable API) Signed-off-by: Emmanuel Blot --- target/riscv/cpu.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index caa5f4e6686c..6da7e769934f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -900,8 +900,6 @@ static void riscv_cpu_reset_hold(Object *obj) } env->mcause = 0; env->miclaim = MIP_SGEIP; - env->pc = env->resetvec; - env->mtvec = cpu->cfg.mtvec; env->bins = 0; env->two_stage_lookup = false; @@ -963,6 +961,24 @@ static void riscv_cpu_reset_hold(Object *obj) #endif } +static void riscv_cpu_reset_exit(Object *obj) +{ + CPUState *cs = CPU(obj); + RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); + CPURISCVState *env = &cpu->env; + +#ifndef CONFIG_USER_ONLY + /* reset vector and mtvec may be updated while hart is in reset */ + env->pc = env->resetvec; + env->mtvec = cpu->cfg.mtvec; +#endif + + if (mcc->parent_phases.exit) { + mcc->parent_phases.exit(obj); + } +} + static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { RISCVCPU *cpu = RISCV_CPU(s); @@ -2199,7 +2215,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, riscv_cpu_realize, &mcc->parent_realize); - resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, + resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, + riscv_cpu_reset_exit, &mcc->parent_phases); cc->class_by_name = riscv_cpu_class_by_name;