From 0a6970c596fe9ce2580088cf2110dac1d55f4742 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Wed, 13 Dec 2023 15:18:33 +0100 Subject: [PATCH 1/5] Revert "[ot] target/riscv: cpu: add a reset exit function to update resetvec and mtvec." This reverts commit a0df1cd5d3bd66118b271084d09bbca440e1226c. --- target/riscv/cpu.c | 23 +++-------------------- 1 file changed, 3 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6da7e769934f..caa5f4e6686c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -900,6 +900,8 @@ static void riscv_cpu_reset_hold(Object *obj) } env->mcause = 0; env->miclaim = MIP_SGEIP; + env->pc = env->resetvec; + env->mtvec = cpu->cfg.mtvec; env->bins = 0; env->two_stage_lookup = false; @@ -961,24 +963,6 @@ static void riscv_cpu_reset_hold(Object *obj) #endif } -static void riscv_cpu_reset_exit(Object *obj) -{ - CPUState *cs = CPU(obj); - RISCVCPU *cpu = RISCV_CPU(cs); - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); - CPURISCVState *env = &cpu->env; - -#ifndef CONFIG_USER_ONLY - /* reset vector and mtvec may be updated while hart is in reset */ - env->pc = env->resetvec; - env->mtvec = cpu->cfg.mtvec; -#endif - - if (mcc->parent_phases.exit) { - mcc->parent_phases.exit(obj); - } -} - static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { RISCVCPU *cpu = RISCV_CPU(s); @@ -2215,8 +2199,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, riscv_cpu_realize, &mcc->parent_realize); - resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, - riscv_cpu_reset_exit, + resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, &mcc->parent_phases); cc->class_by_name = riscv_cpu_class_by_name; From dda7045abc3f03b26d12316f12924e679a1fbe59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Wed, 13 Dec 2023 15:18:41 +0100 Subject: [PATCH 2/5] Revert "[ot] ot_darjeeling: use Resettable API to start Hart in reset" This reverts commit 2d88e7e968b907eda65237a1690370f28a015b1a. --- hw/riscv/ot_darjeeling.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/hw/riscv/ot_darjeeling.c b/hw/riscv/ot_darjeeling.c index b7b6a0ad7c61..695aed79519c 100644 --- a/hw/riscv/ot_darjeeling.c +++ b/hw/riscv/ot_darjeeling.c @@ -1011,12 +1011,7 @@ static void ot_darjeeling_soc_reset_hold(Object *obj) resettable_assert_reset(OBJECT(s->devices[OT_DARJEELING_SOC_DEV_ROM1]), RESET_TYPE_COLD); - /* - * leave hart on reset - * power manager should release it once ROMs have been validated - */ - CPUState *cs = CPU(s->devices[OT_DARJEELING_SOC_DEV_HART]); - resettable_assert_reset(OBJECT(cs), RESET_TYPE_COLD); + cpu_reset(CPU(s->devices[OT_DARJEELING_SOC_DEV_HART])); } static void ot_darjeeling_soc_reset_exit(Object *obj) From 7ceeb3d4987457438cd5e48ddfd7b27be5f186f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Wed, 13 Dec 2023 15:18:47 +0100 Subject: [PATCH 3/5] Revert "[ot] ot_earlgrey: use Resettable API to start Hart in reset" This reverts commit 9f88e0ed691058689edf4752066ad2029640b790. --- hw/riscv/ot_earlgrey.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/hw/riscv/ot_earlgrey.c b/hw/riscv/ot_earlgrey.c index 4d669d010fea..09f0baffd387 100644 --- a/hw/riscv/ot_earlgrey.c +++ b/hw/riscv/ot_earlgrey.c @@ -977,12 +977,7 @@ static void ot_earlgrey_soc_reset_hold(Object *obj) resettable_assert_reset(OBJECT(s->devices[OT_EARLGREY_SOC_DEV_ROM_CTRL]), RESET_TYPE_COLD); - /* - * leave hart on reset - * power manager should release it once ROM has been validated - */ - CPUState *cs = CPU(s->devices[OT_EARLGREY_SOC_DEV_HART]); - resettable_assert_reset(OBJECT(cs), RESET_TYPE_COLD); + cpu_reset(CPU(s->devices[OT_EARLGREY_SOC_DEV_HART])); } static void ot_earlgrey_soc_reset_exit(Object *obj) From 76a3c16521d4cca954c92195b7e595680132ff02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Wed, 13 Dec 2023 15:18:56 +0100 Subject: [PATCH 4/5] Revert "[ot] hw/opentitan: ot_pwrmgr: use Resettable API to release Hart from reset" This reverts commit 86a283fbf2ed8d1363f669eaf7587e86266f9bb7. --- hw/opentitan/ot_pwrmgr.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/opentitan/ot_pwrmgr.c b/hw/opentitan/ot_pwrmgr.c index 09ef8850cb6d..4d1f813c7165 100644 --- a/hw/opentitan/ot_pwrmgr.c +++ b/hw/opentitan/ot_pwrmgr.c @@ -247,9 +247,10 @@ static void ot_pwrmgr_rom_done(void *opaque, int irq, int level) /* if all ROM checks are done, start vCPU or report error */ if (done) { if (good) { - CPUState *cs = ot_common_get_local_cpu(DEVICE(s)); - if (cs) { - resettable_release_reset(OBJECT(cs), RESET_TYPE_COLD); + CPUState *cpu = ot_common_get_local_cpu(DEVICE(s)); + if (cpu) { + cpu->halted = 0; + cpu_resume(cpu); } else { error_report("ot_pwrmgr: Could not find a vCPU to start!"); } From 7b961a001b2612dc2005084de73718b14b59f4fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= Date: Wed, 13 Dec 2023 15:19:11 +0100 Subject: [PATCH 5/5] Revert "[ot] hw/core: Use resettable API to maintain CPU on reset" This reverts commit 6a700931aa3d0805322e908f80708989da6e2de6. --- accel/tcg/cpu-exec.c | 4 ++-- hw/core/cpu-common.c | 25 ++----------------------- include/hw/core/cpu.h | 1 - 3 files changed, 4 insertions(+), 26 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 15d4b050b338..c724e8b6f107 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -689,11 +689,11 @@ static inline bool cpu_handle_halt(CPUState *cpu) return true; } - cpu->halted = cpu->on_reset; + cpu->halted = 0; } #endif /* !CONFIG_USER_ONLY */ - return cpu->on_reset; + return false; } static inline void cpu_handle_debug_exception(CPUState *cpu) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index dff635393b8d..ced66c2b3429 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -116,34 +116,15 @@ void cpu_reset(CPUState *cpu) trace_cpu_reset(cpu->cpu_index); } -static void cpu_common_reset_enter(Object *obj, ResetType type) +static void cpu_common_reset_hold(Object *obj) { CPUState *cpu = CPU(obj); CPUClass *cc = CPU_GET_CLASS(cpu); - cpu->on_reset = true; if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset Enter (CPU %d)\n", cpu->cpu_index); + qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index); log_cpu_state(cpu, cc->reset_dump_flags); } -} - -static void cpu_common_reset_exit(Object *obj) -{ - CPUState *cpu = CPU(obj); - cpu->on_reset = false; - cpu->halted = 0; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - CPUClass *cc = CPU_GET_CLASS(cpu); - qemu_log("CPU Reset Exit (CPU %d) PC:0x%" VADDR_PRIx "\n", - cpu->cpu_index, cc->get_pc(cpu)); - } - cpu_resume(cpu); -} - -static void cpu_common_reset_hold(Object *obj) -{ - CPUState *cpu = CPU(obj); cpu->interrupt_request = 0; cpu->halted = cpu->start_powered_off; @@ -289,9 +270,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize = cpu_common_realizefn; dc->unrealize = cpu_common_unrealizefn; - rc->phases.enter = cpu_common_reset_enter; rc->phases.hold = cpu_common_reset_hold; - rc->phases.exit = cpu_common_reset_exit; cpu_class_init_props(dc); /* * Reason: CPUs still need special care by board code: wiring up diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index f5ca8a6505cb..fdcbe8735258 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -348,7 +348,6 @@ struct CPUState { /* Should CPU start in powered-off state? */ bool start_powered_off; - bool on_reset; bool unplug; bool crash_occurred;