diff --git a/tests/boards/espressif_esp32/rtc_clk/CMakeLists.txt b/tests/boards/espressif_esp32/rtc_clk/CMakeLists.txt new file mode 100644 index 00000000000000..c22ee7652d8b57 --- /dev/null +++ b/tests/boards/espressif_esp32/rtc_clk/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(rtc_clk_test) + +target_sources(app PRIVATE src/rtc_clk_test.c) diff --git a/tests/boards/espressif_esp32/rtc_clk/Kconfig b/tests/boards/espressif_esp32/rtc_clk/Kconfig new file mode 100644 index 00000000000000..5a4705655f333c --- /dev/null +++ b/tests/boards/espressif_esp32/rtc_clk/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +mainmenu "RTC CLK Test Configuration" + +source "Kconfig.zephyr" + +config FIXTURE_XTAL + bool "Selected when external crystal is present" + default n diff --git a/tests/boards/espressif_esp32/rtc_clk/README.rst b/tests/boards/espressif_esp32/rtc_clk/README.rst new file mode 100644 index 00000000000000..caeb6d027c69cb --- /dev/null +++ b/tests/boards/espressif_esp32/rtc_clk/README.rst @@ -0,0 +1,85 @@ +.. _rtc_clk_test: + +Espressif's RTC Clock test +########################## + +Overview +******** + +This test iterates through all the clock sources and checks if the expected frequency is being set. +Espressif SOCs have 3 main clock subsystems: CPU, RTC_FAST and RTC_SLOW. Each of these subsystems have their own clock sources and possible rates. + + +Supported Boards +**************** +- esp32_devkitc_wrover/esp32/procpu +- esp32c3_devkitm +- esp32s2_saola +- esp32s3_devkitm/esp32s3/procpu + +Building and Running +******************** + +Make sure you have the target connected over USB port. + +.. code-block:: console + + west build -b tests/boards/espressif_esp32/rtc_clk + west flash && west espressif monitor + +To run the test with twister, use the following command: + +.. code-block:: console + + west twister -p --device-testing --device-serial=/dev/ttyUSB0 -vv --flash-before -T tests/boards/espressif_esp32/rtc_clk + +If the external 32K crystal is connect to pins 32K_XP and 32K_XN, the test can be run with `external_xtal` fixture enabled: + +.. code-block:: console + + west twister -p esp32c3_devkitm --device-testing --device-serial=/dev/ttyUSB0 -vv --flash-before -T tests/boards/espressif_esp32/rtc_clk -X external_xtal + +Sample Output +============= + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-3162-g529005998ea6 *** + Running TESTSUITE rtc_clk + =================================================================== + CPU frequency: 240000000 + RTC_FAST frequency: 17500000 + RTC_SLOW frequency: 136000 + START - test_cpu_pll_src + Testing CPU frequency: 80 MHz + Testing CPU frequency: 160 MHz + Testing CPU frequency: 240 MHz + PASS - test_cpu_pll_src in 0.020 seconds + =================================================================== + START - test_cpu_xtal_src + Testing CPU frequency: 40 MHz + Testing CPU frequency: 20 MHz + Testing CPU frequency: 10 MHz + Testing CPU frequency: 5 MHz + PASS - test_cpu_xtal_src in 17.645 seconds + =================================================================== + START - test_rtc_fast_src + Testing RTC FAST CLK freq: 20000000 MHz + Testing RTC FAST CLK freq: 17500000 MHz + PASS - test_rtc_fast_src in 0.001 seconds + =================================================================== + START - test_rtc_slow_src + Testing RTC SLOW CLK freq: 136000 MHz + Testing RTC SLOW CLK freq: 68359 MHz + PASS - test_rtc_slow_src in 0.002 seconds + =================================================================== + TESTSUITE rtc_clk succeeded + ------ TESTSUITE SUMMARY START ------ + SUITE PASS - 100.00% [rtc_clk]: pass = 4, fail = 0, skip = 0, total = 4 duration = 17.668 seconds + - PASS - [rtc_clk.test_cpu_pll_src] duration = 0.020 seconds + - PASS - [rtc_clk.test_cpu_xtal_src] duration = 17.645 seconds + - PASS - [rtc_clk.test_rtc_fast_src] duration = 0.001 seconds + - PASS - [rtc_clk.test_rtc_slow_src] duration = 0.002 seconds + ------ TESTSUITE SUMMARY END ------ + =================================================================== + PROJECT EXECUTION SUCCESSFUL diff --git a/tests/boards/espressif_esp32/rtc_clk/prj.conf b/tests/boards/espressif_esp32/rtc_clk/prj.conf new file mode 100644 index 00000000000000..9467c2926896dd --- /dev/null +++ b/tests/boards/espressif_esp32/rtc_clk/prj.conf @@ -0,0 +1 @@ +CONFIG_ZTEST=y diff --git a/tests/boards/espressif_esp32/rtc_clk/src/rtc_clk_test.c b/tests/boards/espressif_esp32/rtc_clk/src/rtc_clk_test.c new file mode 100644 index 00000000000000..2b621d0e715aee --- /dev/null +++ b/tests/boards/espressif_esp32/rtc_clk/src/rtc_clk_test.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SOC_SERIES_ESP32) +#define DT_CPU_COMPAT espressif_xtensa_lx6 +#elif defined(CONFIG_SOC_SERIES_ESP32S2) || defined(CONFIG_SOC_SERIES_ESP32S3) +#define DT_CPU_COMPAT espressif_xtensa_lx7 +#elif CONFIG_SOC_SERIES_ESP32C3 +#define DT_CPU_COMPAT espressif_riscv +#endif + +static const struct device *const clk_dev = DEVICE_DT_GET_ONE(espressif_esp32_rtc); + +static void *rtc_clk_setup(void) +{ + zassert_true(device_is_ready(clk_dev), "CLK device is not ready"); + uint32_t rate = 0; + int ret = 0; + + ret = clock_control_get_rate(clk_dev, + (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &rate); + zassert_false(ret, "Failed to get CPU clock rate"); + TC_PRINT("CPU frequency: %d\n", rate); + + ret = clock_control_get_rate( + clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST, &rate); + zassert_false(ret, "Failed to get RTC_FAST clock rate"); + TC_PRINT("RTC_FAST frequency: %d\n", rate); + + ret = clock_control_get_rate( + clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW, &rate); + zassert_false(ret, "Failed to get RTC_SLOW clock rate"); + TC_PRINT("RTC_SLOW frequency: %d\n", rate); + + return NULL; +} + +ZTEST(rtc_clk, test_cpu_xtal_src) +{ + struct esp32_clock_config clk_cfg = {0}; + int ret = 0; + uint32_t cpu_rate = 0; + + clk_cfg.cpu.clk_src = ESP32_CPU_CLK_SRC_XTAL; + clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1)); + + for (uint8_t i = 0; i < 4; i++) { + clk_cfg.cpu.cpu_freq = clk_cfg.cpu.xtal_freq >> i; + + TC_PRINT("Testing CPU frequency: %d MHz\n", clk_cfg.cpu.cpu_freq); + + ret = clock_control_configure( + clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &clk_cfg); + zassert_false(ret, "Failed to set CPU clock source"); + + ret = clock_control_get_rate( + clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &cpu_rate); + zassert_false(ret, "Failed to get CPU clock rate"); + zassert_equal(cpu_rate, clk_cfg.cpu.cpu_freq * MHZ(1), + "CPU clock rate is not equal to XTAL frequency (%d != %d)", cpu_rate, + clk_cfg.cpu.cpu_freq); + } +} + +uint32_t rtc_pll_src_freq_mhz[] = { + ESP32_CLK_CPU_PLL_80M, + ESP32_CLK_CPU_PLL_160M, +#if !defined(CONFIG_SOC_SERIES_ESP32C3) + ESP32_CLK_CPU_PLL_240M, +#endif +}; + +ZTEST(rtc_clk, test_cpu_pll_src) +{ + struct esp32_clock_config clk_cfg = {0}; + int ret = 0; + uint32_t cpu_rate = 0; + + clk_cfg.cpu.clk_src = ESP32_CPU_CLK_SRC_PLL; + clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1)); + + for (uint8_t i = 0; i < ARRAY_SIZE(rtc_pll_src_freq_mhz); i++) { + clk_cfg.cpu.cpu_freq = rtc_pll_src_freq_mhz[i] / MHZ(1); + + TC_PRINT("Testing CPU frequency: %d MHz\n", clk_cfg.cpu.cpu_freq); + + ret = clock_control_configure( + clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &clk_cfg); + zassert_false(ret, "Failed to set CPU clock source"); + + ret = clock_control_get_rate( + clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &cpu_rate); + zassert_false(ret, "Failed to get CPU clock rate"); + zassert_equal(cpu_rate, clk_cfg.cpu.cpu_freq * MHZ(1), + "CPU clock rate is not equal to configured frequency (%d != %d)", + cpu_rate, clk_cfg.cpu.cpu_freq); + } +} + +uint32_t rtc_rtc_fast_clk_src[] = { +#if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32S2) + ESP32_RTC_FAST_CLK_SRC_XTAL_D4, +#else + ESP32_RTC_FAST_CLK_SRC_XTAL_D2, +#endif + ESP32_RTC_FAST_CLK_SRC_RC_FAST}; + +uint32_t rtc_rtc_fast_clk_src_freq_mhz[] = { +#if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32S2) + DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / 4, +#else + DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / 2, +#endif + ESP32_CLK_CPU_RC_FAST_FREQ +}; + +ZTEST(rtc_clk, test_rtc_fast_src) +{ + struct esp32_clock_config clk_cfg = {0}; + int ret = 0; + uint32_t cpu_rate = 0; + + clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1)); + + for (uint8_t i = 0; i < ARRAY_SIZE(rtc_rtc_fast_clk_src); i++) { + clk_cfg.rtc.rtc_fast_clock_src = rtc_rtc_fast_clk_src[i]; + + TC_PRINT("Testing RTC FAST CLK freq: %d MHz\n", rtc_rtc_fast_clk_src_freq_mhz[i]); + + ret = clock_control_configure( + clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST, + &clk_cfg); + zassert_false(ret, "Failed to set CPU clock source"); + + ret = clock_control_get_rate( + clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST, + &cpu_rate); + zassert_false(ret, "Failed to get RTC_FAST clock rate"); + zassert_equal(cpu_rate, rtc_rtc_fast_clk_src_freq_mhz[i], + "CPU clock rate is not equal to configured frequency (%d != %d)", + cpu_rate, rtc_rtc_fast_clk_src_freq_mhz[i]); + } +} + +uint32_t rtc_rtc_slow_clk_src[] = { + ESP32_RTC_SLOW_CLK_SRC_RC_SLOW, + ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256, +#if CONFIG_FIXTURE_XTAL + ESP32_RTC_SLOW_CLK_SRC_XTAL32K, +#endif +}; + +uint32_t rtc_rtc_slow_clk_src_freq[] = { + ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ, + ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ, +#if CONFIG_FIXTURE_XTAL + ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ, +#endif +}; + +ZTEST(rtc_clk, test_rtc_slow_src) +{ + struct esp32_clock_config clk_cfg = {0}; + int ret = 0; + uint32_t cpu_rate = 0; + + clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1)); + + for (uint8_t i = 0; i < ARRAY_SIZE(rtc_rtc_slow_clk_src); i++) { + clk_cfg.rtc.rtc_slow_clock_src = rtc_rtc_slow_clk_src[i]; + + TC_PRINT("Testing RTC SLOW CLK freq: %d MHz\n", rtc_rtc_slow_clk_src_freq[i]); + + ret = clock_control_configure( + clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW, + &clk_cfg); + zassert_false(ret, "Failed to set CPU clock source"); + + ret = clock_control_get_rate( + clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW, + &cpu_rate); + zassert_false(ret, "Failed to get RTC_SLOW clock rate"); + zassert_equal(cpu_rate, rtc_rtc_slow_clk_src_freq[i], + "CPU clock rate is not equal to configured frequency (%d != %d)", + cpu_rate, rtc_rtc_slow_clk_src_freq[i]); + } +} + +ZTEST_SUITE(rtc_clk, NULL, rtc_clk_setup, NULL, NULL, NULL); diff --git a/tests/boards/espressif_esp32/rtc_clk/testcase.yaml b/tests/boards/espressif_esp32/rtc_clk/testcase.yaml new file mode 100644 index 00000000000000..c968be3850ccc5 --- /dev/null +++ b/tests/boards/espressif_esp32/rtc_clk/testcase.yaml @@ -0,0 +1,17 @@ +tests: + boards.esp32.rtc_clk: + platform_allow: + - esp32_devkitc_wrover/esp32/procpu + - esp32c3_devkitm + - esp32s2_saola + - esp32s3_devkitm/esp32s3/procpu + boards.esp32.rtc_clk.xtal: + platform_allow: + - esp32_devkitc_wrover/esp32/procpu + - esp32c3_devkitm + - esp32s2_saola + - esp32s3_devkitm/esp32s3/procpu + harness_config: + fixture: external_xtal + extra_configs: + - CONFIG_FIXTURE_XTAL=y