From 1d934a51d9f19741c784397f127512b61210a847 Mon Sep 17 00:00:00 2001 From: Googulator Date: Tue, 25 Feb 2025 23:15:21 +0100 Subject: [PATCH 01/11] ipc: Correct ROM map of Intel IPC IPC has only one 4KiB ROM chip, mapped in 2 segments to 0xE800:0xEFFF and 0xF800:0xFFFF. There is no second ROM chip, and no ROM is mapped to 0xF000:0xF7FF. --- src/mame/intel/ipc.cpp | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/mame/intel/ipc.cpp b/src/mame/intel/ipc.cpp index 34caf853799af..139e9b67c76dc 100644 --- a/src/mame/intel/ipc.cpp +++ b/src/mame/intel/ipc.cpp @@ -27,7 +27,9 @@ Preliminary Memory Map - E800-F7FF BIOS ROM area + 0000-7FFF Onboard RAM (IPB & IPC) + 8000-F7FF Onboard RAM (IPC only) + E800-EFFF Bootstrap & diagnostic ROM F800-FFFF Monitor ROM (or other user interface) I/O F4/F5 main console input and output @@ -35,7 +37,7 @@ ToDo: - Everything! - - iPC - Find missing rom F800-FFFF + - Switch between bootstrap ROM area and high RAM at runtime ****************************************************************************/ @@ -71,7 +73,8 @@ void ipc_state::mem_map(address_map &map) { map.unmap_value_high(); map(0x0000, 0xdfff).ram(); - map(0xe800, 0xffff).rom().region("roms", 0); + map(0xe800, 0xefff).rom().region("roms", 0); + map(0xf800, 0xffff).rom().region("roms", 0x800); } void ipc_state::io_map(address_map &map) @@ -133,15 +136,14 @@ void ipc_state::ipc(machine_config &config) /* ROM definition */ ROM_START( ipb ) - ROM_REGION( 0x1800, "roms", 0 ) + ROM_REGION( 0x1000, "roms", 0 ) ROM_LOAD( "ipb_e8_v1.3.bin", 0x0000, 0x0800, CRC(fc9d4703) SHA1(2ce078e1bcd8b24217830c54bcf04c5d146d1b76) ) - ROM_LOAD( "ipb_f8_v1.3.bin", 0x1000, 0x0800, CRC(966ba421) SHA1(d6a904c7d992a05ed0f451d7d34c1fc8de9547ee) ) + ROM_LOAD( "ipb_f8_v1.3.bin", 0x0800, 0x0800, CRC(966ba421) SHA1(d6a904c7d992a05ed0f451d7d34c1fc8de9547ee) ) ROM_END ROM_START( ipc ) - ROM_REGION( 0x1800, "roms", ROMREGION_ERASEFF ) + ROM_REGION( 0x1000, "roms", 0 ) ROM_LOAD( "ipc_v1.3_104584-001.u82", 0x0000, 0x1000, CRC(0889394f) SHA1(b7525baf1884a7d67402dea4b5566016a9861ef2) ) - ROM_LOAD( "ipc_f8_v1.3.bin", 0x1000, 0x0800, NO_DUMP ) // rom name unknown ROM_END } // anonymous namespace @@ -151,4 +153,4 @@ ROM_END /* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */ COMP( 19??, ipb, 0, 0, ipc, ipc, ipc_state, empty_init, "Intel", "iPB", MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE ) -COMP( 19??, ipc, ipb, 0, ipc, ipc, ipc_state, empty_init, "Intel", "iPC", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE ) +COMP( 19??, ipc, ipb, 0, ipc, ipc, ipc_state, empty_init, "Intel", "iPC", MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE ) From d38920dd43ffbae7b9b95fa70e49a0898ef7f8ae Mon Sep 17 00:00:00 2001 From: Googulator Date: Wed, 26 Feb 2025 00:06:51 +0100 Subject: [PATCH 02/11] ipc: Implement differences between IPB and IPC * Use correct clock rates for each board (4.0MHz for IPC, 2.6MHz for IPB) * Make IPB's CPU a 8080A * Remove bogus ROM range between 0xF000 and 0xF7FF * Correct board full names and release years * Only map 32KiB RAM on IPB (IPC has 64KiB, partially shadowed by ROM) --- src/mame/intel/ipc.cpp | 42 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/src/mame/intel/ipc.cpp b/src/mame/intel/ipc.cpp index 139e9b67c76dc..2707420a72e8c 100644 --- a/src/mame/intel/ipc.cpp +++ b/src/mame/intel/ipc.cpp @@ -61,19 +61,30 @@ class ipc_state : public driver_device void ipc(machine_config &config); private: + void board_common(machine_config &config); void io_map(address_map &map) ATTR_COLD; - void mem_map(address_map &map) ATTR_COLD; + void ipb_mem_map(address_map &map) ATTR_COLD; + void ipc_mem_map(address_map &map) ATTR_COLD; virtual void machine_reset() override ATTR_COLD; required_device m_maincpu; }; -void ipc_state::mem_map(address_map &map) +void ipc_state::ipb_mem_map(address_map &map) +{ + map.unmap_value_high(); + map(0x0000, 0x7fff).ram(); + map(0xe800, 0xe7ff).rom().region("roms", 0); + map(0xf800, 0xffff).rom().region("roms", 0x800); +} + + +void ipc_state::ipc_mem_map(address_map &map) { map.unmap_value_high(); map(0x0000, 0xdfff).ram(); - map(0xe800, 0xefff).rom().region("roms", 0); + map(0xe800, 0xe7ff).rom().region("roms", 0); map(0xf800, 0xffff).rom().region("roms", 0x800); } @@ -100,10 +111,25 @@ void ipc_state::machine_reset() void ipc_state::ipc(machine_config &config) { /* basic machine hardware */ - I8085A(config, m_maincpu, XTAL(19'660'800) / 4); - m_maincpu->set_addrmap(AS_PROGRAM, &ipc_state::mem_map); + I8085A(config, m_maincpu, XTAL(8'000'000) / 2); + m_maincpu->set_addrmap(AS_PROGRAM, &ipc_state::ipc_mem_map); m_maincpu->set_addrmap(AS_IO, &ipc_state::io_map); + board_common(config); +} + +void ipc_state::ipb(machine_config &config) +{ + /* basic machine hardware */ + I8080A(config, m_maincpu, XTAL(23'400'000) / 9); + m_maincpu->set_addrmap(AS_PROGRAM, &ipc_state::ipb_mem_map); + m_maincpu->set_addrmap(AS_IO, &ipc_state::io_map); + board_common(config); +} + + +void ipc_state::board_common(machine_config &config) +{ pit8253_device &pit(PIT8253(config, "pit", 0)); pit.set_clk<0>(XTAL(19'660'800) / 16); pit.set_clk<1>(XTAL(19'660'800) / 16); @@ -151,6 +177,6 @@ ROM_END /* Driver */ -/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */ -COMP( 19??, ipb, 0, 0, ipc, ipc, ipc_state, empty_init, "Intel", "iPB", MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE ) -COMP( 19??, ipc, ipb, 0, ipc, ipc, ipc_state, empty_init, "Intel", "iPC", MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE ) +/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */ +COMP( 1977, ipb, 0, 0, ipb, ipc, ipc_state, empty_init, "Intel", "Integrated Processor Board", MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE ) +COMP( 1979, ipc, ipb, 0, ipc, ipc, ipc_state, empty_init, "Intel", "Integrated Processor Card", MACHINE_NO_SOUND_HW | MACHINE_SUPPORTS_SAVE ) From 82bb5bc88c17a93c165f8bb14079b16d1fdba95e Mon Sep 17 00:00:00 2001 From: Googulator Date: Wed, 26 Feb 2025 00:23:57 +0100 Subject: [PATCH 03/11] ipc: Correct ROM sets for IPB The ROM set used before is a modded version of v1.3 that runs uart1 at 9600 baud by default. It's not clear if an IPB ever shipped with a v1.3 monitor from the factory, although many IPBs were upgraded to this monitor version by their operators, so it's better to default to v1.2 - either way, reference the real, genuine ROMs. not some random modified one. --- src/mame/intel/ipc.cpp | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/src/mame/intel/ipc.cpp b/src/mame/intel/ipc.cpp index 2707420a72e8c..cc432639cebdd 100644 --- a/src/mame/intel/ipc.cpp +++ b/src/mame/intel/ipc.cpp @@ -139,7 +139,7 @@ void ipc_state::board_common(machine_config &config) pit.out_handler<1>().set("uart2", FUNC(i8251_device::write_txc)); pit.out_handler<1>().append("uart2", FUNC(i8251_device::write_rxc)); - i8251_device &uart1(I8251(config, "uart1", 0)); // 8 data bits, no parity, 1 stop bit, 9600 baud + i8251_device &uart1(I8251(config, "uart1", 0)); // 8 data bits, no parity, 2 stop bits, 110 baud uart1.txd_handler().set("rs232a", FUNC(rs232_port_device::write_txd)); uart1.dtr_handler().set("rs232a", FUNC(rs232_port_device::write_dtr)); uart1.rts_handler().set("rs232a", FUNC(rs232_port_device::write_rts)); @@ -163,8 +163,19 @@ void ipc_state::board_common(machine_config &config) /* ROM definition */ ROM_START( ipb ) ROM_REGION( 0x1000, "roms", 0 ) - ROM_LOAD( "ipb_e8_v1.3.bin", 0x0000, 0x0800, CRC(fc9d4703) SHA1(2ce078e1bcd8b24217830c54bcf04c5d146d1b76) ) - ROM_LOAD( "ipb_f8_v1.3.bin", 0x0800, 0x0800, CRC(966ba421) SHA1(d6a904c7d992a05ed0f451d7d34c1fc8de9547ee) ) + ROM_DEFAULT_BIOS("mon12") + // 1x2732 Copyright 1979 (in IPC) + // note: it's not clear if an IPB ever shipped with this ROM, but aftermarket ROM upgrades to 1.3 were common + ROM_SYSTEM_BIOS(0, "mon13", "Series II Monitor v1.3") + ROMX_LOAD( "ipc_v1.3_104584-001.u82", 0x0000, 0x1000, CRC(0889394f) SHA1(b7525baf1884a7d67402dea4b5566016a9861ef2), ROM_BIOS(0) ) + // 2x2716 Copyright 1978 + ROM_SYSTEM_BIOS(1, "mon12", "Series II Monitor v1.2") + ROMX_LOAD( "ipb_e8_v1.2.bin", 0x0000, 0x0800, CRC(6496efaf) SHA1(1a9c0f1b19c1807803db3f1543f51349d7fd693a), ROM_BIOS(1) ) + ROMX_LOAD( "ipb_f8_v1.2.bin", 0x0800, 0x0800, CRC(258dc9a6) SHA1(3fde993aee06d9af5093d7a2d9a8cbd71fed0951), ROM_BIOS(1) ) + // 2x2716 Copyright 1977 + ROM_SYSTEM_BIOS(2, "mon11", "Series II Monitor v1.1") + ROMX_LOAD( "ipb_e8_v1.1.bin", 0x0000, 0x0800, CRC(ffb7c036) SHA1(6f60cdfe20621c4b633c972adcb644a1c02eaa39), ROM_BIOS(2) ) + ROMX_LOAD( "ipb_e8_v1.1.bin", 0x0800, 0x0800, CRC(3696ff28) SHA1(38b435e10a81629430275aec051fb0a55ec1f6fd), ROM_BIOS(2) ) ROM_END ROM_START( ipc ) From fb9f0ddcfbc0dc1534a6821ab9bc05e569b1b188 Mon Sep 17 00:00:00 2001 From: Googulator Date: Wed, 26 Feb 2025 00:41:14 +0100 Subject: [PATCH 04/11] ipc: Implement bootstrap ROM en/disable, fix wrong end address --- src/mame/intel/ipc.cpp | 47 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 4 deletions(-) diff --git a/src/mame/intel/ipc.cpp b/src/mame/intel/ipc.cpp index cc432639cebdd..389891ebfa85a 100644 --- a/src/mame/intel/ipc.cpp +++ b/src/mame/intel/ipc.cpp @@ -34,15 +34,16 @@ I/O F4/F5 main console input and output I/O F6/F7 alternate console input + I/O FF ROM control (enable/disable access to bootstrap ROM) ToDo: - Everything! - - Switch between bootstrap ROM area and high RAM at runtime ****************************************************************************/ #include "emu.h" #include "cpu/i8085/i8085.h" +#include "machine/74259.h" #include "machine/i8251.h" #include "machine/pit8253.h" #include "bus/rs232/rs232.h" @@ -67,7 +68,10 @@ class ipc_state : public driver_device void ipc_mem_map(address_map &map) ATTR_COLD; virtual void machine_reset() override ATTR_COLD; + void ipc_control_w(uint8_t data); required_device m_maincpu; + required_device m_ipcctrl; + memory_view m_boot; }; @@ -75,7 +79,17 @@ void ipc_state::ipb_mem_map(address_map &map) { map.unmap_value_high(); map(0x0000, 0x7fff).ram(); - map(0xe800, 0xe7ff).rom().region("roms", 0); + + // selectively map the boot/diagnostic segment + map(0x0000, 0x7fff).view(m_boot); + + // SEL_BOOT/ == 0 and START_UP/ == 0 + m_boot[0](0x0000, 0x07ff).rom().region("roms", 0); + m_boot[0](0xe800, 0xefff).rom().region("roms", 0); + + // SEL_BOOT/ == 0 and START_UP/ == 1 + m_boot[1](0xe800, 0xefff).rom().region("roms", 0); + map(0xf800, 0xffff).rom().region("roms", 0x800); } @@ -83,8 +97,18 @@ void ipc_state::ipb_mem_map(address_map &map) void ipc_state::ipc_mem_map(address_map &map) { map.unmap_value_high(); - map(0x0000, 0xdfff).ram(); - map(0xe800, 0xe7ff).rom().region("roms", 0); + map(0x0000, 0xffff).ram(); + + // selectively map the boot/diagnostic segment + map(0x0000, 0xefff).view(m_boot); + + // SEL_BOOT/ == 0 and START_UP/ == 0 + m_boot[0](0x0000, 0x07ff).rom().region("roms", 0); + m_boot[0](0xe800, 0xefff).rom().region("roms", 0); + + // SEL_BOOT/ == 0 and START_UP/ == 1 + m_boot[1](0xe800, 0xefff).rom().region("roms", 0); + map(0xf800, 0xffff).rom().region("roms", 0x800); } @@ -95,6 +119,7 @@ void ipc_state::io_map(address_map &map) map(0xf0, 0xf3).rw("pit", FUNC(pit8253_device::read), FUNC(pit8253_device::write)); map(0xf4, 0xf5).rw("uart1", FUNC(i8251_device::read), FUNC(i8251_device::write)); map(0xf6, 0xf7).rw("uart2", FUNC(i8251_device::read), FUNC(i8251_device::write)); + map(0xff, 0xff).w(FUNC(ipc_state::ipc_control_w)); } /* Input ports */ @@ -107,6 +132,20 @@ void ipc_state::machine_reset() m_maincpu->set_state_int(i8085a_cpu_device::I8085_PC, 0xE800); } +void ipc_state::ipc_control_w(uint8_t data) +{ + // b3 is ~(bit to be written) + // b2-b0 is ~(no. of bit to be written) + m_ipcctrl->write_bit(~data & 7, BIT(~data, 3)); + + // SEL_BOOT/ == 0 + if (!m_ipcctrl->q3_r()) + // START_UP/ + m_boot.select(m_ipcctrl->q5_r()); + else + m_boot.disable(); +} + void ipc_state::ipc(machine_config &config) { From dc37e2125708a67be8f926f3626e665a822374cd Mon Sep 17 00:00:00 2001 From: Googulator Date: Wed, 26 Feb 2025 01:47:01 +0100 Subject: [PATCH 05/11] ipc: fix missing declarations and initializations --- src/mame/intel/ipc.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mame/intel/ipc.cpp b/src/mame/intel/ipc.cpp index 389891ebfa85a..e4c5a771d6a8d 100644 --- a/src/mame/intel/ipc.cpp +++ b/src/mame/intel/ipc.cpp @@ -57,9 +57,12 @@ class ipc_state : public driver_device ipc_state(const machine_config &mconfig, device_type type, const char *tag) : driver_device(mconfig, type, tag) , m_maincpu(*this, "maincpu") + , m_ipcctrl(*this, "ipcctrl") + , m_boot(*this, "boot") { } void ipc(machine_config &config); + void ipb(machine_config &config); private: void board_common(machine_config &config); @@ -197,6 +200,8 @@ void ipc_state::board_common(machine_config &config) rs232b.rxd_handler().set("uart2", FUNC(i8251_device::write_rxd)); rs232b.dsr_handler().set("uart2", FUNC(i8251_device::write_dsr)); rs232b.cts_handler().set("uart2", FUNC(i8251_device::write_cts)); + + LS259(config, m_ipcctrl); } /* ROM definition */ From c2865e14c76d18e1afcbf4f4dd45698a1fdcd135 Mon Sep 17 00:00:00 2001 From: Googulator Date: Wed, 26 Feb 2025 03:39:48 +0100 Subject: [PATCH 06/11] Add 23.4MHz crystal found on Intel IPB Personally verified with an actual IPB in hand, the crystal in question is clearly marked "23.400 Crystek". Official schematics also say 23.4MHz. --- src/emu/xtal.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/emu/xtal.cpp b/src/emu/xtal.cpp index 271a4fcc4c5ec..ea266380020f5 100644 --- a/src/emu/xtal.cpp +++ b/src/emu/xtal.cpp @@ -359,6 +359,7 @@ const double XTAL::known_xtals[] = { 22'680'000, // 22.680_MHz_XTAL HDS200 80-columns display clock 22'896'000, // 22.896_MHz_XTAL DEC VT220 132-column display clock 23'200'000, // 23.2_MHz_XTAL Roland JV-80 & JV-880 PCM clock + 23'400'000, // 23.4_MHz_XTAL Intel Integrated Processor Board (IPB) from iMDS2 23'814'000, // 23.814_MHz_XTAL TeleVideo TVI-912, 920 & 950 23'961'600, // 23.9616_MHz_XTAL Osborne 4 (Vixen) 24'000'000, // 24_MHz_XTAL Mario, 80's Data East games, 80's Konami games From ea1452c7a5b709958dc19e814d845a00dbca2d80 Mon Sep 17 00:00:00 2001 From: Googulator Date: Wed, 26 Feb 2025 20:48:47 +0100 Subject: [PATCH 07/11] ipc: Fix boundary and initial state of m_boot --- src/mame/intel/ipc.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mame/intel/ipc.cpp b/src/mame/intel/ipc.cpp index e4c5a771d6a8d..cf937ec17e9a3 100644 --- a/src/mame/intel/ipc.cpp +++ b/src/mame/intel/ipc.cpp @@ -71,6 +71,7 @@ class ipc_state : public driver_device void ipc_mem_map(address_map &map) ATTR_COLD; virtual void machine_reset() override ATTR_COLD; + virtual void driver_reset() override; void ipc_control_w(uint8_t data); required_device m_maincpu; required_device m_ipcctrl; @@ -84,7 +85,7 @@ void ipc_state::ipb_mem_map(address_map &map) map(0x0000, 0x7fff).ram(); // selectively map the boot/diagnostic segment - map(0x0000, 0x7fff).view(m_boot); + map(0x0000, 0xefff).view(m_boot); // SEL_BOOT/ == 0 and START_UP/ == 0 m_boot[0](0x0000, 0x07ff).rom().region("roms", 0); @@ -135,6 +136,11 @@ void ipc_state::machine_reset() m_maincpu->set_state_int(i8085a_cpu_device::I8085_PC, 0xE800); } +void ipc_state::driver_reset() +{ + m_boot.select(0); +} + void ipc_state::ipc_control_w(uint8_t data) { // b3 is ~(bit to be written) From 3691d09fa3383d3d59362ad3ceed3df3eab22346 Mon Sep 17 00:00:00 2001 From: Googulator Date: Thu, 27 Feb 2025 04:38:46 +0100 Subject: [PATCH 08/11] ipc: add alternate v1.2 ROM set found in an actual IPB This ROM set was found in an IPB in my possession, programmed into a pair of Hitachi HN462716G EPROMs with 0J3 (September 1980) date code. The IPB in question has Siemens branding, which suggests that it was once part of a Siemens SME system (German OEM version of the Intellec Series II Microcomputer Development System AKA "imds2"). It's identical to the regular v1.2 in every way, except for serial channel A (TTY), which operates at 600 baud instead of the usual 110, and has an additional 400ms wait added after each line break. This seems to be an adaptation to a 600 baud teleprinter, perhaps a Telefunken Telestar 121/122. --- src/mame/intel/ipc.cpp | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/mame/intel/ipc.cpp b/src/mame/intel/ipc.cpp index cf937ec17e9a3..1523e11225894 100644 --- a/src/mame/intel/ipc.cpp +++ b/src/mame/intel/ipc.cpp @@ -222,10 +222,18 @@ ROM_START( ipb ) ROM_SYSTEM_BIOS(1, "mon12", "Series II Monitor v1.2") ROMX_LOAD( "ipb_e8_v1.2.bin", 0x0000, 0x0800, CRC(6496efaf) SHA1(1a9c0f1b19c1807803db3f1543f51349d7fd693a), ROM_BIOS(1) ) ROMX_LOAD( "ipb_f8_v1.2.bin", 0x0800, 0x0800, CRC(258dc9a6) SHA1(3fde993aee06d9af5093d7a2d9a8cbd71fed0951), ROM_BIOS(1) ) + // 2x2716 Copyright 1978 (overwritten in F8 ROM by new code) + // this version was discovered in an IPB with Siemens branding, saved from e-waste - it's unofficial, but is definitely out there + // it's an adaptation to work with a 600 baud teleprinter with slow carriage return + // the names are derived from the chips' markings ("BOOT 600Bd" and "MON 2 600Bd") + // note: expect checksum messages from this ROM set, as whoever made it never bothered to correct the checksums + ROM_SYSTEM_BIOS(2, "mon12_600bd", "Series II Monitor v1.2 - 600 baud teleprinter version") + ROMX_LOAD( "ipb_e8_v1.2_boot_600bd.bin", 0x0000, 0x0800, CRC(6bf62535) SHA1(40ac2546c816884dffdaa0ed2c6e41eb8523dcd6), ROM_BIOS(2) ) + ROMX_LOAD( "ipb_f8_v1.2_mon_2_600bd.bin", 0x0800, 0x0800, CRC(d5ace425) SHA1(d39cd3522ffd1d334f6eb128990e488ce07243ab), ROM_BIOS(2) ) // 2x2716 Copyright 1977 - ROM_SYSTEM_BIOS(2, "mon11", "Series II Monitor v1.1") - ROMX_LOAD( "ipb_e8_v1.1.bin", 0x0000, 0x0800, CRC(ffb7c036) SHA1(6f60cdfe20621c4b633c972adcb644a1c02eaa39), ROM_BIOS(2) ) - ROMX_LOAD( "ipb_e8_v1.1.bin", 0x0800, 0x0800, CRC(3696ff28) SHA1(38b435e10a81629430275aec051fb0a55ec1f6fd), ROM_BIOS(2) ) + ROM_SYSTEM_BIOS(3, "mon11", "Series II Monitor v1.1") + ROMX_LOAD( "ipb_e8_v1.1.bin", 0x0000, 0x0800, CRC(ffb7c036) SHA1(6f60cdfe20621c4b633c972adcb644a1c02eaa39), ROM_BIOS(3) ) + ROMX_LOAD( "ipb_e8_v1.1.bin", 0x0800, 0x0800, CRC(3696ff28) SHA1(38b435e10a81629430275aec051fb0a55ec1f6fd), ROM_BIOS(3) ) ROM_END ROM_START( ipc ) From 11d9946835847aa6c41b9b434819f3ed9b298941 Mon Sep 17 00:00:00 2001 From: Googulator Date: Thu, 27 Feb 2025 04:41:47 +0100 Subject: [PATCH 09/11] ipc: correct clock frequency for IPC 8080 and 8085 require specifying their clocks differently: for 8080, the clock given is the internal core clock, while 8085 instead requires the crystal frequency to be given. This wrongly made IPC slightly slower than IPB; in reality, the IPC is significantly faster. --- src/mame/intel/ipc.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mame/intel/ipc.cpp b/src/mame/intel/ipc.cpp index 1523e11225894..630a47db40154 100644 --- a/src/mame/intel/ipc.cpp +++ b/src/mame/intel/ipc.cpp @@ -159,7 +159,7 @@ void ipc_state::ipc_control_w(uint8_t data) void ipc_state::ipc(machine_config &config) { /* basic machine hardware */ - I8085A(config, m_maincpu, XTAL(8'000'000) / 2); + I8085A(config, m_maincpu, XTAL(8'000'000)); m_maincpu->set_addrmap(AS_PROGRAM, &ipc_state::ipc_mem_map); m_maincpu->set_addrmap(AS_IO, &ipc_state::io_map); board_common(config); From 689af6e6d58299ea0031de31dfda418680546d84 Mon Sep 17 00:00:00 2001 From: Googulator Date: Thu, 27 Feb 2025 04:52:35 +0100 Subject: [PATCH 10/11] imds2: Document exactly which MDS model is emulated This driver emulates a Model 225 MDS in particular. Also, the proper full name used by Intel was "Intellec Series II Microcomputer Development System". During the Series II era, Intel carefully avoided using the abbreviation "MDS" outside of product codes, due to legal action by Mohawk Data Sciences Corporation. --- src/mame/intel/imds2.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mame/intel/imds2.cpp b/src/mame/intel/imds2.cpp index 78b03d12e2630..88ce053b05480 100644 --- a/src/mame/intel/imds2.cpp +++ b/src/mame/intel/imds2.cpp @@ -2,7 +2,7 @@ // copyright-holders:F. Ulivi // // *************************************** -// Driver for Intel Intellec MDS series-II +// Driver for Intel Intellec Series II MDS // *************************************** // // Documentation used for this driver: @@ -13,7 +13,9 @@ // // All these manuals are available on http://www.bitsavers.org // -// An Intellec MDS series-II is composed of the following boards: +// The default configuration emulated by this driver is equivalent to a Model 225 MDS. +// +// An Intellec Series II MDS is composed of the following boards: // // ********** // Integrated Processor Card (IPC) or Integrated Processor Board (IPB) @@ -347,4 +349,4 @@ ROM_END /* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME */ -COMP( 1979, imds2, 0, 0, imds2, imds2, imds2_state, empty_init, "Intel", "Intellec MDS-II", 0) +COMP( 1979, imds2, 0, 0, imds2, imds2, imds2_state, empty_init, "Intel", "Intellec Series II Microcomputer Development System, Model 225", 0) From 88c40c8e92dff6fb342e3e7ccc46445439a891e2 Mon Sep 17 00:00:00 2001 From: Googulator Date: Fri, 28 Feb 2025 18:05:54 +0100 Subject: [PATCH 11/11] ipc: unmapped memory addresses and IO ports return 0, not 0xFF Both the IPB and IPC have pull-up resistors on the output (system-facing) side of the system data bus transceiver(s). Since these are inverting transceivers, a pull-up on the output has equivalent effect to a pull-down on the input (CPU-facing) side. The data bus is shared between I/O and memory accesses, therefore both unmapped memory and unmapped I/O ports return all zeros, not all ones. This should fix the "DISK ERROR" message shown by both IPB and IPC on startup. --- src/mame/intel/ipc.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mame/intel/ipc.cpp b/src/mame/intel/ipc.cpp index 630a47db40154..0d1bf5a815040 100644 --- a/src/mame/intel/ipc.cpp +++ b/src/mame/intel/ipc.cpp @@ -81,7 +81,7 @@ class ipc_state : public driver_device void ipc_state::ipb_mem_map(address_map &map) { - map.unmap_value_high(); + map.unmap_value_low(); map(0x0000, 0x7fff).ram(); // selectively map the boot/diagnostic segment @@ -100,7 +100,7 @@ void ipc_state::ipb_mem_map(address_map &map) void ipc_state::ipc_mem_map(address_map &map) { - map.unmap_value_high(); + map.unmap_value_low(); map(0x0000, 0xffff).ram(); // selectively map the boot/diagnostic segment @@ -118,7 +118,7 @@ void ipc_state::ipc_mem_map(address_map &map) void ipc_state::io_map(address_map &map) { - map.unmap_value_high(); + map.unmap_value_low(); map.global_mask(0xff); map(0xf0, 0xf3).rw("pit", FUNC(pit8253_device::read), FUNC(pit8253_device::write)); map(0xf4, 0xf5).rw("uart1", FUNC(i8251_device::read), FUNC(i8251_device::write));