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processador-de-batata.qsf
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processador-de-batata.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 15:09:22 April 09, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# processador-de-batata_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY processing_unit
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:09:22 APRIL 09, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR "/home/max/faculdade/processador-de-batata/simulation/qsim/" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_M23 -to reset
set_location_assignment PIN_Y23 -to switches[17]
set_location_assignment PIN_Y24 -to switches[16]
set_location_assignment PIN_AA22 -to switches[15]
set_location_assignment PIN_AA23 -to switches[14]
set_location_assignment PIN_AA24 -to switches[13]
set_location_assignment PIN_AB23 -to switches[12]
set_location_assignment PIN_AB24 -to switches[11]
set_location_assignment PIN_AC24 -to switches[10]
set_location_assignment PIN_AB25 -to switches[9]
set_location_assignment PIN_AC25 -to switches[8]
set_location_assignment PIN_AB26 -to switches[7]
set_location_assignment PIN_AD26 -to switches[6]
set_location_assignment PIN_AC26 -to switches[5]
set_location_assignment PIN_AB27 -to switches[4]
set_location_assignment PIN_AD27 -to switches[3]
set_location_assignment PIN_AC27 -to switches[2]
set_location_assignment PIN_AC28 -to switches[1]
set_location_assignment PIN_AB28 -to switches[0]
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_Y2 -to clock_50
set_location_assignment PIN_R24 -to button_clock
set_location_assignment PIN_G18 -to display_0[0]
set_location_assignment PIN_F22 -to display_0[1]
set_location_assignment PIN_E17 -to display_0[2]
set_location_assignment PIN_L26 -to display_0[3]
set_location_assignment PIN_L25 -to display_0[4]
set_location_assignment PIN_J22 -to display_0[5]
set_location_assignment PIN_H22 -to display_0[6]
set_location_assignment PIN_M24 -to display_1[0]
set_location_assignment PIN_Y22 -to display_1[1]
set_location_assignment PIN_W21 -to display_1[2]
set_location_assignment PIN_W22 -to display_1[3]
set_location_assignment PIN_W25 -to display_1[4]
set_location_assignment PIN_U23 -to display_1[5]
set_location_assignment PIN_U24 -to display_1[6]
set_location_assignment PIN_AA25 -to display_2[0]
set_location_assignment PIN_AA26 -to display_2[1]
set_location_assignment PIN_Y25 -to display_2[2]
set_location_assignment PIN_W26 -to display_2[3]
set_location_assignment PIN_Y26 -to display_2[4]
set_location_assignment PIN_W27 -to display_2[5]
set_location_assignment PIN_W28 -to display_2[6]
set_location_assignment PIN_V21 -to display_3[0]
set_location_assignment PIN_U21 -to display_3[1]
set_location_assignment PIN_AB20 -to display_3[2]
set_location_assignment PIN_AA21 -to display_3[3]
set_location_assignment PIN_AD24 -to display_3[4]
set_location_assignment PIN_AF23 -to display_3[5]
set_location_assignment PIN_Y19 -to display_3[6]
set_location_assignment PIN_AB19 -to display_4[0]
set_location_assignment PIN_AA19 -to display_4[1]
set_location_assignment PIN_AG21 -to display_4[2]
set_location_assignment PIN_AH21 -to display_4[3]
set_location_assignment PIN_AE19 -to display_4[4]
set_location_assignment PIN_AF19 -to display_4[5]
set_location_assignment PIN_AE18 -to display_4[6]
set_location_assignment PIN_AD18 -to display_5[0]
set_location_assignment PIN_AC18 -to display_5[1]
set_location_assignment PIN_AB18 -to display_5[2]
set_location_assignment PIN_AH19 -to display_5[3]
set_location_assignment PIN_AG19 -to display_5[4]
set_location_assignment PIN_AF18 -to display_5[5]
set_location_assignment PIN_AH18 -to display_5[6]
set_location_assignment PIN_AA17 -to display_6[0]
set_location_assignment PIN_AB16 -to display_6[1]
set_location_assignment PIN_AA16 -to display_6[2]
set_location_assignment PIN_AB17 -to display_6[3]
set_location_assignment PIN_AB15 -to display_6[4]
set_location_assignment PIN_AA15 -to display_6[5]
set_location_assignment PIN_AC17 -to display_6[6]
set_location_assignment PIN_AD17 -to display_7[0]
set_location_assignment PIN_AE17 -to display_7[1]
set_location_assignment PIN_AG17 -to display_7[2]
set_location_assignment PIN_AH17 -to display_7[3]
set_location_assignment PIN_AF17 -to display_7[4]
set_location_assignment PIN_AG18 -to display_7[5]
set_location_assignment PIN_AA14 -to display_7[6]
set_location_assignment PIN_E21 -to flag_write
set_global_assignment -name VERILOG_FILE frequency_divider.v
set_global_assignment -name VERILOG_FILE bin_to_7seg.v
set_global_assignment -name VERILOG_FILE DeBounce.v
set_global_assignment -name VERILOG_FILE alu.v
set_global_assignment -name VERILOG_FILE extender.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name VERILOG_FILE register_base.v
set_global_assignment -name VERILOG_FILE program_counter.v
set_global_assignment -name VERILOG_FILE memory_data.v
set_global_assignment -name VERILOG_FILE processing_unit.v
set_global_assignment -name VERILOG_FILE instruction_data.v
set_global_assignment -name VERILOG_FILE output_data.v
set_global_assignment -name VERILOG_FILE mux_2.v
set_global_assignment -name VERILOG_FILE mux_4.v
set_global_assignment -name VERILOG_FILE control_unit.v
set_global_assignment -name VERILOG_FILE bin_to_dec.v
set_global_assignment -name SDC_FILE "processador-de-batata.sdc"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "FAST FIT"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top