{"payload":{"header_redesign_enabled":false,"results":[{"id":"182362084","archived":false,"color":"#b2b7f8","followers":15,"has_funding_file":false,"hl_name":"maxs-well/USB_Ctrl","hl_trunc_description":"USB2.0 Verilog","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":182362084,"name":"USB_Ctrl","owner_id":20146936,"owner_login":"maxs-well","updated_at":"2019-04-21T04:31:23.447Z","has_issues":true}},"sponsorable":false,"topics":["usb","cyclone","verilog","altera","quartus","usb2","cy7c68013a"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":73,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Amaxs-well%252FUSB_Ctrl%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/maxs-well/USB_Ctrl/star":{"post":"0oEVy0-RMYB8Bi2hWY_VIOKdnGqSqbfR4Cdg91S3hpkP2kuomM4RDP-0CNrvnIHcLDXS_xrJ5GtWiwndXvbiFQ"},"/maxs-well/USB_Ctrl/unstar":{"post":"bgqFZJSsoVeZDDg7AeIkEq7xu0FizD3uctjsYaaaMOh-W0XIIHHW6Nzm3yDQwBaXOEWZdNm9iaEgvA6lLhuGFQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"k6Wz4Nr45Hnw4RUqSNOnJ_iIM1_uSYGOzftTgF1-I7oZFKIKwJz3DF61B5INSiMdtKJrjwdQ3ZHCDTsiSLSFNg"}}},"title":"Repository search results"}