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ElectronicClock.rpt
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Loading plugins phase: Elapsed time ==> 0s.236ms
<CYPRESSTAG name="CyDsfit arguments...">
cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Users\robom\OneDrive\University\Darmstadt\Embedded Architecture and Applications\Labs\Lab 2 - Electronic Clock\ElectronicClock.cydsn\ElectronicClock.cyprj -d CY8C5888LTI-LP097 -s C:\Users\robom\OneDrive\University\Darmstadt\Embedded Architecture and Applications\Labs\Lab 2 - Electronic Clock\ElectronicClock.cydsn\Generated_Source\PSoC5 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
</CYPRESSTAG>
<CYPRESSTAG name="Design elaboration results...">
ADD: sdb.M0065: information: Analog terminal "vdac_ref" on ADC_SAR_SEQ_v2_10 is unconnected.
* C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\ADC_SAR_SEQ_v2_10\PSoC5\ADC_SAR_SEQ_v2_10.cysch (Signal: vdac_ref)
* C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\ADC_SAR_SEQ_v2_10\PSoC5\ADC_SAR_SEQ_v2_10.cysch (Shape_798)
* C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\ADC_SAR_SEQ_v2_10\PSoC5\ADC_SAR_SEQ_v2_10.cysch (Shape_885)
ADD: fit.M0032: warning: Clock Warning: (TFT_SPI_IntClock's accuracy range '72 MHz +/- 0.25%, (71.82 MHz - 72.18 MHz)' is not within the specified tolerance range '66 MHz +/- 5%, (62.7 MHz - 69.3 MHz)'.).
* C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\SPI_Master_v2_50\SPI_Master_v2_50.cysch (Instance:IntClock)
* C:\Users\robom\OneDrive\University\Darmstadt\Embedded Architecture and Applications\Labs\Lab 2 - Electronic Clock\ElectronicClock.cydsn\ElectronicClock.cydwr (TFT_SPI_IntClock)
</CYPRESSTAG>
Elaboration phase: Elapsed time ==> 3s.425ms
<CYPRESSTAG name="HDL generation results...">
</CYPRESSTAG>
HDL generation phase: Elapsed time ==> 0s.139ms
<CYPRESSTAG name="Synthesis results...">
| | | | | | |
_________________
-| |-
-| |-
-| |-
-| CYPRESS |-
-| |-
-| |- Warp Verilog Synthesis Compiler: Version 6.3 IR 41
-| |- Copyright (C) 1991-2001 Cypress Semiconductor
|_______________|
| | | | | | |
======================================================================
Compiling: ElectronicClock.v
Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\bin\warp.exe
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\robom\OneDrive\University\Darmstadt\Embedded Architecture and Applications\Labs\Lab 2 - Electronic Clock\ElectronicClock.cydsn\ElectronicClock.cyprj -dcpsoc3 ElectronicClock.v -verilog
======================================================================
======================================================================
Compiling: ElectronicClock.v
Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\bin\warp.exe
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\robom\OneDrive\University\Darmstadt\Embedded Architecture and Applications\Labs\Lab 2 - Electronic Clock\ElectronicClock.cydsn\ElectronicClock.cyprj -dcpsoc3 ElectronicClock.v -verilog
======================================================================
======================================================================
Compiling: ElectronicClock.v
Program : vlogfe
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\robom\OneDrive\University\Darmstadt\Embedded Architecture and Applications\Labs\Lab 2 - Electronic Clock\ElectronicClock.cydsn\ElectronicClock.cyprj -dcpsoc3 -verilog ElectronicClock.v
======================================================================
vlogfe V6.3 IR 41: Verilog parser
Sun Apr 02 19:22:25 2023
======================================================================
Compiling: ElectronicClock.v
Program : vpp
Options : -yv2 -q10 ElectronicClock.v
======================================================================
vpp V6.3 IR 41: Verilog Pre-Processor
Sun Apr 02 19:22:26 2023
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\CyControlReg_v1_80\CyControlReg_v1_80.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_PWM_v3_30\B_PWM_v3_30.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\ADC_AMUX_v2_0\ADC_AMUX_v2_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_vref_v1_70\cy_vref_v1_70.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\bADC_SAR_SEQ_v2_0\bADC_SAR_SEQ_v2_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_sync_v1_0\cy_sync_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_50\B_SPI_Master_v2_50.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'
vpp: No errors.
Library 'work' => directory 'lcpsoc3'
General_symbol_table
General_symbol_table
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Using control file 'ElectronicClock.ctl'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1113, col 55): Note: Substituting module 'add_vv_vv' for '+'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1122, col 48): Note: Substituting module 'cmp_vv_vv' for '<'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1122, col 77): Note: Substituting module 'cmp_vv_vv' for '<'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1389, col 59): Note: Substituting module 'cmp_vv_vv' for '<'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1424, col 61): Note: Substituting module 'cmp_vv_vv' for '/='.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1547, col 106): Note: Substituting module 'cmp_vv_vv' for '<'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1603, col 68): Note: Substituting module 'cmp_vv_vv' for '<'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v (line 1604, col 68): Note: Substituting module 'cmp_vv_vv' for '<'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_PWM_v3_30\B_PWM_v3_30.v (line 947, col 46): Note: Substituting module 'sub_vi_vv' for '-'.
C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_PWM_v3_30\B_PWM_v3_30.v (line 977, col 46): Note: Substituting module 'add_vi_vv' for '+'.
ElectronicClock.v (line 1166, col 82): Note: Substituting module 'cmp_vv_vv' for '='.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'.
vlogfe: No errors.
======================================================================
Compiling: ElectronicClock.v
Program : tovif
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\robom\OneDrive\University\Darmstadt\Embedded Architecture and Applications\Labs\Lab 2 - Electronic Clock\ElectronicClock.cydsn\ElectronicClock.cyprj -dcpsoc3 -verilog ElectronicClock.v
======================================================================
tovif V6.3 IR 41: High-level synthesis
Sun Apr 02 19:22:27 2023
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'C:\Users\robom\OneDrive\University\Darmstadt\Embedded Architecture and Applications\Labs\Lab 2 - Electronic Clock\ElectronicClock.cydsn\codegentemp\ElectronicClock.ctl'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\CyControlReg_v1_80\CyControlReg_v1_80.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'.
Linking 'C:\Users\robom\OneDrive\University\Darmstadt\Embedded Architecture and Applications\Labs\Lab 2 - Electronic Clock\ElectronicClock.cydsn\codegentemp\ElectronicClock.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_PWM_v3_30\B_PWM_v3_30.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\ADC_AMUX_v2_0\ADC_AMUX_v2_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_vref_v1_70\cy_vref_v1_70.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\bADC_SAR_SEQ_v2_0\bADC_SAR_SEQ_v2_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_sync_v1_0\cy_sync_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_50\B_SPI_Master_v2_50.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mcompare.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\lcpsoc3\stdlogic\mod_cnst.vif'.
tovif: No errors.
======================================================================
Compiling: ElectronicClock.v
Program : topld
Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\robom\OneDrive\University\Darmstadt\Embedded Architecture and Applications\Labs\Lab 2 - Electronic Clock\ElectronicClock.cydsn\ElectronicClock.cyprj -dcpsoc3 -verilog ElectronicClock.v
======================================================================
topld V6.3 IR 41: Synthesis and optimization
Sun Apr 02 19:22:29 2023
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'C:\Users\robom\OneDrive\University\Darmstadt\Embedded Architecture and Applications\Labs\Lab 2 - Electronic Clock\ElectronicClock.cydsn\codegentemp\ElectronicClock.ctl'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\CyControlReg_v1_80\CyControlReg_v1_80.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'.
Linking 'C:\Users\robom\OneDrive\University\Darmstadt\Embedded Architecture and Applications\Labs\Lab 2 - Electronic Clock\ElectronicClock.cydsn\codegentemp\ElectronicClock.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_UART_v2_50\B_UART_v2_50.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_PWM_v3_30\B_PWM_v3_30.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\ADC_AMUX_v2_0\ADC_AMUX_v2_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_vref_v1_70\cy_vref_v1_70.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\bADC_SAR_SEQ_v2_0\bADC_SAR_SEQ_v2_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_sync_v1_0\cy_sync_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_50\B_SPI_Master_v2_50.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mcompare.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\lcpsoc3\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.
----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
User names
\UART_LOG:BUART:reset_sr\
Net_2068
Net_2064
\UART_LOG:BUART:sRX:s23Poll:MODULE_2:g2:a0:b_1\
\UART_LOG:BUART:sRX:s23Poll:MODULE_2:g2:a0:b_0\
\UART_LOG:BUART:sRX:s23Poll:MODULE_3:g2:a0:gta_0\
\UART_LOG:BUART:sRX:s23Poll:MODULE_4:g2:a0:gta_0\
Net_2061
\UART_LOG:BUART:sRX:MODULE_5:g2:a0:gta_0\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:gx:u0:albi_1\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:gx:u0:agbi_1\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:gx:u0:lt_0\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:gx:u0:gt_0\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:gx:u0:lti_0\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:gx:u0:gti_0\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:gx:u0:albi_0\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:gx:u0:agbi_0\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:xeq\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:xlt\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:xlte\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:xgt\
\UART_LOG:BUART:sRX:MODULE_6:g1:a0:xgte\
\UART_LOG:BUART:sRX:MODULE_6:lt\
\UART_LOG:BUART:sRX:MODULE_6:eq\
\UART_LOG:BUART:sRX:MODULE_6:gt\
\UART_LOG:BUART:sRX:MODULE_6:gte\
\UART_LOG:BUART:sRX:MODULE_6:lte\
\RGB_PWM_red:PWMUDB:km_run\
\RGB_PWM_red:PWMUDB:ctrl_cmpmode2_2\
\RGB_PWM_red:PWMUDB:ctrl_cmpmode2_1\
\RGB_PWM_red:PWMUDB:ctrl_cmpmode2_0\
\RGB_PWM_red:PWMUDB:ctrl_cmpmode1_2\
\RGB_PWM_red:PWMUDB:ctrl_cmpmode1_1\
\RGB_PWM_red:PWMUDB:ctrl_cmpmode1_0\
\RGB_PWM_red:PWMUDB:capt_rising\
\RGB_PWM_red:PWMUDB:capt_falling\
\RGB_PWM_red:PWMUDB:trig_rise\
\RGB_PWM_red:PWMUDB:trig_fall\
\RGB_PWM_red:PWMUDB:sc_kill\
\RGB_PWM_red:PWMUDB:min_kill\
\RGB_PWM_red:PWMUDB:km_tc\
\RGB_PWM_red:PWMUDB:db_tc\
\RGB_PWM_red:PWMUDB:dith_sel\
\RGB_PWM_red:PWMUDB:compare2\
\RGB_PWM_red:Net_101\
Net_2076
Net_2077
\RGB_PWM_red:PWMUDB:cmp2\
\RGB_PWM_red:PWMUDB:MODULE_7:b_31\
\RGB_PWM_red:PWMUDB:MODULE_7:b_30\
\RGB_PWM_red:PWMUDB:MODULE_7:b_29\
\RGB_PWM_red:PWMUDB:MODULE_7:b_28\
\RGB_PWM_red:PWMUDB:MODULE_7:b_27\
\RGB_PWM_red:PWMUDB:MODULE_7:b_26\
\RGB_PWM_red:PWMUDB:MODULE_7:b_25\
\RGB_PWM_red:PWMUDB:MODULE_7:b_24\
\RGB_PWM_red:PWMUDB:MODULE_7:b_23\
\RGB_PWM_red:PWMUDB:MODULE_7:b_22\
\RGB_PWM_red:PWMUDB:MODULE_7:b_21\
\RGB_PWM_red:PWMUDB:MODULE_7:b_20\
\RGB_PWM_red:PWMUDB:MODULE_7:b_19\
\RGB_PWM_red:PWMUDB:MODULE_7:b_18\
\RGB_PWM_red:PWMUDB:MODULE_7:b_17\
\RGB_PWM_red:PWMUDB:MODULE_7:b_16\
\RGB_PWM_red:PWMUDB:MODULE_7:b_15\
\RGB_PWM_red:PWMUDB:MODULE_7:b_14\
\RGB_PWM_red:PWMUDB:MODULE_7:b_13\
\RGB_PWM_red:PWMUDB:MODULE_7:b_12\
\RGB_PWM_red:PWMUDB:MODULE_7:b_11\
\RGB_PWM_red:PWMUDB:MODULE_7:b_10\
\RGB_PWM_red:PWMUDB:MODULE_7:b_9\
\RGB_PWM_red:PWMUDB:MODULE_7:b_8\
\RGB_PWM_red:PWMUDB:MODULE_7:b_7\
\RGB_PWM_red:PWMUDB:MODULE_7:b_6\
\RGB_PWM_red:PWMUDB:MODULE_7:b_5\
\RGB_PWM_red:PWMUDB:MODULE_7:b_4\
\RGB_PWM_red:PWMUDB:MODULE_7:b_3\
\RGB_PWM_red:PWMUDB:MODULE_7:b_2\
\RGB_PWM_red:PWMUDB:MODULE_7:b_1\
\RGB_PWM_red:PWMUDB:MODULE_7:b_0\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_31\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_30\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_29\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_28\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_27\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_26\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_25\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_24\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_31\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_30\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_29\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_28\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_27\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_26\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_25\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_24\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_23\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_22\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_21\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_20\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_19\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_18\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_17\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_16\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_15\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_14\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_13\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_12\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_11\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_10\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_9\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_8\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_7\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_6\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_5\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_4\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_3\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_2\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_1\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:b_0\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_31\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_30\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_29\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_28\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_27\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_26\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_25\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_24\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_23\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_22\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_21\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_20\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_19\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_18\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_17\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_16\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_15\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_14\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_13\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_12\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_11\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_10\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_9\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_8\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_7\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_6\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_5\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_4\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_3\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:s_2\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_31\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_30\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_29\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_28\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_27\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_26\
\RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:c_25\
Net_2072
Net_2079
\RGB_PWM_red:Net_113\
\RGB_PWM_red:Net_107\
\RGB_PWM_red:Net_114\
\RGB_PWM_green:PWMUDB:km_run\
\RGB_PWM_green:PWMUDB:ctrl_cmpmode2_2\
\RGB_PWM_green:PWMUDB:ctrl_cmpmode2_1\
\RGB_PWM_green:PWMUDB:ctrl_cmpmode2_0\
\RGB_PWM_green:PWMUDB:ctrl_cmpmode1_2\
\RGB_PWM_green:PWMUDB:ctrl_cmpmode1_1\
\RGB_PWM_green:PWMUDB:ctrl_cmpmode1_0\
\RGB_PWM_green:PWMUDB:capt_rising\
\RGB_PWM_green:PWMUDB:capt_falling\
\RGB_PWM_green:PWMUDB:trig_rise\
\RGB_PWM_green:PWMUDB:trig_fall\
\RGB_PWM_green:PWMUDB:sc_kill\
\RGB_PWM_green:PWMUDB:min_kill\
\RGB_PWM_green:PWMUDB:km_tc\
\RGB_PWM_green:PWMUDB:db_tc\
\RGB_PWM_green:PWMUDB:dith_sel\
\RGB_PWM_green:PWMUDB:compare2\
\RGB_PWM_green:Net_101\
Net_2089
Net_2090
\RGB_PWM_green:PWMUDB:cmp2\
\RGB_PWM_green:PWMUDB:MODULE_8:b_31\
\RGB_PWM_green:PWMUDB:MODULE_8:b_30\
\RGB_PWM_green:PWMUDB:MODULE_8:b_29\
\RGB_PWM_green:PWMUDB:MODULE_8:b_28\
\RGB_PWM_green:PWMUDB:MODULE_8:b_27\
\RGB_PWM_green:PWMUDB:MODULE_8:b_26\
\RGB_PWM_green:PWMUDB:MODULE_8:b_25\
\RGB_PWM_green:PWMUDB:MODULE_8:b_24\
\RGB_PWM_green:PWMUDB:MODULE_8:b_23\
\RGB_PWM_green:PWMUDB:MODULE_8:b_22\
\RGB_PWM_green:PWMUDB:MODULE_8:b_21\
\RGB_PWM_green:PWMUDB:MODULE_8:b_20\
\RGB_PWM_green:PWMUDB:MODULE_8:b_19\
\RGB_PWM_green:PWMUDB:MODULE_8:b_18\
\RGB_PWM_green:PWMUDB:MODULE_8:b_17\
\RGB_PWM_green:PWMUDB:MODULE_8:b_16\
\RGB_PWM_green:PWMUDB:MODULE_8:b_15\
\RGB_PWM_green:PWMUDB:MODULE_8:b_14\
\RGB_PWM_green:PWMUDB:MODULE_8:b_13\
\RGB_PWM_green:PWMUDB:MODULE_8:b_12\
\RGB_PWM_green:PWMUDB:MODULE_8:b_11\
\RGB_PWM_green:PWMUDB:MODULE_8:b_10\
\RGB_PWM_green:PWMUDB:MODULE_8:b_9\
\RGB_PWM_green:PWMUDB:MODULE_8:b_8\
\RGB_PWM_green:PWMUDB:MODULE_8:b_7\
\RGB_PWM_green:PWMUDB:MODULE_8:b_6\
\RGB_PWM_green:PWMUDB:MODULE_8:b_5\
\RGB_PWM_green:PWMUDB:MODULE_8:b_4\
\RGB_PWM_green:PWMUDB:MODULE_8:b_3\
\RGB_PWM_green:PWMUDB:MODULE_8:b_2\
\RGB_PWM_green:PWMUDB:MODULE_8:b_1\
\RGB_PWM_green:PWMUDB:MODULE_8:b_0\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_31\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_30\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_29\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_28\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_27\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_26\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_25\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_24\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_31\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_30\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_29\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_28\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_27\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_26\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_25\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_24\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_23\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_22\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_21\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_20\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_19\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_18\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_17\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_16\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_15\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_14\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_13\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_12\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_11\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_10\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_9\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_8\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_7\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_6\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_5\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_4\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_3\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_2\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_1\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:b_0\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_31\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_30\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_29\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_28\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_27\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_26\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_25\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_24\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_23\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_22\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_21\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_20\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_19\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_18\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_17\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_16\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_15\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_14\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_13\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_12\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_11\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_10\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_9\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_8\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_7\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_6\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_5\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_4\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_3\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:s_2\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_31\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_30\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_29\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_28\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_27\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_26\
\RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:c_25\
Net_2085
Net_2092
\RGB_PWM_green:Net_113\
\RGB_PWM_green:Net_107\
\RGB_PWM_green:Net_114\
\RGB_PWM_blue:PWMUDB:km_run\
\RGB_PWM_blue:PWMUDB:ctrl_cmpmode2_2\
\RGB_PWM_blue:PWMUDB:ctrl_cmpmode2_1\
\RGB_PWM_blue:PWMUDB:ctrl_cmpmode2_0\
\RGB_PWM_blue:PWMUDB:ctrl_cmpmode1_2\
\RGB_PWM_blue:PWMUDB:ctrl_cmpmode1_1\
\RGB_PWM_blue:PWMUDB:ctrl_cmpmode1_0\
\RGB_PWM_blue:PWMUDB:capt_rising\
\RGB_PWM_blue:PWMUDB:capt_falling\
\RGB_PWM_blue:PWMUDB:trig_rise\
\RGB_PWM_blue:PWMUDB:trig_fall\
\RGB_PWM_blue:PWMUDB:sc_kill\
\RGB_PWM_blue:PWMUDB:min_kill\
\RGB_PWM_blue:PWMUDB:km_tc\
\RGB_PWM_blue:PWMUDB:db_tc\
\RGB_PWM_blue:PWMUDB:dith_sel\
\RGB_PWM_blue:PWMUDB:compare2\
\RGB_PWM_blue:Net_101\
Net_2101
Net_2102
\RGB_PWM_blue:PWMUDB:cmp2\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_31\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_30\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_29\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_28\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_27\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_26\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_25\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_24\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_23\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_22\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_21\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_20\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_19\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_18\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_17\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_16\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_15\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_14\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_13\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_12\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_11\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_10\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_9\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_8\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_7\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_6\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_5\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_4\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_3\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_2\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_1\
\RGB_PWM_blue:PWMUDB:MODULE_9:b_0\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_31\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_30\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_29\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_28\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_27\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_26\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_25\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_24\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_31\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_30\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_29\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_28\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_27\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_26\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_25\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_24\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_23\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_22\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_21\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_20\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_19\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_18\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_17\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_16\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_15\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_14\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_13\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_12\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_11\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_10\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_9\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_8\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_7\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_6\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_5\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_4\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_3\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_2\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_1\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:b_0\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_31\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_30\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_29\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_28\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_27\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_26\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_25\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_24\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_23\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_22\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_21\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_20\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_19\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_18\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_17\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_16\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_15\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_14\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_13\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_12\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_11\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_10\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_9\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_8\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_7\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_6\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_5\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_4\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_3\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:s_2\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:g1:z1:s0:g1:u0:c_31\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:g1:z1:s0:g1:u0:c_30\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:g1:z1:s0:g1:u0:c_29\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:g1:z1:s0:g1:u0:c_28\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:g1:z1:s0:g1:u0:c_27\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:g1:z1:s0:g1:u0:c_26\
\RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:g1:z1:s0:g1:u0:c_25\
Net_2097
Net_2104
\RGB_PWM_blue:Net_113\
\RGB_PWM_blue:Net_107\
\RGB_PWM_blue:Net_114\
\JOYSTICK_ADC_XY:SAR:Net_221\
\JOYSTICK_ADC_XY:SAR:Net_383\
\JOYSTICK_ADC_XY:bSAR_SEQ:sw_soc\
\JOYSTICK_ADC_XY:soc_out\
\JOYSTICK_ADC_XY:Net_3905\
\JOYSTICK_ADC_XY:Net_3867\
\JOYSTICK_ADC_XY:MODULE_1:g1:a0:gx:u0:albi_2\
\JOYSTICK_ADC_XY:MODULE_1:g1:a0:gx:u0:agbi_2\
\JOYSTICK_ADC_XY:MODULE_1:g1:a0:gx:u0:albi_1\
\JOYSTICK_ADC_XY:MODULE_1:g1:a0:gx:u0:agbi_1\
\JOYSTICK_ADC_XY:MODULE_1:g1:a0:gx:u0:albi_0\
\JOYSTICK_ADC_XY:MODULE_1:g1:a0:gx:u0:agbi_0\
\JOYSTICK_ADC_XY:MODULE_1:g1:a0:xneq\
\JOYSTICK_ADC_XY:MODULE_1:g1:a0:xlt\
\JOYSTICK_ADC_XY:MODULE_1:g1:a0:xlte\
\JOYSTICK_ADC_XY:MODULE_1:g1:a0:xgt\
\JOYSTICK_ADC_XY:MODULE_1:g1:a0:xgte\
\JOYSTICK_ADC_XY:MODULE_1:lt\
\JOYSTICK_ADC_XY:MODULE_1:gt\
\JOYSTICK_ADC_XY:MODULE_1:gte\
\JOYSTICK_ADC_XY:MODULE_1:lte\
\JOYSTICK_ADC_XY:MODULE_1:neq\
\TFT_SPI:BSPIM:mosi_after_ld\
\TFT_SPI:BSPIM:so_send\
\TFT_SPI:BSPIM:mosi_fin\
\TFT_SPI:BSPIM:mosi_cpha_0\
\TFT_SPI:BSPIM:mosi_cpha_1\
\TFT_SPI:BSPIM:pre_mosi\
\TFT_SPI:BSPIM:dpcounter_zero\
\TFT_SPI:BSPIM:control_7\
\TFT_SPI:BSPIM:control_6\
\TFT_SPI:BSPIM:control_5\
\TFT_SPI:BSPIM:control_4\
\TFT_SPI:BSPIM:control_3\
\TFT_SPI:BSPIM:control_2\
\TFT_SPI:BSPIM:control_1\
\TFT_SPI:BSPIM:control_0\
\TFT_SPI:Net_294\
Net_2220
Net_2227
\TFT_BackLight:Net_114\
\USBUART:dma_complete_0\
\USBUART:Net_1922\
\USBUART:dma_complete_1\
\USBUART:Net_1921\
\USBUART:dma_complete_2\
\USBUART:Net_1920\
\USBUART:dma_complete_3\
\USBUART:Net_1919\
\USBUART:dma_complete_4\
\USBUART:Net_1918\
\USBUART:dma_complete_5\
\USBUART:Net_1917\
\USBUART:dma_complete_6\
\USBUART:Net_1916\
\USBUART:dma_complete_7\
\USBUART:Net_1915\
Synthesized names
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_31\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_30\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_29\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_28\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_27\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_26\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_25\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_24\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_23\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_22\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_21\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_20\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_19\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_18\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_17\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_16\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_15\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_14\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_13\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_12\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_11\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_10\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_9\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_8\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_7\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_6\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_5\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_4\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_3\
\RGB_PWM_red:PWMUDB:add_vi_vv_MODGEN_7_2\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_31\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_30\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_29\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_28\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_27\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_26\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_25\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_24\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_23\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_22\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_21\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_20\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_19\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_18\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_17\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_16\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_15\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_14\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_13\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_12\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_11\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_10\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_9\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_8\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_7\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_6\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_5\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_4\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_3\
\RGB_PWM_green:PWMUDB:add_vi_vv_MODGEN_8_2\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_31\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_30\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_29\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_28\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_27\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_26\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_25\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_24\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_23\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_22\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_21\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_20\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_19\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_18\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_17\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_16\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_15\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_14\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_13\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_12\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_11\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_10\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_9\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_8\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_7\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_6\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_5\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_4\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_3\
\RGB_PWM_blue:PWMUDB:add_vi_vv_MODGEN_9_2\
Deleted 489 User equations/components.
Deleted 90 Synthesized equations/components.
------------------------------------------------------
Alias Detection
------------------------------------------------------
Aliasing one to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__SEVEN_B_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__SEVEN_C_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__SEVEN_D_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__SEVEN_E_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__SEVEN_F_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__SEVEN_G_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__SEVEN_DP_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__SEVEN_SELECT_net_0 to tmpOE__SEVEN_A_net_0
Aliasing \SEVEN_reg:clk\ to zero
Aliasing \SEVEN_reg:rst\ to zero
Aliasing tmpOE__BUTTON_1_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__BUTTON_2_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__BUTTON_3_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__BUTTON_4_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__LED_red_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__LED_yellow_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__LED_green_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__DEBUG_TX_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__DEBUG_RX_net_0 to tmpOE__SEVEN_A_net_0
Aliasing \UART_LOG:BUART:tx_hd_send_break\ to zero
Aliasing \UART_LOG:BUART:HalfDuplexSend\ to zero
Aliasing \UART_LOG:BUART:FinalParityType_1\ to zero
Aliasing \UART_LOG:BUART:FinalParityType_0\ to zero
Aliasing \UART_LOG:BUART:FinalAddrMode_2\ to zero
Aliasing \UART_LOG:BUART:FinalAddrMode_1\ to zero
Aliasing \UART_LOG:BUART:FinalAddrMode_0\ to zero
Aliasing \UART_LOG:BUART:tx_ctrl_mark\ to zero
Aliasing \UART_LOG:BUART:tx_status_6\ to zero
Aliasing \UART_LOG:BUART:tx_status_5\ to zero
Aliasing \UART_LOG:BUART:tx_status_4\ to zero
Aliasing \UART_LOG:BUART:rx_count7_bit8_wire\ to zero
Aliasing \UART_LOG:BUART:sRX:s23Poll:MODULE_2:g2:a0:g1:z1:s0:g1:u0:b_0\ to tmpOE__SEVEN_A_net_0
Aliasing \UART_LOG:BUART:sRX:s23Poll:MODIN4_1\ to \UART_LOG:BUART:sRX:s23Poll:MODIN3_1\
Aliasing \UART_LOG:BUART:sRX:s23Poll:MODIN4_0\ to \UART_LOG:BUART:sRX:s23Poll:MODIN3_0\
Aliasing \UART_LOG:BUART:sRX:s23Poll:MODULE_3:g2:a0:newb_1\ to zero
Aliasing \UART_LOG:BUART:sRX:s23Poll:MODULE_3:g2:a0:newb_0\ to tmpOE__SEVEN_A_net_0
Aliasing \UART_LOG:BUART:sRX:s23Poll:MODIN5_1\ to \UART_LOG:BUART:sRX:s23Poll:MODIN3_1\
Aliasing \UART_LOG:BUART:sRX:s23Poll:MODIN5_0\ to \UART_LOG:BUART:sRX:s23Poll:MODIN3_0\
Aliasing \UART_LOG:BUART:sRX:s23Poll:MODULE_4:g2:a0:newb_1\ to tmpOE__SEVEN_A_net_0
Aliasing \UART_LOG:BUART:sRX:s23Poll:MODULE_4:g2:a0:newb_0\ to zero
Aliasing \UART_LOG:BUART:rx_status_1\ to zero
Aliasing \UART_LOG:BUART:sRX:MODULE_5:g2:a0:newa_6\ to zero
Aliasing \UART_LOG:BUART:sRX:MODULE_5:g2:a0:newa_5\ to zero
Aliasing \UART_LOG:BUART:sRX:MODULE_5:g2:a0:newa_4\ to zero
Aliasing \UART_LOG:BUART:sRX:MODULE_5:g2:a0:newb_6\ to zero
Aliasing \UART_LOG:BUART:sRX:MODULE_5:g2:a0:newb_5\ to zero
Aliasing \UART_LOG:BUART:sRX:MODULE_5:g2:a0:newb_4\ to zero
Aliasing \UART_LOG:BUART:sRX:MODULE_5:g2:a0:newb_3\ to zero
Aliasing \UART_LOG:BUART:sRX:MODULE_5:g2:a0:newb_2\ to tmpOE__SEVEN_A_net_0
Aliasing \UART_LOG:BUART:sRX:MODULE_5:g2:a0:newb_1\ to tmpOE__SEVEN_A_net_0
Aliasing \UART_LOG:BUART:sRX:MODULE_5:g2:a0:newb_0\ to zero
Aliasing \UART_LOG:BUART:sRX:MODULE_6:g1:a0:gx:u0:aeqb_0\ to tmpOE__SEVEN_A_net_0
Aliasing \RGB_PWM_red:PWMUDB:hwCapture\ to zero
Aliasing \RGB_PWM_red:PWMUDB:trig_out\ to tmpOE__SEVEN_A_net_0
Aliasing \RGB_PWM_red:PWMUDB:runmode_enable\\R\ to zero
Aliasing \RGB_PWM_red:PWMUDB:runmode_enable\\S\ to zero
Aliasing \RGB_PWM_red:PWMUDB:ltch_kill_reg\\R\ to zero
Aliasing \RGB_PWM_red:PWMUDB:ltch_kill_reg\\S\ to zero
Aliasing \RGB_PWM_red:PWMUDB:min_kill_reg\\R\ to zero
Aliasing \RGB_PWM_red:PWMUDB:min_kill_reg\\S\ to zero
Aliasing \RGB_PWM_red:PWMUDB:final_kill\ to tmpOE__SEVEN_A_net_0
Aliasing \RGB_PWM_red:PWMUDB:dith_count_1\\R\ to zero
Aliasing \RGB_PWM_red:PWMUDB:dith_count_1\\S\ to zero
Aliasing \RGB_PWM_red:PWMUDB:dith_count_0\\R\ to zero
Aliasing \RGB_PWM_red:PWMUDB:dith_count_0\\S\ to zero
Aliasing \RGB_PWM_red:PWMUDB:cs_addr_0\ to zero
Aliasing \RGB_PWM_red:PWMUDB:pwm1_i\ to zero
Aliasing \RGB_PWM_red:PWMUDB:pwm2_i\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_23\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_22\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_21\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_20\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_19\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_18\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_17\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_16\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_15\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_14\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_13\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_12\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_11\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_10\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_9\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_8\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_7\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_6\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_5\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_4\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_3\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:a_2\ to zero
Aliasing \RGB_PWM_red:PWMUDB:MODULE_7:g2:a0:g1:z1:s0:g1:u0:b_0\ to tmpOE__SEVEN_A_net_0
Aliasing \RGB_PWM_green:PWMUDB:hwCapture\ to zero
Aliasing \RGB_PWM_green:PWMUDB:trig_out\ to tmpOE__SEVEN_A_net_0
Aliasing \RGB_PWM_green:PWMUDB:runmode_enable\\R\ to zero
Aliasing \RGB_PWM_green:PWMUDB:runmode_enable\\S\ to zero
Aliasing \RGB_PWM_green:PWMUDB:ltch_kill_reg\\R\ to zero
Aliasing \RGB_PWM_green:PWMUDB:ltch_kill_reg\\S\ to zero
Aliasing \RGB_PWM_green:PWMUDB:min_kill_reg\\R\ to zero
Aliasing \RGB_PWM_green:PWMUDB:min_kill_reg\\S\ to zero
Aliasing \RGB_PWM_green:PWMUDB:final_kill\ to tmpOE__SEVEN_A_net_0
Aliasing \RGB_PWM_green:PWMUDB:dith_count_1\\R\ to zero
Aliasing \RGB_PWM_green:PWMUDB:dith_count_1\\S\ to zero
Aliasing \RGB_PWM_green:PWMUDB:dith_count_0\\R\ to zero
Aliasing \RGB_PWM_green:PWMUDB:dith_count_0\\S\ to zero
Aliasing \RGB_PWM_green:PWMUDB:cs_addr_0\ to zero
Aliasing \RGB_PWM_green:PWMUDB:pwm1_i\ to zero
Aliasing \RGB_PWM_green:PWMUDB:pwm2_i\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_23\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_22\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_21\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_20\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_19\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_18\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_17\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_16\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_15\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_14\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_13\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_12\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_11\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_10\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_9\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_8\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_7\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_6\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_5\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_4\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_3\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:a_2\ to zero
Aliasing \RGB_PWM_green:PWMUDB:MODULE_8:g2:a0:g1:z1:s0:g1:u0:b_0\ to tmpOE__SEVEN_A_net_0
Aliasing \RGB_PWM_blue:PWMUDB:hwCapture\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:trig_out\ to tmpOE__SEVEN_A_net_0
Aliasing \RGB_PWM_blue:PWMUDB:runmode_enable\\R\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:runmode_enable\\S\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:ltch_kill_reg\\R\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:ltch_kill_reg\\S\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:min_kill_reg\\R\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:min_kill_reg\\S\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:final_kill\ to tmpOE__SEVEN_A_net_0
Aliasing \RGB_PWM_blue:PWMUDB:dith_count_1\\R\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:dith_count_1\\S\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:dith_count_0\\R\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:dith_count_0\\S\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:cs_addr_0\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:pwm1_i\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:pwm2_i\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_23\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_22\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_21\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_20\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_19\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_18\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_17\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_16\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_15\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_14\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_13\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_12\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_11\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_10\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_9\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_8\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_7\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_6\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_5\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_4\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_3\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:a_2\ to zero
Aliasing \RGB_PWM_blue:PWMUDB:MODULE_9:g2:a0:g1:z1:s0:g1:u0:b_0\ to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__RGB_R_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__RGB_G_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__RGB_B_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__BUTTON_JOYSTICK_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__JOYSTICK_X_net_0 to tmpOE__SEVEN_A_net_0
Aliasing tmpOE__JOYSTICK_Y_net_0 to tmpOE__SEVEN_A_net_0
Aliasing \JOYSTICK_ADC_XY:AMuxHw_2_Decoder_enable\ to tmpOE__SEVEN_A_net_0
Aliasing \JOYSTICK_ADC_XY:SAR:vp_ctl_0\ to zero
Aliasing \JOYSTICK_ADC_XY:SAR:vp_ctl_2\ to zero
Aliasing \JOYSTICK_ADC_XY:SAR:vn_ctl_1\ to zero
Aliasing \JOYSTICK_ADC_XY:SAR:vn_ctl_3\ to zero
Aliasing \JOYSTICK_ADC_XY:SAR:vp_ctl_1\ to zero
Aliasing \JOYSTICK_ADC_XY:SAR:vp_ctl_3\ to zero
Aliasing \JOYSTICK_ADC_XY:SAR:vn_ctl_0\ to zero
Aliasing \JOYSTICK_ADC_XY:SAR:vn_ctl_2\ to zero
Aliasing \JOYSTICK_ADC_XY:SAR:soc\ to zero
Aliasing \JOYSTICK_ADC_XY:bSAR_SEQ:status_7\ to zero
Aliasing \JOYSTICK_ADC_XY:bSAR_SEQ:status_6\ to zero
Aliasing \JOYSTICK_ADC_XY:bSAR_SEQ:status_5\ to zero
Aliasing \JOYSTICK_ADC_XY:bSAR_SEQ:status_4\ to zero
Aliasing \JOYSTICK_ADC_XY:bSAR_SEQ:status_3\ to zero
Aliasing \JOYSTICK_ADC_XY:bSAR_SEQ:status_2\ to zero
Aliasing \JOYSTICK_ADC_XY:bSAR_SEQ:status_1\ to zero
Aliasing Net_2204 to \JOYSTICK_ADC_XY:bSAR_SEQ:status_0\
Aliasing \JOYSTICK_ADC_XY:MODULE_1:g1:a0:gx:u0:aeqb_0\ to tmpOE__SEVEN_A_net_0
Aliasing \TFT_SPI:BSPIM:pol_supprt\ to zero
Aliasing \TFT_SPI:BSPIM:tx_status_3\ to \TFT_SPI:BSPIM:load_rx_data\
Aliasing \TFT_SPI:BSPIM:tx_status_6\ to zero
Aliasing \TFT_SPI:BSPIM:tx_status_5\ to zero
Aliasing \TFT_SPI:BSPIM:rx_status_3\ to zero
Aliasing \TFT_SPI:BSPIM:rx_status_2\ to zero
Aliasing \TFT_SPI:BSPIM:rx_status_1\ to zero
Aliasing \TFT_SPI:BSPIM:rx_status_0\ to zero