From cb98848dd6fd9d06f703017b70aa161adcada0f4 Mon Sep 17 00:00:00 2001 From: Madhu Comandur Jagannathan Raghunathan Date: Thu, 21 May 2020 10:09:24 -0700 Subject: [PATCH 1/3] Adding support for Xcelium - Xcelium Makefile, README_XCELIUM --- doc/README_XCELIUM | 57 ++++++++++++++++++++++++++++ sim/rtl_sim/bin/Xcelium_Makefile | 51 +++++++++++++++++++++++++ sim/rtl_sim/run/xcelium_run/Makefile | 1 + 3 files changed, 109 insertions(+) create mode 100644 doc/README_XCELIUM create mode 100644 sim/rtl_sim/bin/Xcelium_Makefile create mode 100644 sim/rtl_sim/run/xcelium_run/Makefile diff --git a/doc/README_XCELIUM b/doc/README_XCELIUM new file mode 100644 index 0000000..06bff52 --- /dev/null +++ b/doc/README_XCELIUM @@ -0,0 +1,57 @@ +SD Card Controller on Xcelium - Source code from [https://github.com/mczerski/SD-card-controller] + +Directory Structure: + . RTL files and Testbench sources: + . rtl/verilog IP core Verilog sources + . bench/verilog Verilog TB files + . The TOP level test is bench/verilog/sd_controller_top_tb.sv which utilizes the sdModel.v. The corresponding RTL file is rtl/verilog/sdc_controller.v + . sim/rtl_sim/log Log dir created during simulation + . sim/rtl_sim/run/xcelium_run simulation run directory for Xcelium + . sim/rtl_sim/bin contains Xcelium_Makefile + +Changes to get the files to run and pass on Xcelium : + + . In bench/verilog/wb_master_behavioral.v, replace 'return' (match exact case and word) with 'return_type'. As per LRM, 'return' is a SV keyword and cannot be used as a variable name. + . In bench/verilog/sd_controller_top_tb.sv, + . add `include of all the *.v files (under bench/verilog/) -> sdModel.v, wb_master_behavioral.v, wb_slave_behavioral.v, wb_bus_mon.v, wb_master32.v + . change the path as -> `define LOG_DIR "../../log", parameter ramdisk="../../bin/ramdisk2.hex", parameter sd_model_log_file="../../log/sd_model.log", parameter wb_memory_file="../../bin/wb_memory.txt" + +Simulation: To start simulation and run all the tests with Xcelium, + +#> cd sim/rtl_sim/run/xcelium_run + +#> make + This runs all the tests and creates separate snapshot directories(*_tb_dir) as well as logs for every test. The logs can be found under *_tb.log + + Every TB is self-checking with assertions. If the log displays - + # testbench name starts.. + # testbench name finish.. + without any assertion in between errors, the test passes. + +#> make *_tb + compiles and executes given testbench. Refers to any individual testbench as listed by print_testbenches target. Example for testbench_name : sd_controller_top_tb + +#> make clean + Removes all log files and snapshots (*_tb_dir) + +#> make print_testbenches + Lists all testbenches. + + +Additional Info : + +EXAMPLE: To run sd_controller_top_tb as a standalone test using xrun commands - + +#> cd sim/rtl_sim/ +#> mkdir log + +#> cd run/xcelium_run + +#> xrun -clean -elaborate -sv ../../../../rtl/verilog/*.v ../../../../bench/verilog/sd_controller_top_tb.sv -incdir ../../../../rtl/verilog/ -incdir ../../../../bench/verilog -xmlibdirname sd_controller_top_tb_dir +This compiles the TOP test and all RTL files and creates a snapshot using -xmlibdirname in the location specified. Creating a specific snapshot for every TB prevents overriding of the same xcelium.d for the tests. + +#> xrun -R -xmlibdirname sd_controller_top_tb_dir +This runs the specified test. Log information is stored in xrun.log + + + diff --git a/sim/rtl_sim/bin/Xcelium_Makefile b/sim/rtl_sim/bin/Xcelium_Makefile new file mode 100644 index 0000000..75a61df --- /dev/null +++ b/sim/rtl_sim/bin/Xcelium_Makefile @@ -0,0 +1,51 @@ +###################################################################### +#### #### +#### WISHBONE SD Card Controller IP Core #### +#### #### +#### Xcelium Makefile #### +#### #### +###################################################################### + + +RUN_DIR = $(shell pwd) +BIN_DIR = $(shell pwd)/../../bin +LOG_DIR = $(shell pwd)/../../log + +WORK_DIR = ../../../../rtl/verilog +TEST_DIR = ../../../../bench/verilog +WORK_SOURCES = $(wildcard $(WORK_DIR)/*.v) +TEST_SOURCES = $(wildcard $(TEST_DIR)/*.sv) $(wildcard $(TEST_DIR)/*.v) + + +all: simulate + + +TESTBENCH_SOURCES = $(shell ls $(TEST_DIR)/*_tb.sv) +TESTBENCHES = $(shell echo $(TESTBENCH_SOURCES) | sed 's:$(TEST_DIR)/::g' | sed 's:\.sv::g') + + +$(LOG_DIR): + mkdir $@ + + +%_tb: $(LOG_DIR) + xrun -sv -clean $(WORK_SOURCES) $(TEST_DIR)/$@.sv -incdir $(WORK_DIR) -incdir $(TEST_DIR) -xmlibdirname $@_dir > $@.log + + +simulate: $(TESTBENCHES) + + +print_work_sources: + echo $(WORK_SOURCES) + +print_test_sources: + echo $(TEST_SOURCES) + +print_testbenches: + echo $(TESTBENCHES) + +clean: + echo "Removing ..." + rm -rfv *.log + rm -rfv *_dir + rm -rfv $(LOG_DIR) diff --git a/sim/rtl_sim/run/xcelium_run/Makefile b/sim/rtl_sim/run/xcelium_run/Makefile new file mode 100644 index 0000000..7d00b4f --- /dev/null +++ b/sim/rtl_sim/run/xcelium_run/Makefile @@ -0,0 +1 @@ +include ../../bin/Xcelium_Makefile From d71f084b7f4fee845ddd5eaa1e6eb5f4de73479a Mon Sep 17 00:00:00 2001 From: madhucjr <65677422+madhucjr@users.noreply.github.com> Date: Sun, 24 May 2020 21:32:58 -0700 Subject: [PATCH 2/3] Add -gui option and some changes to Xcelium Makefile --- sim/rtl_sim/bin/Xcelium_Makefile | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/sim/rtl_sim/bin/Xcelium_Makefile b/sim/rtl_sim/bin/Xcelium_Makefile index 75a61df..3164e49 100644 --- a/sim/rtl_sim/bin/Xcelium_Makefile +++ b/sim/rtl_sim/bin/Xcelium_Makefile @@ -29,7 +29,24 @@ $(LOG_DIR): %_tb: $(LOG_DIR) - xrun -sv -clean $(WORK_SOURCES) $(TEST_DIR)/$@.sv -incdir $(WORK_DIR) -incdir $(TEST_DIR) -xmlibdirname $@_dir > $@.log + @echo " " + @echo "Running $@... " + @echo " " + xrun -sv -clean -elaborate $(WORK_SOURCES) $(TEST_DIR)/$@.sv -incdir $(WORK_DIR) -incdir $(TEST_DIR) -xmlibdirname $@_dir > $@_compile.log + @echo " " + xrun -R -xmlibdirname $@_dir > $@_run.log + @echo " " + @echo "Compile log at $@_compile.log" + @echo "Simulation log at $@_run.log" + @echo " " + +%_tb_gui: $(LOG_DIR) + @echo " " + @echo "Running $@... " + @echo " " + xrun -sv -clean -elaborate $(WORK_SOURCES) $(TEST_DIR)/$(@:_gui=).sv -incdir $(WORK_DIR) -incdir $(TEST_DIR) -xmlibdirname $@_dir -lwdgen -access +rwc + @echo " " + xrun -R -xmlibdirname $@_dir -gui -indago simulate: $(TESTBENCHES) From 8b446600fdaf0b83dd5b41b032d0495bdd574631 Mon Sep 17 00:00:00 2001 From: madhucjr <65677422+madhucjr@users.noreply.github.com> Date: Sun, 24 May 2020 21:34:05 -0700 Subject: [PATCH 3/3] Update README --- doc/README_XCELIUM | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/doc/README_XCELIUM b/doc/README_XCELIUM index 06bff52..7809ca5 100644 --- a/doc/README_XCELIUM +++ b/doc/README_XCELIUM @@ -1,4 +1,4 @@ -SD Card Controller on Xcelium - Source code from [https://github.com/mczerski/SD-card-controller] +SD Card Controller on Xcelium - Directory Structure: . RTL files and Testbench sources: @@ -12,6 +12,8 @@ Directory Structure: Changes to get the files to run and pass on Xcelium : . In bench/verilog/wb_master_behavioral.v, replace 'return' (match exact case and word) with 'return_type'. As per LRM, 'return' is a SV keyword and cannot be used as a variable name. + [Note : A request to make this change to Github Repo for SD Card open source code has been submitted. Check latest file from Github for changes.] + . In bench/verilog/sd_controller_top_tb.sv, . add `include of all the *.v files (under bench/verilog/) -> sdModel.v, wb_master_behavioral.v, wb_slave_behavioral.v, wb_bus_mon.v, wb_master32.v . change the path as -> `define LOG_DIR "../../log", parameter ramdisk="../../bin/ramdisk2.hex", parameter sd_model_log_file="../../log/sd_model.log", parameter wb_memory_file="../../bin/wb_memory.txt" @@ -21,9 +23,9 @@ Simulation: To start simulation and run all the tests with Xcelium, #> cd sim/rtl_sim/run/xcelium_run #> make - This runs all the tests and creates separate snapshot directories(*_tb_dir) as well as logs for every test. The logs can be found under *_tb.log + This compiles and runs all the tests and creates separate snapshot directories(*_tb_dir) as well as logs for every test. The logs can be found under *_tb_compile.log and *_tb_run.log - Every TB is self-checking with assertions. If the log displays - + Every TB is self-checking with assertions. If the run log displays - # testbench name starts.. # testbench name finish.. without any assertion in between errors, the test passes. @@ -31,6 +33,9 @@ Simulation: To start simulation and run all the tests with Xcelium, #> make *_tb compiles and executes given testbench. Refers to any individual testbench as listed by print_testbenches target. Example for testbench_name : sd_controller_top_tb +#> make *_tb_gui + same as *_tb but opens Indago GUI for interactive debug for the given testbench + #> make clean Removes all log files and snapshots (*_tb_dir) @@ -43,6 +48,7 @@ Additional Info : EXAMPLE: To run sd_controller_top_tb as a standalone test using xrun commands - #> cd sim/rtl_sim/ + #> mkdir log #> cd run/xcelium_run @@ -54,4 +60,3 @@ This compiles the TOP test and all RTL files and creates a snapshot using -xmlib This runs the specified test. Log information is stored in xrun.log -