diff --git a/.envrc b/.envrc new file mode 100644 index 0000000..30da14f --- /dev/null +++ b/.envrc @@ -0,0 +1,5 @@ +export DIRENV_WARN_TIMEOUT=20s + +eval "$(devenv direnvrc)" + +use devenv diff --git a/.github/dependabot.yml b/.github/dependabot.yml new file mode 100644 index 0000000..e509831 --- /dev/null +++ b/.github/dependabot.yml @@ -0,0 +1,6 @@ +version: 2 +updates: + - package-ecosystem: "cargo" + directory: "/" + schedule: + interval: "daily" \ No newline at end of file diff --git a/.gitignore b/.gitignore index 1e7caa9..16aef35 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,12 @@ Cargo.lock target/ + +# Devenv +.devenv* +devenv.local.nix + +# direnv +.direnv + +# pre-commit +.pre-commit-config.yaml diff --git a/.gitmodules b/.gitmodules index b961f25..e69de29 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +0,0 @@ -[submodule "crossbeam"] - path = crossbeam - url = https://github.com/crossbeam-rs/crossbeam.git diff --git a/Cargo.toml b/Cargo.toml index de1e236..6b9c464 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -23,10 +23,8 @@ default = ["std"] std = [] [dev-dependencies] -rand = "0.8" -criterion = "0.3" -# TODO: This is only needed for the doctests of cache_padded.rs! Is there a way to avoid this? -crossbeam-utils = { version = "0.8", default-features = false } +rand = "0.9.0" +criterion = "0.5.1" # aggressive optimization for benchmarks [profile.bench] diff --git a/Justfile b/Justfile new file mode 100644 index 0000000..3b5cc31 --- /dev/null +++ b/Justfile @@ -0,0 +1,63 @@ +# Justfile + +# By default, run a full check (check) +default: check + +# Full check: fmt (format check), clippy, tests +check: + @echo "==> Checking format..." + cargo fmt --all -- --check + + @echo "==> Checking clippy..." + cargo clippy --all-targets --all-features -- -D warnings + + @echo "==> Running tests with nextest..." + cargo nextest run --workspace --all-features + + @echo "==> Running audit..." + cargo audit + + @echo "==> Checking outdated dependencies..." + cargo outdated + + @echo "All checks passed!" + +# Code formatting +fmt: + @echo "==> Formatting code..." + cargo fmt --all + +# Running Clippy +clippy: + @echo "==> Clippy linting..." + cargo clippy --all-targets --all-features -- -D warnings + +# Running tests (nextest) +test: + @echo "==> Running tests (debug)..." + cargo nextest run --workspace --all-features + +# Running tests in release build +test-release: + @echo "==> Running tests (release)..." + cargo nextest run --workspace --all-features --release + +# Generating (and opening) documentation +doc: + @echo "==> Building docs..." + cargo doc --no-deps --all-features --open + +# Checking for outdated dependencies +outdated: + @echo "==> Checking outdated dependencies..." + cargo outdated + +# Updating dependencies +update: + @echo "==> Updating dependencies..." + cargo update + +# Checking dependencies for vulnerabilities +audit: + @echo "==> Auditing dependencies..." + cargo audit \ No newline at end of file diff --git a/crossbeam b/crossbeam deleted file mode 160000 index 00283fb..0000000 --- a/crossbeam +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 00283fb1818174c25b02d7f1c883c5e19f8506a4 diff --git a/devenv.lock b/devenv.lock new file mode 100644 index 0000000..c528a55 --- /dev/null +++ b/devenv.lock @@ -0,0 +1,140 @@ +{ + "nodes": { + "devenv": { + "locked": { + "dir": "src/modules", + "lastModified": 1738414267, + "owner": "cachix", + "repo": "devenv", + "rev": "3f49b4afbb9a80b1e81fb6071f59dac152177efa", + "type": "github" + }, + "original": { + "dir": "src/modules", + "owner": "cachix", + "repo": "devenv", + "type": "github" + } + }, + "fenix": { + "inputs": { + "nixpkgs": [ + "nixpkgs" + ], + "rust-analyzer-src": "rust-analyzer-src" + }, + "locked": { + "lastModified": 1738650687, + "owner": "nix-community", + "repo": "fenix", + "rev": "37a1f29ebf98fbbac667730edc5dab4ebe2e3954", + "type": "github" + }, + "original": { + "owner": "nix-community", + "repo": "fenix", + "type": "github" + } + }, + "flake-compat": { + "flake": false, + "locked": { + "lastModified": 1733328505, + "owner": "edolstra", + "repo": "flake-compat", + "rev": "ff81ac966bb2cae68946d5ed5fc4994f96d0ffec", + "type": "github" + }, + "original": { + "owner": "edolstra", + "repo": "flake-compat", + "type": "github" + } + }, + "git-hooks": { + "inputs": { + "flake-compat": "flake-compat", + "gitignore": "gitignore", + "nixpkgs": [ + "nixpkgs" + ] + }, + "locked": { + "lastModified": 1737465171, + "owner": "cachix", + "repo": "git-hooks.nix", + "rev": "9364dc02281ce2d37a1f55b6e51f7c0f65a75f17", + "type": "github" + }, + "original": { + "owner": "cachix", + "repo": "git-hooks.nix", + "type": "github" + } + }, + "gitignore": { + "inputs": { + "nixpkgs": [ + "git-hooks", + "nixpkgs" + ] + }, + "locked": { + "lastModified": 1709087332, + "owner": "hercules-ci", + "repo": "gitignore.nix", + "rev": "637db329424fd7e46cf4185293b9cc8c88c95394", + "type": "github" + }, + "original": { + "owner": "hercules-ci", + "repo": "gitignore.nix", + "type": "github" + } + }, + "nixpkgs": { + "locked": { + "lastModified": 1738703096, + "owner": "NixOS", + "repo": "nixpkgs", + "rev": "f7384aacd0ecd28681a99269ac0dff2c3a805d63", + "type": "github" + }, + "original": { + "owner": "NixOS", + "ref": "nixpkgs-unstable", + "repo": "nixpkgs", + "type": "github" + } + }, + "root": { + "inputs": { + "devenv": "devenv", + "fenix": "fenix", + "git-hooks": "git-hooks", + "nixpkgs": "nixpkgs", + "pre-commit-hooks": [ + "git-hooks" + ] + } + }, + "rust-analyzer-src": { + "flake": false, + "locked": { + "lastModified": 1738698211, + "owner": "rust-lang", + "repo": "rust-analyzer", + "rev": "6fb64beb807b07dc687fd0f00261c7c404a83947", + "type": "github" + }, + "original": { + "owner": "rust-lang", + "ref": "nightly", + "repo": "rust-analyzer", + "type": "github" + } + } + }, + "root": "root", + "version": 7 +} diff --git a/devenv.nix b/devenv.nix new file mode 100644 index 0000000..e6bf68d --- /dev/null +++ b/devenv.nix @@ -0,0 +1,27 @@ +{ pkgs, lib, config, inputs, ... }: + +{ + # https://devenv.sh/packages/ + packages = [ + pkgs.curl + pkgs.git + pkgs.jq + pkgs.rustup + pkgs.sccache + pkgs.cargo-outdated + pkgs.cargo-nextest + pkgs.cargo-audit + pkgs.just + pkgs.tree + ] ++ lib.optionals pkgs.stdenv.isDarwin (with pkgs.darwin.apple_sdk; [ + frameworks.SystemConfiguration + frameworks.Security + frameworks.CoreFoundation + ]); + + # https://devenv.sh/languages/ + languages.nix.enable = true; + languages.rust.enable = true; + + env.RUSTC_WRAPPER = "${pkgs.sccache}/bin/sccache"; +} diff --git a/devenv.yaml b/devenv.yaml new file mode 100644 index 0000000..5fedb91 --- /dev/null +++ b/devenv.yaml @@ -0,0 +1,9 @@ +# yaml-language-server: $schema=https://devenv.sh/devenv.schema.json +inputs: + nixpkgs: + url: github:NixOS/nixpkgs/nixpkgs-unstable + fenix: + url: github:nix-community/fenix + inputs: + nixpkgs: + follows: nixpkgs \ No newline at end of file diff --git a/src/cache_padded.rs b/src/cache_padded.rs deleted file mode 120000 index b6f5124..0000000 --- a/src/cache_padded.rs +++ /dev/null @@ -1 +0,0 @@ -../crossbeam/crossbeam-utils/src/cache_padded.rs \ No newline at end of file diff --git a/src/cache_padded.rs b/src/cache_padded.rs new file mode 100644 index 0000000..69c6524 --- /dev/null +++ b/src/cache_padded.rs @@ -0,0 +1,202 @@ +use core::fmt; +use core::ops::{Deref, DerefMut}; + +/// Pads and aligns a value to the length of a cache line. +/// +/// In concurrent programming, sometimes it is desirable to make sure commonly accessed pieces of +/// data are not placed into the same cache line. Updating an atomic value invalidates the whole +/// cache line it belongs to, which makes the next access to the same cache line slower for other +/// CPU cores. Use `CachePadded` to ensure updating one piece of data doesn't invalidate other +/// cached data. +/// +/// # Size and alignment +/// +/// Cache lines are assumed to be N bytes long, depending on the architecture: +/// +/// * On x86-64, aarch64, and powerpc64, N = 128. +/// * On arm, mips, mips64, sparc, and hexagon, N = 32. +/// * On m68k, N = 16. +/// * On s390x, N = 256. +/// * On all others, N = 64. +/// +/// Note that N is just a reasonable guess and is not guaranteed to match the actual cache line +/// length of the machine the program is running on. On modern Intel architectures, spatial +/// prefetcher is pulling pairs of 64-byte cache lines at a time, so we pessimistically assume that +/// cache lines are 128 bytes long. +/// +/// The size of `CachePadded` is the smallest multiple of N bytes large enough to accommodate +/// a value of type `T`. +/// +/// The alignment of `CachePadded` is the maximum of N bytes and the alignment of `T`. +/// +/// # Examples +/// +/// Alignment and padding: +/// +/// ``` +/// use crossbeam_utils::CachePadded; +/// +/// let array = [CachePadded::new(1i8), CachePadded::new(2i8)]; +/// let addr1 = &*array[0] as *const i8 as usize; +/// let addr2 = &*array[1] as *const i8 as usize; +/// +/// assert!(addr2 - addr1 >= 32); +/// assert_eq!(addr1 % 32, 0); +/// assert_eq!(addr2 % 32, 0); +/// ``` +/// +/// When building a concurrent queue with a head and a tail index, it is wise to place them in +/// different cache lines so that concurrent threads pushing and popping elements don't invalidate +/// each other's cache lines: +/// +/// ``` +/// use crossbeam_utils::CachePadded; +/// use std::sync::atomic::AtomicUsize; +/// +/// struct Queue { +/// head: CachePadded, +/// tail: CachePadded, +/// buffer: *mut T, +/// } +/// ``` +#[derive(Clone, Copy, Default, Hash, PartialEq, Eq)] +// Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache +// lines at a time, so we have to align to 128 bytes rather than 64. +// +// Sources: +// - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf +// - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107 +// +// aarch64/arm64ec's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size. +// +// Sources: +// - https://www.mono-project.com/news/2016/09/12/arm64-icache/ +// +// powerpc64 has 128-byte cache line size. +// +// Sources: +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9 +// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/powerpc/include/asm/cache.h#L26 +#[cfg_attr( + any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "arm64ec", + target_arch = "powerpc64", + ), + repr(align(128)) +)] +// arm, mips, mips64, sparc, and hexagon have 32-byte cache line size. +// +// Sources: +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7 +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7 +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7 +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9 +// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/sparc/include/asm/cache.h#L17 +// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/hexagon/include/asm/cache.h#L12 +#[cfg_attr( + any( + target_arch = "arm", + target_arch = "mips", + target_arch = "mips32r6", + target_arch = "mips64", + target_arch = "mips64r6", + target_arch = "sparc", + target_arch = "hexagon", + ), + repr(align(32)) +)] +// m68k has 16-byte cache line size. +// +// Sources: +// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/m68k/include/asm/cache.h#L9 +#[cfg_attr(target_arch = "m68k", repr(align(16)))] +// s390x has 256-byte cache line size. +// +// Sources: +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7 +// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/s390/include/asm/cache.h#L13 +#[cfg_attr(target_arch = "s390x", repr(align(256)))] +// x86, wasm, riscv, and sparc64 have 64-byte cache line size. +// +// Sources: +// - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9 +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7 +// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/riscv/include/asm/cache.h#L10 +// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/sparc/include/asm/cache.h#L19 +// +// All others are assumed to have 64-byte cache line size. +#[cfg_attr( + not(any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "arm64ec", + target_arch = "powerpc64", + target_arch = "arm", + target_arch = "mips", + target_arch = "mips32r6", + target_arch = "mips64", + target_arch = "mips64r6", + target_arch = "sparc", + target_arch = "hexagon", + target_arch = "m68k", + target_arch = "s390x", + )), + repr(align(64)) +)] +pub struct CachePadded { + value: T, +} + +unsafe impl Send for CachePadded {} +unsafe impl Sync for CachePadded {} + +impl CachePadded { + /// Pads and aligns a value to the length of a cache line. + /// + /// # Examples + /// + /// ``` + /// use crossbeam_utils::CachePadded; + /// + /// let padded_value = CachePadded::new(1); + /// ``` + pub const fn new(t: T) -> CachePadded { + CachePadded:: { value: t } + } +} + +impl Deref for CachePadded { + type Target = T; + + fn deref(&self) -> &T { + &self.value + } +} + +impl DerefMut for CachePadded { + fn deref_mut(&mut self) -> &mut T { + &mut self.value + } +} + +impl fmt::Debug for CachePadded { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("CachePadded") + .field("value", &self.value) + .finish() + } +} + +impl From for CachePadded { + fn from(t: T) -> Self { + CachePadded::new(t) + } +} + +impl fmt::Display for CachePadded { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + fmt::Display::fmt(&self.value, f) + } +} diff --git a/src/lib.rs b/src/lib.rs index cd6f216..64835d3 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -60,7 +60,7 @@ use core::marker::PhantomData; use core::mem::{ManuallyDrop, MaybeUninit}; use core::sync::atomic::{AtomicUsize, Ordering}; -#[allow(dead_code, clippy::undocumented_unsafe_blocks)] +#[allow(clippy::undocumented_unsafe_blocks)] mod cache_padded; use cache_padded::CachePadded; diff --git a/tests/lib.rs b/tests/lib.rs index 260b666..f4a748a 100644 --- a/tests/lib.rs +++ b/tests/lib.rs @@ -68,7 +68,7 @@ fn parallel() { #[test] fn drops() { - use rand::{thread_rng, Rng}; + use rand::Rng; use std::sync::atomic::{AtomicUsize, Ordering}; const RUNS: usize = if cfg!(miri) { 10 } else { 100 }; @@ -84,11 +84,11 @@ fn drops() { } } - let mut rng = thread_rng(); + let mut rng = rand::rng(); for _ in 0..RUNS { - let steps = rng.gen_range(0..if cfg!(miri) { 100 } else { 10_000 }); - let additional = rng.gen_range(0..50); + let steps = rng.random_range(0..if cfg!(miri) { 100 } else { 10_000 }); + let additional = rng.random_range(0..50); DROPS.store(0, Ordering::SeqCst); let (mut p, mut c) = RingBuffer::new(50);