Way hazard on WAR in dual issue processor

[StefMassin]

In the dual issue processor a way-hazard occurs for example when running the instructions

addi x2 x1 -1
addi x1 x3 0

As far as I can tell this is due to the following lines:

Ripes/src/processors/RISC-V/rv6s_dual/rv6s_dual_waycontrol.h

Lines 142 to 149 in 1a03ff2

	} else if (rawHazard()) {
	// WAR hazard; only issue 1st fetched instruction
	m_dataWayValid = way1Type == WayClass::Data;
	m_execWayValid = way1Type != WayClass::Data;
	m_dataWaySrc = WaySrc::WAY1;
	m_execWaySrc = WaySrc::WAY1;
	m_stall = true && ifid_valid.uValue();
	} else {

Ripes/src/processors/RISC-V/rv6s_dual/rv6s_dual_waycontrol.h

Lines 69 to 88 in 1a03ff2

	bool rawHazard() const {
	const unsigned wridx_1 = wr_reg_idx_way1.uValue();
	const unsigned wridx_2 = wr_reg_idx_way2.uValue();
	const unsigned idx1_1 = r1_reg_idx_way1.uValue();
	const unsigned idx2_1 = r2_reg_idx_way1.uValue();
	const unsigned idx1_2 = r1_reg_idx_way2.uValue();
	const unsigned idx2_2 = r2_reg_idx_way2.uValue();
	// way1 write => way 2 read?
	const bool hazard_1 = (wridx_1 != 0) &&
	(wridx_1 == idx1_2 || wridx_1 == idx2_2) &&
	isWriteRegInstr(opcode_way1.uValue());
	// way2 write => way 1 read?
	const bool hazard_2 = (wridx_2 != 0) &&
	(wridx_2 == idx1_1 || wridx_2 == idx2_1) &&
	isWriteRegInstr(opcode_way2.uValue());
	return hazard_1 || hazard_2;
	}

Here the rawHazard() function will look for a RAW, where way1 writes to one of the sources of way2. I get this would cause problems since the instruction in slot 1 has not written its result, yet slot 2 needs it. However at the same time it also looks for a WAR, since hazard_1 and hazard_2 are or'd in the return value.

Is this intended behaviour? Would a WAR hazard cause incorrect behaviour later in the pipeline and if so, where?