[RVC][Tracker] Support for RISC-V "C" extension

[mortbopet]

This is a tracking issue for tracking the implementation of the RISC-V compressed ISA extension in Ripes.

• [RVC] Relax instruction alignment constraint when RVC is enabled #124
• [RVC] Add support for compiling with the compressed extension #126
• [RVC] Add support for variable length instructions in the InstructionModel #127
• [RVC] Add processor support for the C extension #128
• [RVC] Fix assembling of register values in compressed instructions #129
• [RVC] Implement all "C" instructions #130
• [RVC] Fix disassembly indent on compressed instructions #132
• [RVC] Add unit tests for RV-C instructions #137
• [RVC] Update wiki with RVC-related info #144
• [RVC] Implement c.addi16sp instruction #152
• [RVC] Resetting RV-C single cycle processor is very slow #156
• [RVC] Incorrect behaviour when executing consoleInput.c on single cycle RVC #157
• Disassembler does not correctly disassemble some RVC instructions  #166

Discussion on support for the C extension: #119.

[Zikon328]

Disassembler does not correct dissasemble register, when reduce range register x8-x15
and not error for reduce reg in asm source.
( Asm and C mode )

Command c.beqz and c.bnez not valid compute offset.
( Asm mode )

format command c.lw and c.sw
c.lw rd, rs, offset

not really
c.lw rd, offset(rs)