diff --git a/build/a.out1 b/build/a.out1 index 8331dea..31b0040 100644 --- a/build/a.out1 +++ b/build/a.out1 @@ -1,51 +1,16 @@ -**** module/scope: sar_controller - Flip-Flops : 0 - Logic Gates : 0 -**** module/scope: sar_controller.auto_samp_inst - Flip-Flops : 5 - Logic Gates : 26 +**** module/scope: SAR_Logic_12bit + Flip-Flops : 40 + Logic Gates : 946 ADDER[4]: 1 units - MAGNITUDE[4]: 1 units - MUX[2]: 4 slices - LOG[13]: 1 unaccounted - LOG[14]: 1 unaccounted -**** module/scope: sar_controller.cdac_ctrl_inst - Flip-Flops : 24 - Logic Gates : 73 - MUX[2]: 24 slices - LOG[13]: 1 unaccounted - LOG[14]: 1 unaccounted -**** module/scope: sar_controller.clk_div_inst - Flip-Flops : 4 - Logic Gates : 14 - ADDER[2]: 1 units - EQUALITY[2]: 2 units - LOG[13]: 1 unaccounted - LOG[14]: 1 unaccounted -**** module/scope: sar_controller.comp_ext_inst - Flip-Flops : 1 - Logic Gates : 11 - MUX[2]: 1 slices - LOG[13]: 1 unaccounted - LOG[14]: 1 unaccounted -**** module/scope: sar_controller.cyclic_flag_inst - Flip-Flops : 12 - Logic Gates : 25 - MUX[2]: 12 slices - LOG[13]: 1 unaccounted - LOG[14]: 1 unaccounted -**** module/scope: sar_controller.data_latch_inst - Flip-Flops : 12 - Logic Gates : 0 + EQUALITY[4]: 13 units + MUX[2]: 380 slices LOG[13]: 1 unaccounted LOG[14]: 1 unaccounted **** TOTALS - Flip-Flops : 58 - Logic Gates : 149 - ADDER[2]: 1 units + Flip-Flops : 40 + Logic Gates : 946 ADDER[4]: 1 units - EQUALITY[2]: 2 units - MAGNITUDE[4]: 1 units - MUX[2]: 41 slices - LOG[13]: 6 unaccounted - LOG[14]: 6 unaccounted + EQUALITY[4]: 13 units + MUX[2]: 380 slices + LOG[13]: 1 unaccounted + LOG[14]: 1 unaccounted diff --git a/gds/SAR_Logic_12bit.gds b/gds/SAR_Logic_12bit.gds new file mode 100644 index 0000000..e5c4672 Binary files /dev/null and b/gds/SAR_Logic_12bit.gds differ diff --git a/transistor_mode.py b/transistor_mode.py deleted file mode 100644 index ac7fee4..0000000 --- a/transistor_mode.py +++ /dev/null @@ -1,77 +0,0 @@ -# in ngspice run a simulation and after run this -# $ set altshow -# $ show >> - -import re - -def parse(filename): - transistors = [] - - with open(filename) as file: - while True: - line = file.readline() - if not line: - break - - # Find nfet and pfet - device_str = r"model.*=\s*(.*):.*([n|p]fet).*" - # Find vgs, vds, vth, id - param_str = r"(vgs|vds|vth|id|vdsat)\s*=\s*(.*)" - - m = re.match(device_str, line) - if m is None: - continue - - tras = {} # new device - tras["name"] = m.group(1) - tras["type"] = m.group(2) - - while True: - line = file.readline() - if not line: - break - - m = re.match(param_str, line) - if m is not None: - tras[m.group(1)] = float(m.group(2)) - - if re.match(device_str, line) is not None: - break - - # Go back one line - file.seek(file.tell() - len(line)) - transistors.append(tras) - - return transistors - -def transistor_mode(tras): - if tras["type"] == "nfet": - if tras["vgs"] <= tras["vth"]: - return "Cutoff" - if tras["vds"] >= tras["vdsat"]: - return "Saturation" - else: - return "Linear" - elif tras["type"] == "pfet": - if abs(tras["vgs"]) <= abs(tras["vth"]): - return "Cutoff" - if abs(tras["vds"]) >= abs(tras["vdsat"]): - return "Saturation" - else: - return "Linear" - -def mode(tras): - print(f"{tras['type']:>5} | {tras['name']:>10} | " - f"{transistor_mode(tras):>12} | |vgs-vth| = {abs(tras['vgs'] - tras['vth']):>23} | " - f"vgs = {tras['vgs']:>17} | " - f"vth = {tras['vth']:>17} | " - f"vdsat = {tras['vdsat']:>17} | " - f"vds = {abs(tras['vds']):>17} | " - f"id = {abs(tras['id']):>17}") - -# Example usage: -# filename = 'your_file.txt' -# transistors = parse(filename) -# for tras in transistors: -# mode(tras) - diff --git a/verilog/rtl/SAR_Logic_12bit.v b/verilog/rtl/SAR_Logic_12bit.v new file mode 100644 index 0000000..57ff192 --- /dev/null +++ b/verilog/rtl/SAR_Logic_12bit.v @@ -0,0 +1,112 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 20:20:54 10/14/2024 +// Design Name: +// Module Name: SAR_Logic_12bit +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module SAR_Logic_12bit( + input clk_src, + input reset, + input digital_in, + output [11:0] da_converter, + output [11:0] result + ); + +reg [11:0]da_converter_register; +reg [11:0]result_register; +reg [11:0]interim_register; +reg [3:0]state; + +assign da_converter = da_converter_register; +assign result = result_register; + +always @(posedge clk_src) begin + state <= state + 2'b01; + if (reset == 1'b1) begin + da_converter_register <= 12'b000000000000; + interim_register <= 12'b000000000000; + result_register <= 12'b000000000000; + state <= 4'b0000; + end + else if(state == 4'b0000) begin + da_converter_register <= 12'b100000000000; + interim_register[11] <= digital_in; + end + else if(state == 4'b0001) begin + da_converter_register[11] <= interim_register[11]; + da_converter_register[10] <= 1'b1; + interim_register[10] <= digital_in; + end + else if(state == 4'b0010) begin + da_converter_register[10] <= interim_register[10]; + da_converter_register[9] <= 1'b1; + interim_register[9] <= digital_in; + end + else if(state == 4'b0011) begin + da_converter_register[9] <= interim_register[9]; + da_converter_register[8] <= 1'b1; + interim_register[8] <= digital_in; + end + else if(state == 4'b0100) begin + da_converter_register[8] <= interim_register[8]; + da_converter_register[7] <= 1'b1; + interim_register[7] <= digital_in; + end + else if(state == 4'b0101) begin + da_converter_register[7] <= interim_register[7]; + da_converter_register[6] <= 1'b1; + interim_register[6] <= digital_in; + end + else if(state == 4'b0110) begin + da_converter_register[6] <= interim_register[6]; + da_converter_register[5] <= 1'b1; + interim_register[5] <= digital_in; + end + else if(state == 4'b0111) begin + da_converter_register[5] <= interim_register[5]; + da_converter_register[4] <= 1'b1; + interim_register[4] <= digital_in; + end + else if(state == 4'b1000) begin + da_converter_register[4] <= interim_register[4]; + da_converter_register[3] <= 1'b1; + interim_register[3] <= digital_in; + end + else if(state == 4'b1001) begin + da_converter_register[3] <= interim_register[3]; + da_converter_register[2] <= 1'b1; + interim_register[2] <= digital_in; + end + else if(state == 4'b1010) begin + da_converter_register[2] <= interim_register[2]; + da_converter_register[1] <= 1'b1; + interim_register[1] <= digital_in; + end + else if(state == 4'b1011) begin + da_converter_register[1] <= interim_register[1]; + da_converter_register[0] <= 1'b1; + interim_register[0] <= digital_in; + end + else if(state == 4'b1100) begin + result_register <= interim_register; + state <= 4'b0000; + end + else + state <= 4'b0000; + end + +endmodule diff --git a/verilog/rtl/clk b/verilog/rtl/clk deleted file mode 100755 index 5c43622..0000000 --- a/verilog/rtl/clk +++ /dev/null @@ -1,91 +0,0 @@ -#! /usr/bin/vvp -:ivl_version "11.0 (stable)"; -:ivl_delay_selection "TYPICAL"; -:vpi_time_precision - 12; -:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; -:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; -:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; -:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; -:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; -S_0x5e7255b8fd50 .scope module, "cyclic_flag_tb" "cyclic_flag_tb" 2 3; - .timescale -9 -12; -v0x5e7255ba27f0_0 .var "CLK", 0 0; -v0x5e7255ba28c0_0 .var "RST", 0 0; -v0x5e7255ba2990_0 .net "shift_reg", 11 0, v0x5e7255ba26b0_0; 1 drivers -S_0x5e7255b8fee0 .scope module, "uut" "cyclic_flag" 2 10, 2 45 0, S_0x5e7255b8fd50; - .timescale -9 -12; - .port_info 0 /INPUT 1 "CLK"; - .port_info 1 /INPUT 1 "RST"; - .port_info 2 /OUTPUT 12 "shift_reg"; -v0x5e7255b567b0_0 .net "CLK", 0 0, v0x5e7255ba27f0_0; 1 drivers -v0x5e7255b56ba0_0 .net "RST", 0 0, v0x5e7255ba28c0_0; 1 drivers -v0x5e7255ba26b0_0 .var "shift_reg", 0 11; -E_0x5e7255b903a0 .event posedge, v0x5e7255b567b0_0; - .scope S_0x5e7255b8fee0; -T_0 ; - %wait E_0x5e7255b903a0; - %load/vec4 v0x5e7255b56ba0_0; - %flag_set/vec4 8; - %jmp/0xz T_0.0, 8; - %pushi/vec4 0, 0, 12; - %assign/vec4 v0x5e7255ba26b0_0, 0; - %jmp T_0.1; -T_0.0 ; - %load/vec4 v0x5e7255ba26b0_0; - %parti/s 1, 11, 5; - %cmpi/e 0, 0, 1; - %jmp/0xz T_0.2, 4; - %load/vec4 v0x5e7255ba26b0_0; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %shiftl 4; - %pushi/vec4 1, 0, 12; - %or; - %assign/vec4 v0x5e7255ba26b0_0, 0; - %jmp T_0.3; -T_0.2 ; - %load/vec4 v0x5e7255ba26b0_0; - %assign/vec4 v0x5e7255ba26b0_0, 0; -T_0.3 ; -T_0.1 ; - %jmp T_0; - .thread T_0; - .scope S_0x5e7255b8fd50; -T_1 ; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x5e7255ba27f0_0, 0, 1; -T_1.0 ; - %delay 10000, 0; - %load/vec4 v0x5e7255ba27f0_0; - %inv; - %store/vec4 v0x5e7255ba27f0_0, 0, 1; - %jmp T_1.0; - %end; - .thread T_1; - .scope S_0x5e7255b8fd50; -T_2 ; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x5e7255ba28c0_0, 0, 1; - %delay 25000, 0; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x5e7255ba28c0_0, 0, 1; - %delay 500000, 0; - %vpi_call 2 29 "$finish" {0 0 0}; - %end; - .thread T_2; - .scope S_0x5e7255b8fd50; -T_3 ; - %vpi_call 2 34 "$monitor", "Time=%0t ns | RST=%b | shift_reg=%b", $time, v0x5e7255ba28c0_0, v0x5e7255ba2990_0 {0 0 0}; - %end; - .thread T_3; - .scope S_0x5e7255b8fd50; -T_4 ; - %vpi_call 2 39 "$dumpfile", "cyclic_flag_tb.vcd" {0 0 0}; - %vpi_call 2 40 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x5e7255b8fd50 {0 0 0}; - %end; - .thread T_4; -# The file index is used to find the file name in the following table. -:file_names 3; - "N/A"; - ""; - "test_bench.v"; diff --git a/verilog/rtl/clkdiv_tb.vcd b/verilog/rtl/clkdiv_tb.vcd deleted file mode 100644 index 6ff1b5c..0000000 --- a/verilog/rtl/clkdiv_tb.vcd +++ /dev/null @@ -1,303 +0,0 @@ -$date - Thu Oct 10 03:26:21 2024 -$end -$version - Icarus Verilog -$end -$timescale - 1ps -$end -$scope module clkdiv_tb $end -$var wire 1 ! CLK_S $end -$var wire 1 " CLK_NS $end -$var reg 1 # CLK $end -$scope module uut $end -$var wire 1 # CLK $end -$var reg 1 " CLK_NS $end -$var reg 1 ! CLK_S $end -$var reg 2 $ counter [1:0] $end -$var reg 4 % init_counter [3:0] $end -$var reg 1 & internal_reset $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -1& -b0 % -bx $ -0# -x" -x! -$end -#5000 -b1 % -0! -0" -b0 $ -1# -#10000 -0# -#15000 -b10 % -1# -#20000 -0# -#25000 -b11 % -1# -#30000 -0# -#35000 -b100 % -1# -#40000 -0# -#45000 -b101 % -1# -#50000 -0# -#55000 -b110 % -1# -#60000 -0# -#65000 -b111 % -1# -#70000 -0# -#75000 -b1000 % -1# -#80000 -0# -#85000 -b1001 % -1# -#90000 -0# -#95000 -b1010 % -1# -#100000 -0# -#105000 -b1011 % -1# -#110000 -0# -#115000 -b1100 % -1# -#120000 -0# -#125000 -b1101 % -1# -#130000 -0# -#135000 -b1110 % -1# -#140000 -0# -#145000 -b1111 % -1# -#150000 -0# -#155000 -0& -b0 % -1# -#160000 -0# -#165000 -b1 $ -1# -#170000 -0# -#175000 -1" -b10 $ -1# -#180000 -0# -#185000 -b11 $ -1# -#190000 -0# -#195000 -1! -b0 $ -1# -#200000 -0# -#205000 -b1 $ -1# -#210000 -0# -#215000 -0" -b10 $ -1# -#220000 -0# -#225000 -b11 $ -1# -#230000 -0# -#235000 -0! -b0 $ -1# -#240000 -0# -#245000 -b1 $ -1# -#250000 -0# -#255000 -1" -b10 $ -1# -#260000 -0# -#265000 -b11 $ -1# -#270000 -0# -#275000 -1! -b0 $ -1# -#280000 -0# -#285000 -b1 $ -1# -#290000 -0# -#295000 -0" -b10 $ -1# -#300000 -0# -#305000 -b11 $ -1# -#310000 -0# -#315000 -0! -b0 $ -1# -#320000 -0# -#325000 -b1 $ -1# -#330000 -0# -#335000 -1" -b10 $ -1# -#340000 -0# -#345000 -b11 $ -1# -#350000 -0# -#355000 -1! -b0 $ -1# -#360000 -0# -#365000 -b1 $ -1# -#370000 -0# -#375000 -0" -b10 $ -1# -#380000 -0# -#385000 -b11 $ -1# -#390000 -0# -#395000 -0! -b0 $ -1# -#400000 -0# -#405000 -b1 $ -1# -#410000 -0# -#415000 -1" -b10 $ -1# -#420000 -0# -#425000 -b11 $ -1# -#430000 -0# -#435000 -1! -b0 $ -1# -#440000 -0# -#445000 -b1 $ -1# -#450000 -0# -#455000 -0" -b10 $ -1# -#460000 -0# -#465000 -b11 $ -1# -#470000 -0# -#475000 -0! -b0 $ -1# -#480000 -0# -#485000 -b1 $ -1# -#490000 -0# -#495000 -1" -b10 $ -1# -#500000 -0# diff --git a/verilog/rtl/cyclic_flag_tb.vcd b/verilog/rtl/cyclic_flag_tb.vcd deleted file mode 100644 index 22b8a7e..0000000 --- a/verilog/rtl/cyclic_flag_tb.vcd +++ /dev/null @@ -1,160 +0,0 @@ -$date - Thu Oct 10 04:15:53 2024 -$end -$version - Icarus Verilog -$end -$timescale - 1ps -$end -$scope module cyclic_flag_tb $end -$var wire 12 ! shift_reg [11:0] $end -$var reg 1 " CLK $end -$var reg 1 # RST $end -$scope module uut $end -$var wire 1 " CLK $end -$var wire 1 # RST $end -$var reg 12 $ shift_reg [0:11] $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -bx $ -1# -0" -bx ! -$end -#10000 -b0 ! -b0 $ -1" -#20000 -0" -#25000 -0# -#30000 -b1 ! -b1 $ -1" -#40000 -0" -#50000 -b11 ! -b11 $ -1" -#60000 -0" -#70000 -b111 ! -b111 $ -1" -#80000 -0" -#90000 -b1111 ! -b1111 $ -1" -#100000 -0" -#110000 -b11111 ! -b11111 $ -1" -#120000 -0" -#130000 -b111111 ! -b111111 $ -1" -#140000 -0" -#150000 -b1111111 ! -b1111111 $ -1" -#160000 -0" -#170000 -b11111111 ! -b11111111 $ -1" -#180000 -0" -#190000 -b111111111 ! -b111111111 $ -1" -#200000 -0" -#210000 -b1111111111 ! -b1111111111 $ -1" -#220000 -0" -#230000 -b11111111111 ! -b11111111111 $ -1" -#240000 -0" -#250000 -b111111111111 ! -b111111111111 $ -1" -#260000 -0" -#270000 -1" -#280000 -0" -#290000 -1" -#300000 -0" -#310000 -1" -#320000 -0" -#330000 -1" -#340000 -0" -#350000 -1" -#360000 -0" -#370000 -1" -#380000 -0" -#390000 -1" -#400000 -0" -#410000 -1" -#420000 -0" -#430000 -1" -#440000 -0" -#450000 -1" -#460000 -0" -#470000 -1" -#480000 -0" -#490000 -1" -#500000 -0" -#510000 -1" -#520000 -0" -#525000 diff --git a/verilog/rtl/sar_adc_12bit_diff_tb.vcd b/verilog/rtl/sar_adc_12bit_diff_tb.vcd deleted file mode 100644 index 576f980..0000000 --- a/verilog/rtl/sar_adc_12bit_diff_tb.vcd +++ /dev/null @@ -1,4275 +0,0 @@ -$date - Thu Oct 10 03:41:35 2024 -$end -$version - Icarus Verilog -$end -$timescale - 1ps -$end -$scope module sar_adc_12bit_diff_tb $end -$var wire 1 ! samp_en $end -$var wire 12 " dout [11:0] $end -$var wire 12 # dac_code_p [11:0] $end -$var wire 12 $ dac_code_n [11:0] $end -$var reg 1 % clk $end -$var reg 1 & comp_out $end -$var real 1 ' Vdac_n $end -$var real 1 ( Vdac_p $end -$var real 1 ) Vin_n $end -$var real 1 * Vin_p $end -$var real 1 + Vref $end -$scope module uut $end -$var wire 1 % clk $end -$var wire 1 & comp_out $end -$var reg 4 , bit_cnt [3:0] $end -$var reg 1 - comp_delay $end -$var reg 12 . dac_code_n [11:0] $end -$var reg 12 / dac_code_p [11:0] $end -$var reg 12 0 dout [11:0] $end -$var reg 1 1 phase $end -$var reg 1 ! samp_en $end -$var reg 12 2 sar_reg [11:0] $end -$var reg 1 3 state $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -x3 -bx 2 -x1 -bx 0 -bx / -bx . -x- -bx , -r3.3 + -r1.65 * -r0 ) -r0 ( -r0 ' -x& -0% -bx $ -bx # -bx " -x! -$end -#5000 -03 -1& -1% -#10000 -0% -#15000 -13 -01 -b0 $ -b0 . -b0 # -b0 / -b0 2 -b0 , -1! -1% -#20000 -0% -#25000 -r3.3 ' -11 -1- -b111111111111 $ -b111111111111 . -b100000000000 2 -0! -1% -#30000 -0% -#35000 -01 -b1 , -1% -#40000 -0% -#45000 -r1.649597069597069 ' -r1.65040293040293 ( -11 -b11111111111 $ -b11111111111 . -b100000000000 # -b100000000000 / -b110000000000 2 -1% -#50000 -0% -#55000 -01 -b10 , -1% -#60000 -0% -#65000 -r0.8243956043956043 ' -r2.475604395604396 ( -11 -b1111111111 $ -b1111111111 . -b110000000000 # -b110000000000 / -b111000000000 2 -1% -#70000 -0% -#75000 -0& -01 -b11 , -1% -#80000 -0% -#85000 -r0.4117948717948718 ' -r2.888205128205128 ( -11 -0- -b111111111 $ -b111111111 . -b111000000000 # -b111000000000 / -b111100000000 2 -1% -#90000 -0% -#95000 -01 -b100 , -b111000000000 2 -1% -#100000 -0% -#105000 -11 -b111010000000 2 -1% -#110000 -0% -#115000 -01 -b101 , -b111000000000 2 -1% -#120000 -0% -#125000 -11 -b111001000000 2 -1% -#130000 -0% -#135000 -01 -b110 , -b111000000000 2 -1% -#140000 -0% -#145000 -11 -b111000100000 2 -1% -#150000 -0% -#155000 -01 -b111 , -b111000000000 2 -1% -#160000 -0% -#165000 -11 -b111000010000 2 -1% -#170000 -0% -#175000 -01 -b1000 , -b111000000000 2 -1% -#180000 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-#4385000 -01 -b110 , -1% -#4390000 -0% -#4395000 -r1.701172161172161 ' -r1.598827838827839 ( -11 -b100000111111 $ -b100000111111 . -b11111000000 # -b11111000000 / -b11111100000 2 -1% -#4400000 -0% -#4405000 -01 -b111 , -1% -#4410000 -0% -#4415000 -r1.675384615384615 ' -r1.624615384615385 ( -11 -b100000011111 $ -b100000011111 . -b11111100000 # -b11111100000 / -b11111110000 2 -1% -#4420000 -0% -#4425000 -01 -b1000 , -1% -#4430000 -0% -#4435000 -r1.662490842490842 ' -r1.637509157509157 ( -11 -b100000001111 $ -b100000001111 . -b11111110000 # -b11111110000 / -b11111111000 2 -1% -#4440000 -0% -#4445000 -01 -b1001 , -1% -#4450000 -0% -#4455000 -r1.656043956043956 ' -r1.643956043956044 ( -11 -b100000000111 $ -b100000000111 . -b11111111000 # -b11111111000 / -b11111111100 2 -1% -#4460000 -0% -#4465000 -01 -b1010 , -1% -#4470000 -0% -#4475000 -r1.652820512820513 ' -r1.647179487179487 ( -11 -b100000000011 $ -b100000000011 . -b11111111100 # -b11111111100 / -b11111111110 2 -1% -#4480000 -0% -#4485000 -01 -b1011 , -1% -#4490000 -0% -#4495000 -r1.651208791208791 ' -r1.648791208791209 ( -11 -b100000000001 $ -b100000000001 . -b11111111110 # -b11111111110 / -b11111111111 2 -1% -#4500000 -0% -#4505000 -01 -03 -b11111111111 " -b11111111111 0 -b1100 , -1% -#4510000 -0% -#4515000 -r0 ' -r0 ( -13 -b0 $ -b0 . -b0 # -b0 / -b0 2 -b0 , -1! -1% -#4520000 -0% -#4525000 -r3.3 ' -11 -b111111111111 $ -b111111111111 . -b100000000000 2 -0! -1% -#4530000 -0% -#4535000 -01 -b1 , -1% -#4540000 -0% -#4545000 -r1.649597069597069 ' -r1.65040293040293 ( -11 -b11111111111 $ -b11111111111 . -b100000000000 # -b100000000000 / -b110000000000 2 -1% -#4550000 -0% -#4555000 -01 -b10 , -1% -#4560000 -0% -#4565000 -r0.8243956043956043 ' -r2.475604395604396 ( -11 -b1111111111 $ -b1111111111 . -b110000000000 # -b110000000000 / -b111000000000 2 -1% -#4570000 -0% -#4575000 -0& -01 -b11 , -1% -#4580000 -0% -#4585000 -r0.4117948717948718 ' -r2.888205128205128 ( -11 -0- -b111111111 $ -b111111111 . -b111000000000 # -b111000000000 / -b111100000000 2 -1% -#4590000 -0% -#4595000 -01 -b100 , -b111000000000 2 -1% -#4600000 -0% -#4605000 -11 -b111010000000 2 -1% -#4610000 -0% -#4615000 -01 -b101 , -b111000000000 2 -1% -#4620000 -0% -#4625000 -11 -b111001000000 2 -1% -#4630000 -0% -#4635000 -01 -b110 , -b111000000000 2 -1% -#4640000 -0% -#4645000 -11 -b111000100000 2 -1% -#4650000 -0% -#4655000 -01 -b111 , -b111000000000 2 -1% -#4660000 -0% -#4665000 -11 -b111000010000 2 -1% -#4670000 -0% -#4675000 -01 -b1000 , -b111000000000 2 -1% -#4680000 -0% -#4685000 -11 -b111000001000 2 -1% -#4690000 -0% -#4695000 -01 -b1001 , -b111000000000 2 -1% -#4700000 -0% -#4705000 -11 -b111000000100 2 -1% -#4710000 -0% -#4715000 -01 -b1010 , -b111000000000 2 -1% -#4720000 -0% -#4725000 -11 -b111000000010 2 -1% -#4730000 -0% -#4735000 -01 -b1011 , -b111000000000 2 -1% -#4740000 -0% -#4745000 -11 -b111000000001 2 -1% -#4750000 -0% -#4755000 -01 -03 -b111000000001 " -b111000000001 0 -b1100 , -b111000000000 2 -1% -#4760000 -0% -#4765000 -r0 ' -r0 ( -13 -b0 $ -b0 . -b0 # -b0 / -b0 2 -b0 , -1! -1% -#4770000 -0% -#4775000 -r3.3 ' -11 -b111111111111 $ -b111111111111 . -b100000000000 2 -0! -1% -#4780000 -0% -#4785000 -01 -b1 , -b0 2 -1& -1% -#4790000 -0% -#4795000 -11 -1- -b10000000000 2 -1% -#4800000 -0% -#4805000 -01 -b10 , -1% -#4810000 -0% -#4815000 -r2.474798534798535 ' -r0.8252014652014652 ( -11 -b101111111111 $ -b101111111111 . -b10000000000 # -b10000000000 / -b11000000000 2 -1% -#4820000 -0% -#4825000 -01 -b11 , -1% -#4830000 -0% -#4835000 -r2.062197802197802 ' -r1.237802197802198 ( -11 -b100111111111 $ -b100111111111 . -b11000000000 # -b11000000000 / -b11100000000 2 -1% -#4840000 -0% -#4845000 -01 -b100 , -1% -#4850000 -0% -#4855000 -r1.855897435897436 ' -r1.444102564102564 ( -11 -b100011111111 $ -b100011111111 . -b11100000000 # -b11100000000 / -b11110000000 2 -1% -#4860000 -0% -#4865000 -01 -b101 , -1% -#4870000 -0% -#4875000 -r1.752747252747253 ' -r1.547252747252747 ( -11 -b100001111111 $ -b100001111111 . -b11110000000 # -b11110000000 / -b11111000000 2 -1% -#4880000 -0% -#4885000 -01 -b110 , -1% -#4890000 -0% -#4895000 -r1.701172161172161 ' -r1.598827838827839 ( -11 -b100000111111 $ -b100000111111 . -b11111000000 # -b11111000000 / -b11111100000 2 -1% -#4900000 -0% -#4905000 -01 -b111 , -1% -#4910000 -0% -#4915000 -r1.675384615384615 ' -r1.624615384615385 ( -11 -b100000011111 $ -b100000011111 . -b11111100000 # -b11111100000 / -b11111110000 2 -1% -#4920000 -0% -#4925000 -01 -b1000 , -1% -#4930000 -0% -#4935000 -r1.662490842490842 ' -r1.637509157509157 ( -11 -b100000001111 $ -b100000001111 . -b11111110000 # -b11111110000 / -b11111111000 2 -1% -#4940000 -0% -#4945000 -01 -b1001 , -1% -#4950000 -0% -#4955000 -r1.656043956043956 ' -r1.643956043956044 ( -11 -b100000000111 $ -b100000000111 . -b11111111000 # -b11111111000 / -b11111111100 2 -1% -#4960000 -0% -#4965000 -01 -b1010 , -1% -#4970000 -0% -#4975000 -r1.652820512820513 ' -r1.647179487179487 ( -11 -b100000000011 $ -b100000000011 . -b11111111100 # -b11111111100 / -b11111111110 2 -1% -#4980000 -0% -#4985000 -01 -b1011 , -1% -#4990000 -0% -#4995000 -r1.651208791208791 ' -r1.648791208791209 ( -11 -b100000000001 $ -b100000000001 . -b11111111110 # -b11111111110 / -b11111111111 2 -1% -#5000000 -0% diff --git a/verilog/rtl/testbench_sar.v b/verilog/rtl/testbench_sar.v new file mode 100644 index 0000000..80646b3 --- /dev/null +++ b/verilog/rtl/testbench_sar.v @@ -0,0 +1,129 @@ +`timescale 1ns / 1ps + +module sar_controller_tb; + + // Sinyal input + reg CLK; + reg ENABLE; + reg COMP_P; + reg COMP_N; + + // Sinyal output + wire CLKS; + wire CLK_S; + wire CLK_NS; + wire EOC; + wire [0:11] DOUT; + wire [0:11] CDAC_P; + wire [0:11] CDAC_N; + + // Instansiasi modul sar_controller + sar_controller uut ( + .ENABLE (ENABLE), + .CLK (CLK), + .COMP_P (COMP_P), + .COMP_N (COMP_N), + .CLKS (CLKS), + .CLK_S (CLK_S), + .CLK_NS (CLK_NS), + .EOC (EOC), + .DOUT (DOUT), + .CDAC_P (CDAC_P), + .CDAC_N (CDAC_N) + ); + + // Parameter untuk simulasi + real Vref = 3.3; // Tegangan referensi + real Vin_p_real; // Tegangan input positif (real) + real Vin_n_real; // Tegangan input negatif (real) + real Vdac_p_real; // Output DAC positif (real) + real Vdac_n_real; // Output DAC negatif (real) + + // Representasi tetap untuk plotting + integer Vin_p_fixed; // Vin_p dalam mV + integer Vin_n_fixed; // Vin_n dalam mV + integer Vdac_p_fixed; // Vdac_p dalam mV + integer Vdac_n_fixed; // Vdac_n dalam mV + + // Skala untuk konversi real ke integer + integer scale_factor = 1000; // Skala volt ke milivolt + + // Clock generation: 50 MHz clock dengan periode 20ns + initial begin + CLK = 0; + forever #10 CLK = ~CLK; // Toggle clock setiap 10ns + end + + // Inisialisasi input + initial begin + ENABLE = 1; + COMP_P = 0; + COMP_N = 0; + + Vin_p_real = 1.65; // Tegangan input awal (setengah Vref) + Vin_n_real = 0.0; + + #5000; // Simulasi selama 5000ns + $finish; + end + + // Variabel untuk menyimpan nilai CDAC_P dan CDAC_N sebagai integer + integer CDAC_P_value; + integer CDAC_N_value; + + // Konversi CDAC_P dan CDAC_N dari vektor bit ke integer + always @(*) begin + CDAC_P_value = CDAC_P[0]*1 + CDAC_P[1]*2 + CDAC_P[2]*4 + CDAC_P[3]*8 + + CDAC_P[4]*16 + CDAC_P[5]*32 + CDAC_P[6]*64 + CDAC_P[7]*128 + + CDAC_P[8]*256 + CDAC_P[9]*512 + CDAC_P[10]*1024 + CDAC_P[11]*2048; + + CDAC_N_value = CDAC_N[0]*1 + CDAC_N[1]*2 + CDAC_N[2]*4 + CDAC_N[3]*8 + + CDAC_N[4]*16 + CDAC_N[5]*32 + CDAC_N[6]*64 + CDAC_N[7]*128 + + CDAC_N[8]*256 + CDAC_N[9]*512 + CDAC_N[10]*1024 + CDAC_N[11]*2048; + end + + // Model DAC: Hitung Vdac_p_real dan Vdac_n_real berdasarkan CDAC_P_value dan CDAC_N_value + always @(*) begin + Vdac_p_real = (CDAC_P_value / 4095.0) * Vref; + Vdac_n_real = (CDAC_N_value / 4095.0) * Vref; + end + + // Konversi Vin dan Vdac ke bentuk integer untuk plotting + always @(*) begin + Vin_p_fixed = Vin_p_real * scale_factor; // Dalam mV + Vin_n_fixed = Vin_n_real * scale_factor; + Vdac_p_fixed = Vdac_p_real * scale_factor; + Vdac_n_fixed = Vdac_n_real * scale_factor; + end + + // Model Komparator: Menghasilkan COMP_P dan COMP_N berdasarkan Vin dan Vdac + always @(posedge CLK_NS) begin + if (CLKS) begin + // Selama sampling, komparator tidak aktif + COMP_P <= 0; + COMP_N <= 0; + end else begin + // Selama konversi, bandingkan Vin dengan Vdac + if ((Vin_p_real - Vin_n_real) > (Vdac_p_real - Vdac_n_real)) begin + COMP_P <= 1; + COMP_N <= 0; + end else begin + COMP_P <= 0; + COMP_N <= 1; + end + end + end + + // Monitor output + initial begin + $monitor("Time=%0t ns | DOUT=%b | Vin_p=%0f V | Vin_n=%0f V | Vdac_p=%0f V | Vdac_n=%0f V | COMP_P=%b | COMP_N=%b", + $time, DOUT, Vin_p_real, Vin_n_real, Vdac_p_real, Vdac_n_real, COMP_P, COMP_N); + end + + // Dump waveforms untuk GTKWave + initial begin + $dumpfile("sar_controller_tb.vcd"); // Nama file dump + $dumpvars(0, sar_controller_tb); // Dump semua variabel dalam modul ini + end + +endmodule diff --git a/xschem/10b_cap_array.sch b/xschem/10b_cap_array.sch new file mode 100644 index 0000000..264a135 --- /dev/null +++ b/xschem/10b_cap_array.sch @@ -0,0 +1,46 @@ +v {xschem version=3.4.5 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +C {devices/lab_wire.sym} 960 -70 2 0 {name=p1 sig_type=std_logic lab=vcm} +C {devices/lab_wire.sym} 960 -170 2 0 {name=p3 sig_type=std_logic lab=swp[0]} +C {devices/lab_wire.sym} 960 -280 2 0 {name=p5 sig_type=std_logic lab=swp[1]} +C {devices/lab_wire.sym} 960 -390 2 0 {name=p7 sig_type=std_logic lab=swp[2]} +C {devices/lab_wire.sym} 960 -500 2 0 {name=p9 sig_type=std_logic lab=swp[3]} +C {devices/lab_wire.sym} 960 -610 2 0 {name=p11 sig_type=std_logic lab=swp[4]} +C {devices/lab_wire.sym} 960 -720 2 0 {name=p13 sig_type=std_logic lab=swp[5]} +C {devices/lab_wire.sym} 960 -830 2 0 {name=p15 sig_type=std_logic lab=swp[6]} +C {devices/lab_wire.sym} 960 -940 2 0 {name=p17 sig_type=std_logic lab=swp[7]} +C {devices/lab_wire.sym} 960 -1050 2 0 {name=p19 sig_type=std_logic lab=swp[8]} +C {devices/lab_wire.sym} 960 -1160 2 0 {name=p21 sig_type=std_logic lab=swp[9]} +C {devices/ipin.sym} 210 -670 0 0 {name=p53 lab=swp[0:11]} +C {devices/ipin.sym} 210 -690 0 0 {name=p54 lab=vcm} +C {devices/iopin.sym} 190 -650 0 0 {name=p56 lab=vc + +} +C {devices/param.sym} 260 -770 0 0 {name=s1 value="dim_unit=2u"} +C {devices/lab_wire.sym} 960 -1220 0 1 {name=p30 sig_type=std_logic lab=vc} +C {sky130_fd_pr/cap_mim_m3_1.sym} 960 -1190 0 0 {name=C3 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=512 spiceprefix=X} +C {devices/lab_wire.sym} 960 -1110 0 1 {name=p31 sig_type=std_logic lab=vc} +C {sky130_fd_pr/cap_mim_m3_1.sym} 960 -1080 0 0 {name=C4 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=256 spiceprefix=X} +C {devices/lab_wire.sym} 960 -1000 0 1 {name=p32 sig_type=std_logic lab=vc} +C {sky130_fd_pr/cap_mim_m3_1.sym} 960 -970 0 0 {name=C5 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=128 spiceprefix=X} +C {devices/lab_wire.sym} 960 -890 0 1 {name=p33 sig_type=std_logic lab=vc} +C {sky130_fd_pr/cap_mim_m3_1.sym} 960 -860 0 0 {name=C6 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=64 spiceprefix=X} +C {devices/lab_wire.sym} 960 -780 0 1 {name=p34 sig_type=std_logic lab=vc} +C {sky130_fd_pr/cap_mim_m3_1.sym} 960 -750 0 0 {name=C7 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=32 spiceprefix=X} +C {devices/lab_wire.sym} 960 -670 0 1 {name=p35 sig_type=std_logic lab=vc} +C {sky130_fd_pr/cap_mim_m3_1.sym} 960 -640 0 0 {name=C8 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=16 spiceprefix=X} +C {devices/lab_wire.sym} 960 -560 0 1 {name=p36 sig_type=std_logic lab=vc} +C {sky130_fd_pr/cap_mim_m3_1.sym} 960 -530 0 0 {name=C9 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=8 spiceprefix=X} +C {devices/lab_wire.sym} 960 -450 0 1 {name=p37 sig_type=std_logic lab=vc} +C {sky130_fd_pr/cap_mim_m3_1.sym} 960 -420 0 0 {name=C10 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=4 spiceprefix=X} +C {devices/lab_wire.sym} 960 -340 0 1 {name=p38 sig_type=std_logic lab=vc} +C {sky130_fd_pr/cap_mim_m3_1.sym} 960 -310 0 0 {name=C11 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=2 spiceprefix=X} +C {devices/lab_wire.sym} 960 -230 0 1 {name=p39 sig_type=std_logic lab=vc} +C {sky130_fd_pr/cap_mim_m3_1.sym} 960 -200 0 0 {name=C12 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=1 spiceprefix=X} +C {sky130_fd_pr/cap_mim_m3_1.sym} 960 -100 0 0 {name=C13 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=1 spiceprefix=X} +C {devices/lab_wire.sym} 960 -130 0 1 {name=p71 sig_type=std_logic lab=vc} diff --git a/xschem/10b_cap_array.sym b/xschem/10b_cap_array.sym new file mode 100644 index 0000000..3f9b3dc --- /dev/null +++ b/xschem/10b_cap_array.sym @@ -0,0 +1,20 @@ +v {xschem version=3.4.5 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +T {@symname} -76.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -32 0 0 0.2 0.2 {} +L 4 -130 -20 130 -20 {} +L 4 -130 20 130 20 {} +L 4 -130 -20 -130 20 {} +L 4 130 -20 130 20 {} +B 5 -152.5 -12.5 -147.5 -7.5 {name=vcm dir=in} +L 4 -150 -10 -130 -10 {} +T {vcm} -125 -14 0 0 0.2 0.2 {} +B 5 -152.5 7.5 -147.5 12.5 {name=swp[0:11] dir=in} +L 4 -150 10 -130 10 {} +T {swp[0:11]} -125 6 0 0 0.2 0.2 {} +B 5 147.5 -12.5 152.5 -7.5 {name=vc dir=inout} +L 7 130 -10 150 -10 {} +T {vc} 125 -14 0 1 0.2 0.2 {} diff --git a/xschem/4b_adc.sch b/xschem/4b_adc.sch deleted file mode 100644 index a655101..0000000 --- a/xschem/4b_adc.sch +++ /dev/null @@ -1,57 +0,0 @@ -v {xschem version=3.4.5 file_version=1.2 -} -G {} -K {} -V {} -S {} -E {} -C {4b_cdac_and_sw.sym} 430 -230 0 0 {name=x1} -C {th_sw.sym} 430 -410 0 0 {name=x2} -C {epc.sym} 890 -420 0 0 {name=x3} -C {sar.sym} 890 -210 0 0 {name=x4} -C {devices/lab_wire.sym} 280 -460 0 0 {name=p1 sig_type=std_logic lab=VDDA} -C {devices/lab_wire.sym} 280 -280 0 0 {name=p2 sig_type=std_logic lab=VDDA} -C {devices/lab_wire.sym} 740 -460 0 0 {name=p3 sig_type=std_logic lab=VDDA} -C {devices/lab_wire.sym} 740 -380 0 0 {name=p4 sig_type=std_logic lab=VSSA} -C {devices/lab_wire.sym} 280 -180 0 0 {name=p5 sig_type=std_logic lab=VSSA} -C {devices/lab_wire.sym} 280 -360 0 0 {name=p6 sig_type=std_logic lab=VSSA} -C {devices/lab_wire.sym} 740 -280 0 0 {name=p7 sig_type=std_logic lab=VDDD} -C {devices/lab_wire.sym} 740 -200 0 0 {name=p8 sig_type=std_logic lab=VSSD} -C {devices/lab_wire.sym} 280 -440 0 0 {name=p9 sig_type=std_logic lab=CLKS} -C {devices/lab_wire.sym} 280 -420 0 0 {name=p10 sig_type=std_logic lab=CLKSB} -C {devices/lab_wire.sym} 1040 -280 0 1 {name=p11 sig_type=std_logic lab=CLKS} -C {devices/lab_wire.sym} 1040 -260 0 1 {name=p12 sig_type=std_logic lab=CLKSB} -C {devices/lab_wire.sym} 1040 -460 0 1 {name=p13 sig_type=std_logic lab=COMP_P} -C {devices/lab_wire.sym} 1040 -440 0 1 {name=p14 sig_type=std_logic lab=COMP_N} -C {devices/lab_wire.sym} 740 -240 0 0 {name=p15 sig_type=std_logic lab=COMP_P} -C {devices/lab_wire.sym} 740 -220 0 0 {name=p16 sig_type=std_logic lab=COMP_N} -C {devices/lab_wire.sym} 740 -260 0 0 {name=p17 sig_type=std_logic lab=CLK} -C {devices/lab_wire.sym} 580 -460 0 1 {name=p18 sig_type=std_logic lab=VCP} -C {devices/lab_wire.sym} 580 -440 0 1 {name=p19 sig_type=std_logic lab=VCN} -C {devices/lab_wire.sym} 580 -280 0 1 {name=p20 sig_type=std_logic lab=VCP} -C {devices/lab_wire.sym} 580 -260 0 1 {name=p21 sig_type=std_logic lab=VCN} -C {devices/lab_wire.sym} 740 -440 0 0 {name=p22 sig_type=std_logic lab=VCP} -C {devices/lab_wire.sym} 740 -420 0 0 {name=p23 sig_type=std_logic lab=VCN} -C {devices/lab_wire.sym} 1040 -140 0 1 {name=p24 sig_type=std_logic lab=CLK_NS} -C {devices/lab_wire.sym} 740 -400 0 0 {name=p25 sig_type=std_logic lab=CLK_NS} -C {devices/lab_wire.sym} 280 -260 0 0 {name=p26 sig_type=std_logic lab=VCM} -C {devices/lab_wire.sym} 280 -400 0 0 {name=p27 sig_type=std_logic lab=VIP} -C {devices/lab_wire.sym} 280 -380 0 0 {name=p28 sig_type=std_logic lab=VIN} -C {devices/lab_wire.sym} 280 -240 0 0 {name=p29 sig_type=std_logic lab=CF[0:3]} -C {devices/lab_wire.sym} 280 -220 0 0 {name=p30 sig_type=std_logic lab=SWP[0:3]} -C {devices/lab_wire.sym} 280 -200 0 0 {name=p31 sig_type=std_logic lab=SWN[0:3]} -C {devices/lab_wire.sym} 1040 -240 0 1 {name=p32 sig_type=std_logic lab=CF[0:3]} -C {devices/lab_wire.sym} 1040 -220 0 1 {name=p33 sig_type=std_logic lab=SWP[0:3]} -C {devices/lab_wire.sym} 1040 -200 0 1 {name=p34 sig_type=std_logic lab=SWN[0:3]} -C {devices/lab_wire.sym} 1040 -160 0 1 {name=p35 sig_type=std_logic lab=CKO} -C {devices/lab_wire.sym} 1040 -180 0 1 {name=p36 sig_type=std_logic lab=DOUT[0:3]} -C {devices/ipin.sym} 80 -480 0 0 {name=p37 sig_type=std_logic lab=VDDA} -C {devices/ipin.sym} 80 -460 0 0 {name=p38 sig_type=std_logic lab=VDDD} -C {devices/ipin.sym} 80 -440 0 0 {name=p39 sig_type=std_logic lab=VCM} -C {devices/ipin.sym} 80 -420 0 0 {name=p40 sig_type=std_logic lab=CLK} -C {devices/ipin.sym} 80 -400 0 0 {name=p41 sig_type=std_logic lab=VIP} -C {devices/ipin.sym} 80 -380 0 0 {name=p42 sig_type=std_logic lab=VIN} -C {devices/ipin.sym} 80 -360 0 0 {name=p43 sig_type=std_logic lab=VSSA} -C {devices/ipin.sym} 80 -340 0 0 {name=p44 sig_type=std_logic lab=VSSD} -C {devices/opin.sym} 80 -300 0 0 {name=p45 sig_type=std_logic lab=DOUT[0:3]} -C {devices/opin.sym} 80 -280 0 0 {name=p46 sig_type=std_logic lab=CKO} diff --git a/xschem/4b_adc.sym b/xschem/4b_adc.sym deleted file mode 100644 index 4272154..0000000 --- a/xschem/4b_adc.sym +++ /dev/null @@ -1,41 +0,0 @@ -v {xschem version=3.4.5 file_version=1.2} -K {type=subcircuit -format="@name @pinlist @symname" -template="name=x1" -} -T {@symname} -45 -6 0 0 0.3 0.3 {} -T {@name} 135 -92 0 0 0.2 0.2 {} -L 4 -130 -80 130 -80 {} -L 4 -130 80 130 80 {} -L 4 -130 -80 -130 80 {} -L 4 130 -80 130 80 {} -B 5 -152.5 -72.5 -147.5 -67.5 {name=VDDA sig_type=std_logic dir=in} -L 4 -150 -70 -130 -70 {} -T {VDDA} -125 -74 0 0 0.2 0.2 {} -B 5 -152.5 -52.5 -147.5 -47.5 {name=VDDD sig_type=std_logic dir=in} -L 4 -150 -50 -130 -50 {} -T {VDDD} -125 -54 0 0 0.2 0.2 {} -B 5 -152.5 -32.5 -147.5 -27.5 {name=VCM sig_type=std_logic dir=in} -L 4 -150 -30 -130 -30 {} -T {VCM} -125 -34 0 0 0.2 0.2 {} -B 5 -152.5 -12.5 -147.5 -7.5 {name=CLK sig_type=std_logic dir=in} -L 4 -150 -10 -130 -10 {} -T {CLK} -125 -14 0 0 0.2 0.2 {} -B 5 -152.5 7.5 -147.5 12.5 {name=VIP sig_type=std_logic dir=in} -L 4 -150 10 -130 10 {} -T {VIP} -125 6 0 0 0.2 0.2 {} -B 5 -152.5 27.5 -147.5 32.5 {name=VIN sig_type=std_logic dir=in} -L 4 -150 30 -130 30 {} -T {VIN} -125 26 0 0 0.2 0.2 {} -B 5 -152.5 47.5 -147.5 52.5 {name=VSSA sig_type=std_logic dir=in} -L 4 -150 50 -130 50 {} -T {VSSA} -125 46 0 0 0.2 0.2 {} -B 5 -152.5 67.5 -147.5 72.5 {name=VSSD sig_type=std_logic dir=in} -L 4 -150 70 -130 70 {} -T {VSSD} -125 66 0 0 0.2 0.2 {} -B 5 147.5 -72.5 152.5 -67.5 {name=DOUT[0:3] sig_type=std_logic dir=out} -L 4 130 -70 150 -70 {} -T {DOUT[0:3]} 125 -74 0 1 0.2 0.2 {} -B 5 147.5 -52.5 152.5 -47.5 {name=CKO sig_type=std_logic dir=out} -L 4 130 -50 150 -50 {} -T {CKO} 125 -54 0 1 0.2 0.2 {} diff --git a/xschem/4b_cdac.sch b/xschem/4b_cdac.sch deleted file mode 100644 index e10fa25..0000000 --- a/xschem/4b_cdac.sch +++ /dev/null @@ -1,42 +0,0 @@ -v {xschem version=3.4.5 file_version=1.2 -} -G {} -K {} -V {} -S {} -E {} -N 480 -400 1240 -400 { -lab=vcn} -N 480 -520 1240 -520 { -lab=vcp} -N 400 -520 480 -520 { -lab=vcp} -N 400 -400 480 -400 { -lab=vcn} -C {devices/ipin.sym} 220 -480 0 0 {name=p21 lab=vcm} -C {devices/ipin.sym} 220 -440 0 0 {name=p22 lab=swp[0:3]} -C {devices/ipin.sym} 220 -400 0 0 {name=p23 lab=swn[0:3]} -C {devices/opin.sym} 200 -360 0 0 {name=p24 lab=vcp} -C {devices/opin.sym} 200 -320 0 0 {name=p25 lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 480 -370 0 0 {name=C1 model=cap_mim_m3_1 W=5 L=5 MF=8 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_1.sym} 660 -370 0 0 {name=C2 model=cap_mim_m3_1 W=5 L=5 MF=4 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_1.sym} 850 -370 0 0 {name=C3 model=cap_mim_m3_1 W=5 L=5 MF=2 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1040 -370 0 0 {name=C4 model=cap_mim_m3_1 W=5 L=5 MF=1 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1240 -370 0 0 {name=C5 model=cap_mim_m3_1 W=5 L=5 MF=1 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_1.sym} 480 -550 2 0 {name=C6 model=cap_mim_m3_1 W=5 L=5 MF=8 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_1.sym} 660 -550 2 0 {name=C7 model=cap_mim_m3_1 W=5 L=5 MF=4 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_1.sym} 850 -550 2 0 {name=C8 model=cap_mim_m3_1 W=5 L=5 MF=2 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1040 -550 2 0 {name=C9 model=cap_mim_m3_1 W=5 L=5 MF=1 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1240 -550 2 0 {name=C10 model=cap_mim_m3_1 W=5 L=5 MF=1 spiceprefix=X} -C {devices/lab_wire.sym} 480 -580 0 0 {name=p1 sig_type=std_logic lab=swp[3]} -C {devices/lab_wire.sym} 660 -580 0 0 {name=p2 sig_type=std_logic lab=swp[2]} -C {devices/lab_wire.sym} 850 -580 0 0 {name=p3 sig_type=std_logic lab=swp[1]} -C {devices/lab_wire.sym} 1040 -580 0 0 {name=p4 sig_type=std_logic lab=swp[0]} -C {devices/lab_wire.sym} 1240 -580 0 0 {name=p5 sig_type=std_logic lab=vcm} -C {devices/lab_wire.sym} 480 -340 2 1 {name=p6 sig_type=std_logic lab=swn[3]} -C {devices/lab_wire.sym} 660 -340 2 1 {name=p7 sig_type=std_logic lab=swn[2]} -C {devices/lab_wire.sym} 850 -340 2 1 {name=p8 sig_type=std_logic lab=swn[1]} -C {devices/lab_wire.sym} 1040 -340 2 1 {name=p9 sig_type=std_logic lab=swn[0]} -C {devices/lab_wire.sym} 1240 -340 2 1 {name=p10 sig_type=std_logic lab=vcm} -C {devices/lab_wire.sym} 400 -520 2 1 {name=p11 sig_type=std_logic lab=vcp} -C {devices/lab_wire.sym} 400 -400 0 0 {name=p12 sig_type=std_logic lab=vcn} diff --git a/xschem/4b_cdac.sym b/xschem/4b_cdac.sym deleted file mode 100644 index 32c0570..0000000 --- a/xschem/4b_cdac.sym +++ /dev/null @@ -1,26 +0,0 @@ -v {xschem version=3.4.5 file_version=1.2} -K {type=subcircuit -format="@name @pinlist @symname" -template="name=x1" -} -T {@symname} -49.5 -6 0 0 0.3 0.3 {} -T {@name} 135 -42 0 0 0.2 0.2 {} -L 4 -130 -30 130 -30 {} -L 4 -130 30 130 30 {} -L 4 -130 -30 -130 30 {} -L 4 130 -30 130 30 {} -B 5 -152.5 -22.5 -147.5 -17.5 {name=vcm dir=in} -L 4 -150 -20 -130 -20 {} -T {vcm} -125 -24 0 0 0.2 0.2 {} -B 5 -152.5 -2.5 -147.5 2.5 {name=swp[0:3] dir=in} -L 4 -150 0 -130 0 {} -T {swp[0:3]} -125 -4 0 0 0.2 0.2 {} -B 5 -152.5 17.5 -147.5 22.5 {name=swn[0:3] dir=in} -L 4 -150 20 -130 20 {} -T {swn[0:3]} -125 16 0 0 0.2 0.2 {} -B 5 147.5 -22.5 152.5 -17.5 {name=vcp dir=out} -L 4 130 -20 150 -20 {} -T {vcp} 125 -24 0 1 0.2 0.2 {} -B 5 147.5 -2.5 152.5 2.5 {name=vcn dir=out} -L 4 130 0 150 0 {} -T {vcn} 125 -4 0 1 0.2 0.2 {} diff --git a/xschem/4b_cdac_and_sw.sch b/xschem/4b_cdac_and_sw.sch deleted file mode 100644 index 1eece0d..0000000 --- a/xschem/4b_cdac_and_sw.sch +++ /dev/null @@ -1,35 +0,0 @@ -v {xschem version=3.4.5 file_version=1.2 -} -G {} -K {} -V {} -S {} -E {} -C {4b_cdac.sym} 990 -310 0 0 {name=x1} -C {cdac_sw.sym} 410 -430 0 0 {name=x2[0:3]} -C {cdac_sw.sym} 410 -310 0 0 {name=x3[0:3]} -C {devices/lab_wire.sym} 260 -470 0 0 {name=p2 sig_type=std_logic lab=vdda} -C {devices/lab_wire.sym} 260 -350 0 0 {name=p3 sig_type=std_logic lab=vdda} -C {devices/lab_wire.sym} 260 -270 0 0 {name=p4 sig_type=std_logic lab=vssa} -C {devices/lab_wire.sym} 260 -390 0 0 {name=p5 sig_type=std_logic lab=vssa} -C {devices/lab_wire.sym} 260 -410 0 0 {name=p6 sig_type=std_logic lab=vcm} -C {devices/lab_wire.sym} 260 -290 0 0 {name=p7 sig_type=std_logic lab=vcm} -C {devices/lab_wire.sym} 840 -330 0 0 {name=p8 sig_type=std_logic lab=vcm} -C {devices/lab_wire.sym} 260 -450 0 0 {name=p9 sig_type=std_logic lab=cf[0:3]} -C {devices/lab_wire.sym} 260 -330 0 0 {name=p10 sig_type=std_logic lab=cf[0:3]} -C {devices/lab_wire.sym} 260 -430 0 0 {name=p11 sig_type=std_logic lab=swp[0:3]} -C {devices/lab_wire.sym} 260 -310 0 0 {name=p12 sig_type=std_logic lab=swn[0:3]} -C {devices/lab_wire.sym} 840 -310 0 0 {name=p13 sig_type=std_logic lab=dac_outp[0:3]} -C {devices/lab_wire.sym} 840 -290 0 0 {name=p14 sig_type=std_logic lab=dac_outn[0:3]} -C {devices/lab_wire.sym} 560 -470 0 1 {name=p15 sig_type=std_logic lab=dac_outp[0:3]} -C {devices/lab_wire.sym} 560 -350 0 1 {name=p16 sig_type=std_logic lab=dac_outn[0:3]} -C {devices/lab_wire.sym} 1140 -330 0 1 {name=p17 sig_type=std_logic lab=vcp} -C {devices/lab_wire.sym} 1140 -310 0 1 {name=p18 sig_type=std_logic lab=vcn} -C {devices/ipin.sym} 80 -460 0 0 {name=p1 sig_type=std_logic lab=vdda} -C {devices/ipin.sym} 80 -420 0 0 {name=p19 sig_type=std_logic lab=cf[0:3]} -C {devices/ipin.sym} 80 -440 0 0 {name=p20 sig_type=std_logic lab=vcm} -C {devices/ipin.sym} 80 -400 0 0 {name=p21 sig_type=std_logic lab=swp[0:3]} -C {devices/ipin.sym} 80 -380 0 0 {name=p22 sig_type=std_logic lab=swn[0:3]} -C {devices/ipin.sym} 80 -360 0 0 {name=p23 sig_type=std_logic lab=vssa} -C {devices/iopin.sym} 80 -320 0 1 {name=p24 sig_type=std_logic lab=vcp} -C {devices/iopin.sym} 80 -300 0 1 {name=p25 sig_type=std_logic lab=vcn} diff --git a/xschem/4b_cdac_and_sw.sym b/xschem/4b_cdac_and_sw.sym deleted file mode 100644 index b199121..0000000 --- a/xschem/4b_cdac_and_sw.sym +++ /dev/null @@ -1,35 +0,0 @@ -v {xschem version=3.4.5 file_version=1.2} -K {type=subcircuit -format="@name @pinlist @symname" -template="name=x1" -} -T {@symname} -81 -6 0 0 0.3 0.3 {} -T {@name} 135 -72 0 0 0.2 0.2 {} -L 4 -130 -60 130 -60 {} -L 4 -130 60 130 60 {} -L 4 -130 -60 -130 60 {} -L 4 130 -60 130 60 {} -B 5 -152.5 -52.5 -147.5 -47.5 {name=vdda sig_type=std_logic dir=in} -L 4 -150 -50 -130 -50 {} -T {vdda} -125 -54 0 0 0.2 0.2 {} -B 5 -152.5 -32.5 -147.5 -27.5 {name=vcm sig_type=std_logic dir=in} -L 4 -150 -30 -130 -30 {} -T {vcm} -125 -34 0 0 0.2 0.2 {} -B 5 -152.5 -12.5 -147.5 -7.5 {name=cf[0:3] sig_type=std_logic dir=in} -L 4 -150 -10 -130 -10 {} -T {cf[0:3]} -125 -14 0 0 0.2 0.2 {} -B 5 -152.5 7.5 -147.5 12.5 {name=swp[0:3] sig_type=std_logic dir=in} -L 4 -150 10 -130 10 {} -T {swp[0:3]} -125 6 0 0 0.2 0.2 {} -B 5 -152.5 27.5 -147.5 32.5 {name=swn[0:3] sig_type=std_logic dir=in} -L 4 -150 30 -130 30 {} -T {swn[0:3]} -125 26 0 0 0.2 0.2 {} -B 5 -152.5 47.5 -147.5 52.5 {name=vssa sig_type=std_logic dir=in} -L 4 -150 50 -130 50 {} -T {vssa} -125 46 0 0 0.2 0.2 {} -B 5 147.5 -52.5 152.5 -47.5 {name=vcp sig_type=std_logic dir=inout} -L 7 130 -50 150 -50 {} -T {vcp} 125 -54 0 1 0.2 0.2 {} -B 5 147.5 -32.5 152.5 -27.5 {name=vcn sig_type=std_logic dir=inout} -L 7 130 -30 150 -30 {} -T {vcn} 125 -34 0 1 0.2 0.2 {} diff --git a/xschem/all.spice b/xschem/all.spice deleted file mode 100644 index 06d7501..0000000 --- a/xschem/all.spice +++ /dev/null @@ -1,57 +0,0 @@ -** sch_path: /home/mthudaa/Documents/UNIC-CASS-TSAR-ADC-ITS/xschem/epc.sch -.subckt all VDDA OUTP VP OUTN VN START VSSA -*.ipin VDDA -*.ipin VP -*.ipin VN -*.ipin VSSA -*.opin OUTP -*.ipin START -*.opin OUTN -x9 OUTP START VSSA VSSA VDDA VDDA net2 sky130_fd_sc_hd__nand2_1 -x10 OUTN START VSSA VSSA VDDA VDDA net1 sky130_fd_sc_hd__nand2_1 -x1 VDDA net1 VP VN VSSA OUTP epc_delay_line -x2 VDDA net2 VN VP VSSA OUTN epc_delay_line -.ends - -* expanding symbol: epc_delay_line.sym # of pins=6 -** sym_path: /home/mthudaa/Documents/UNIC-CASS-TSAR-ADC-ITS/xschem/epc_delay_line.sym -** sch_path: /home/mthudaa/Documents/UNIC-CASS-TSAR-ADC-ITS/xschem/epc_delay_line.sch -.subckt epc_delay_line vdd in vp vn vss out -*.ipin vdd -*.ipin in -*.ipin vp -*.ipin vn -*.ipin vss -*.opin out -x1 in net1 vp vdd vss epc_delay -x2 net1 net2 vn vdd vss epc_delay -x3 net2 net3 vp vdd vss epc_delay -x4 net3 net4 vn vdd vss epc_delay -x5 net4 net5 vp vdd vss epc_delay -x6 net5 net6 vn vdd vss epc_delay -x7 net6 net7 vp vdd vss epc_delay -x8 net7 out vn vdd vss epc_delay -.ends - - -* expanding symbol: epc_delay.sym # of pins=5 -** sym_path: /home/mthudaa/Documents/UNIC-CASS-TSAR-ADC-ITS/xschem/epc_delay.sym -** sch_path: /home/mthudaa/Documents/UNIC-CASS-TSAR-ADC-ITS/xschem/epc_delay.sch -.subckt epc_delay IN OUT VIN VDD VSS -*.ipin VDD -*.ipin VIN -*.ipin IN -*.ipin VSS -*.opin OUT -.param W_N=0.5 L_N=0.5 W_P=1.0 L_P=0.5 -XM1 net2 VIN VDD VDD sky130_fd_pr__pfet_01v8_lvt L=L_P W=W_P nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM2 OUT IN net2 VDD sky130_fd_pr__pfet_01v8_lvt L=L_P W=W_P nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM3 OUT IN net1 VSS sky130_fd_pr__nfet_01v8_lvt L=L_N W=W_N nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM4 net1 VIN VSS VSS sky130_fd_pr__nfet_01v8_lvt L=L_N W=W_N nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -.ends - -.end diff --git a/xschem/bsw.spice b/xschem/bsw.spice deleted file mode 100644 index 237c904..0000000 --- a/xschem/bsw.spice +++ /dev/null @@ -1,31 +0,0 @@ -** sch_path: /home/mthudaa/Documents/UNIC-CASS-TSAR-ADC-ITS/xschem/bsw.sch -**.subckt bsw vdd clk clkb vi vss vo -*.ipin vdd -*.ipin clk -*.ipin clkb -*.ipin vi -*.ipin vss -*.opin vo -XM1 net1 clk vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' -+ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM2 net2 net3 vdd net2 sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM3 net3 net1 net2 net2 sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM4 net1 clk net5 vss sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' -+ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM5 net5 clkb vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' -+ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM6 net1 net3 net5 vss sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' -+ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM7 net5 net3 vi vss sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' -+ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM8 net3 vdd net4 vss sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' -+ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM9 net4 clkb vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' -+ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XC1 net2 net5 sky130_fd_pr__cap_mim_m3_1 W=2 L=8 MF=1 m=1 -XM10 vo net3 vi vss sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' -+ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -**.ends -.end diff --git a/xschem/cap_array.sch b/xschem/cap_array.sch deleted file mode 100644 index 45a74f3..0000000 --- a/xschem/cap_array.sch +++ /dev/null @@ -1,91 +0,0 @@ -v {xschem version=3.4.5 file_version=1.2 -} -G {} -K {} -V {} -S {} -E {} -C {devices/lab_wire.sym} 950 -70 2 0 {name=p1 sig_type=std_logic lab=vcm} -C {devices/lab_wire.sym} 950 -170 2 0 {name=p3 sig_type=std_logic lab=swp[0]} -C {devices/lab_wire.sym} 1490 -180 2 0 {name=p4 sig_type=std_logic lab=swn[0]} -C {devices/lab_wire.sym} 950 -280 2 0 {name=p5 sig_type=std_logic lab=swp[1]} -C {devices/lab_wire.sym} 1490 -290 2 0 {name=p6 sig_type=std_logic lab=swn[1]} -C {devices/lab_wire.sym} 950 -390 2 0 {name=p7 sig_type=std_logic lab=swp[2]} -C {devices/lab_wire.sym} 1490 -400 2 0 {name=p8 sig_type=std_logic lab=swn[2]} -C {devices/lab_wire.sym} 950 -500 2 0 {name=p9 sig_type=std_logic lab=swp[3]} -C {devices/lab_wire.sym} 1490 -510 2 0 {name=p10 sig_type=std_logic lab=swn[3]} -C {devices/lab_wire.sym} 950 -610 2 0 {name=p11 sig_type=std_logic lab=swp[4]} -C {devices/lab_wire.sym} 1490 -620 2 0 {name=p12 sig_type=std_logic lab=swn[4]} -C {devices/lab_wire.sym} 950 -720 2 0 {name=p13 sig_type=std_logic lab=swp[5]} -C {devices/lab_wire.sym} 1490 -730 2 0 {name=p14 sig_type=std_logic lab=swn[5]} -C {devices/lab_wire.sym} 950 -830 2 0 {name=p15 sig_type=std_logic lab=swp[6]} -C {devices/lab_wire.sym} 1490 -840 2 0 {name=p16 sig_type=std_logic lab=swn[6]} -C {devices/lab_wire.sym} 950 -940 2 0 {name=p17 sig_type=std_logic lab=swp[7]} -C {devices/lab_wire.sym} 1490 -950 2 0 {name=p18 sig_type=std_logic lab=swn[7]} -C {devices/lab_wire.sym} 950 -1050 2 0 {name=p19 sig_type=std_logic lab=swp[8]} -C {devices/lab_wire.sym} 1490 -1060 2 0 {name=p20 sig_type=std_logic lab=swn[8]} -C {devices/lab_wire.sym} 950 -1160 2 0 {name=p21 sig_type=std_logic lab=swp[9]} -C {devices/lab_wire.sym} 1490 -1170 2 0 {name=p22 sig_type=std_logic lab=swn[9]} -C {devices/lab_wire.sym} 950 -1270 2 0 {name=p23 sig_type=std_logic lab=swp[10]} -C {devices/lab_wire.sym} 1490 -1280 2 0 {name=p24 sig_type=std_logic lab=swn[10]} -C {devices/lab_wire.sym} 950 -1380 2 0 {name=p25 sig_type=std_logic lab=swp[11]} -C {devices/lab_wire.sym} 1490 -1390 2 0 {name=p26 sig_type=std_logic lab=swn[11]} -C {devices/lab_wire.sym} 950 -1440 0 1 {name=p27 sig_type=std_logic lab=vcp} -C {devices/ipin.sym} 220 -860 0 0 {name=p53 lab=swp[0:11]} -C {devices/ipin.sym} 220 -880 0 0 {name=p54 lab=vcm} -C {devices/ipin.sym} 220 -840 0 0 {name=p55 lab=swn[0:11]} -C {devices/iopin.sym} 200 -820 0 0 {name=p56 lab=vcp} -C {devices/iopin.sym} 200 -800 0 0 {name=p57 lab=vcn} -C {devices/param.sym} 270 -960 0 0 {name=s1 value="dim_unit=2u"} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -1410 0 0 {name=C1 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=2048 spiceprefix=X} -C {devices/lab_wire.sym} 950 -1330 0 1 {name=p29 sig_type=std_logic lab=vcp} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -1300 0 0 {name=C2 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=1024 spiceprefix=X} -C {devices/lab_wire.sym} 950 -1220 0 1 {name=p30 sig_type=std_logic lab=vcp} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -1190 0 0 {name=C3 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=512 spiceprefix=X} -C {devices/lab_wire.sym} 950 -1110 0 1 {name=p31 sig_type=std_logic lab=vcp} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -1080 0 0 {name=C4 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=256 spiceprefix=X} -C {devices/lab_wire.sym} 950 -1000 0 1 {name=p32 sig_type=std_logic lab=vcp} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -970 0 0 {name=C5 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=128 spiceprefix=X} -C {devices/lab_wire.sym} 950 -890 0 1 {name=p33 sig_type=std_logic lab=vcp} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -860 0 0 {name=C6 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=64 spiceprefix=X} -C {devices/lab_wire.sym} 950 -780 0 1 {name=p34 sig_type=std_logic lab=vcp} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -750 0 0 {name=C7 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=32 spiceprefix=X} -C {devices/lab_wire.sym} 950 -670 0 1 {name=p35 sig_type=std_logic lab=vcp} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -640 0 0 {name=C8 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=16 spiceprefix=X} -C {devices/lab_wire.sym} 950 -560 0 1 {name=p36 sig_type=std_logic lab=vcp} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -530 0 0 {name=C9 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=8 spiceprefix=X} -C {devices/lab_wire.sym} 950 -450 0 1 {name=p37 sig_type=std_logic lab=vcp} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -420 0 0 {name=C10 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=4 spiceprefix=X} -C {devices/lab_wire.sym} 950 -340 0 1 {name=p38 sig_type=std_logic lab=vcp} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -310 0 0 {name=C11 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=2 spiceprefix=X} -C {devices/lab_wire.sym} 950 -230 0 1 {name=p39 sig_type=std_logic lab=vcp} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -200 0 0 {name=C12 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=1 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_1.sym} 950 -100 0 0 {name=C13 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=1 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -80 2 0 {name=p40 sig_type=std_logic lab=vcm} -C {devices/lab_wire.sym} 1490 -1450 0 1 {name=p58 sig_type=std_logic lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -1420 0 0 {name=C14 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=2048 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -1340 0 1 {name=p59 sig_type=std_logic lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -1310 0 0 {name=C15 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=1024 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -1230 0 1 {name=p60 sig_type=std_logic lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -1200 0 0 {name=C16 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=512 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -1120 0 1 {name=p61 sig_type=std_logic lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -1090 0 0 {name=C17 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=256 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -1010 0 1 {name=p62 sig_type=std_logic lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -980 0 0 {name=C18 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=128 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -900 0 1 {name=p63 sig_type=std_logic lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -870 0 0 {name=C19 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=64 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -790 0 1 {name=p64 sig_type=std_logic lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -760 0 0 {name=C20 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=32 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -680 0 1 {name=p65 sig_type=std_logic lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -650 0 0 {name=C21 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=16 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -570 0 1 {name=p66 sig_type=std_logic lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -540 0 0 {name=C22 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=8 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -460 0 1 {name=p67 sig_type=std_logic lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -430 0 0 {name=C23 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=4 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -350 0 1 {name=p68 sig_type=std_logic lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -320 0 0 {name=C24 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=2 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -240 0 1 {name=p69 sig_type=std_logic lab=vcn} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -210 0 0 {name=C25 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=1 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_1.sym} 1490 -110 0 0 {name=C26 model=cap_mim_m3_1 W=dim_unit L=dim_unit MF=1 spiceprefix=X} -C {devices/lab_wire.sym} 1490 -140 0 1 {name=p70 sig_type=std_logic lab=vcn} -C {devices/lab_wire.sym} 950 -130 0 1 {name=p71 sig_type=std_logic lab=vcp} diff --git a/xschem/cap_array.sym b/xschem/cap_array.sym deleted file mode 100644 index 54fb950..0000000 --- a/xschem/cap_array.sym +++ /dev/null @@ -1,26 +0,0 @@ -v {xschem version=3.4.5 file_version=1.2} -K {type=subcircuit -format="@name @pinlist @symname" -template="name=x1" -} -T {@symname} -58.5 -6 0 0 0.3 0.3 {} -T {@name} 135 -42 0 0 0.2 0.2 {} -L 4 -130 -30 130 -30 {} -L 4 -130 30 130 30 {} -L 4 -130 -30 -130 30 {} -L 4 130 -30 130 30 {} -B 5 -152.5 -22.5 -147.5 -17.5 {name=vcm dir=in} -L 4 -150 -20 -130 -20 {} -T {vcm} -125 -24 0 0 0.2 0.2 {} -B 5 -152.5 -2.5 -147.5 2.5 {name=swp[0:11] dir=in} -L 4 -150 0 -130 0 {} -T {swp[0:11]} -125 -4 0 0 0.2 0.2 {} -B 5 -152.5 17.5 -147.5 22.5 {name=swn[0:11] dir=in} -L 4 -150 20 -130 20 {} -T {swn[0:11]} -125 16 0 0 0.2 0.2 {} -B 5 147.5 -22.5 152.5 -17.5 {name=vcp dir=inout} -L 7 130 -20 150 -20 {} -T {vcp} 125 -24 0 1 0.2 0.2 {} -B 5 147.5 -2.5 152.5 2.5 {name=vcn dir=inout} -L 7 130 0 150 0 {} -T {vcn} 125 -4 0 1 0.2 0.2 {} diff --git a/xschem/cap_cell.sch b/xschem/cap_cell.sch deleted file mode 100644 index b00d009..0000000 --- a/xschem/cap_cell.sch +++ /dev/null @@ -1,18 +0,0 @@ -v {xschem version=3.4.5 file_version=1.2 -} -G {} -K {} -V {} -S {} -E {} -C {sky130_fd_pr/cap_mim_m3_2.sym} 640 -310 0 0 {name=C1 model=cap_mim_m3_2 W=dim L=dim MF=num spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_2.sym} 640 -200 0 0 {name=C2 model=cap_mim_m3_2 W=dim L=dim MF=num spiceprefix=X} -C {devices/lab_wire.sym} 640 -340 0 0 {name=p1 sig_type=std_logic lab=vcp} -C {devices/lab_wire.sym} 640 -230 0 0 {name=p2 sig_type=std_logic lab=vcn} -C {devices/lab_wire.sym} 640 -170 2 1 {name=p9 sig_type=std_logic lab=cdac_swn} -C {devices/lab_wire.sym} 640 -280 2 1 {name=p10 sig_type=std_logic lab=cdac_swp} -C {devices/iopin.sym} 200 -240 0 0 {name=p3 lab=vcp} -C {devices/iopin.sym} 200 -220 0 0 {name=p4 lab=vcn} -C {devices/ipin.sym} 200 -260 0 0 {name=p5 lab=cdac_swn} -C {devices/ipin.sym} 200 -280 0 0 {name=p6 lab=cdac_swp} -C {devices/param.sym} 300 -370 0 0 {name=s1 value="dim=1u num=1"} diff --git a/xschem/cap_cell.sym b/xschem/cap_cell.sym deleted file mode 100644 index 6741929..0000000 --- a/xschem/cap_cell.sym +++ /dev/null @@ -1,28 +0,0 @@ -v {xschem version=3.4.5 file_version=1.2 -} -G {} -K {type=subcircuit -format="@name @pinlist @symname" -template="name=x1 dim=1u num=1" -} -V {} -S {} -E {} -L 4 -130 -20 130 -20 {} -L 4 -130 20 130 20 {} -L 4 -130 -20 -130 20 {} -L 4 130 -20 130 20 {} -L 4 -150 -10 -130 -10 {} -L 4 -150 10 -130 10 {} -L 7 130 -10 150 -10 {} -L 7 130 10 150 10 {} -B 5 -152.5 -12.5 -147.5 -7.5 {name=cdac_swp dir=in} -B 5 -152.5 7.5 -147.5 12.5 {name=cdac_swn dir=in} -B 5 147.5 -12.5 152.5 -7.5 {name=vcp dir=inout} -B 5 147.5 7.5 152.5 12.5 {name=vcn dir=inout} -T {@symname} -54 -6 0 0 0.3 0.3 {} -T {@name} 135 -32 0 0 0.2 0.2 {} -T {cdac_swp} -125 -14 0 0 0.2 0.2 {} -T {cdac_swn} -125 6 0 0 0.2 0.2 {} -T {vcp} 125 -14 0 1 0.2 0.2 {} -T {vcn} 125 6 0 1 0.2 0.2 {} diff --git a/xschem/cdac_12b.sch b/xschem/cdac_12b.sch index abde2ae..476db53 100644 --- a/xschem/cdac_12b.sch +++ b/xschem/cdac_12b.sch @@ -5,31 +5,33 @@ K {} V {} S {} E {} -C {cap_array.sym} 570 -330 0 0 {name=x1} +C {10b_cap_array.sym} 570 -340 0 0 {name=x1} C {cdac_sw.sym} 570 -450 0 0 {name=x2[0:11]} C {cdac_sw.sym} 570 -570 0 0 {name=x3[0:11]} -C {lab_wire.sym} 420 -610 0 0 {name=p1 sig_type=std_logic lab=vdref} -C {lab_wire.sym} 420 -490 0 0 {name=p2 sig_type=std_logic lab=vdref} -C {lab_wire.sym} 420 -530 0 0 {name=p3 sig_type=std_logic lab=vsref} -C {lab_wire.sym} 420 -410 0 0 {name=p4 sig_type=std_logic lab=vsref} -C {lab_wire.sym} 720 -610 2 0 {name=p5 sig_type=std_logic lab=swp[0:11]} -C {lab_wire.sym} 420 -330 0 0 {name=p6 sig_type=std_logic lab=swp[0:11]} -C {lab_wire.sym} 720 -490 2 0 {name=p7 sig_type=std_logic lab=swn[0:11]} -C {lab_wire.sym} 420 -310 0 0 {name=p8 sig_type=std_logic lab=swn[0:11]} -C {lab_wire.sym} 420 -350 0 0 {name=p9 sig_type=std_logic lab=vcm} -C {lab_wire.sym} 420 -430 0 0 {name=p10 sig_type=std_logic lab=vcm} -C {lab_wire.sym} 420 -550 0 0 {name=p11 sig_type=std_logic lab=vcm} -C {lab_wire.sym} 420 -590 0 0 {name=p12 sig_type=std_logic lab=cf[0:11]} -C {lab_wire.sym} 420 -470 0 0 {name=p13 sig_type=std_logic lab=cf[0:11]} -C {lab_wire.sym} 420 -570 0 0 {name=p14 sig_type=std_logic lab=swp_in[0:11]} -C {lab_wire.sym} 420 -450 0 0 {name=p15 sig_type=std_logic lab=swn_in[0:11]} -C {lab_wire.sym} 720 -350 0 1 {name=p16 sig_type=std_logic lab=vcp} -C {lab_wire.sym} 720 -330 0 1 {name=p17 sig_type=std_logic lab=vcn} -C {ipin.sym} 180 -620 0 0 {name=p18 lab=vdref} -C {ipin.sym} 180 -590 0 0 {name=p19 lab=cf[0:11]} -C {ipin.sym} 180 -560 0 0 {name=p20 lab=swp_in[0:11]} -C {ipin.sym} 180 -530 0 0 {name=p21 lab=swn_in[0:11]} -C {ipin.sym} 180 -500 0 0 {name=p22 lab=vcm} -C {ipin.sym} 180 -470 0 0 {name=p23 lab=vsref} -C {iopin.sym} 160 -440 0 0 {name=p24 lab=vcp} -C {iopin.sym} 160 -410 0 0 {name=p25 lab=vcn} +C {devices/lab_wire.sym} 420 -610 0 0 {name=p1 sig_type=std_logic lab=vdref} +C {devices/lab_wire.sym} 420 -490 0 0 {name=p2 sig_type=std_logic lab=vdref} +C {devices/lab_wire.sym} 420 -530 0 0 {name=p3 sig_type=std_logic lab=vsref} +C {devices/lab_wire.sym} 420 -410 0 0 {name=p4 sig_type=std_logic lab=vsref} +C {devices/lab_wire.sym} 720 -610 2 0 {name=p5 sig_type=std_logic lab=swp[0:9]} +C {devices/lab_wire.sym} 420 -330 0 0 {name=p6 sig_type=std_logic lab=swp[0:9]} +C {devices/lab_wire.sym} 720 -490 2 0 {name=p7 sig_type=std_logic lab=swn[0:9]} +C {devices/lab_wire.sym} 420 -250 0 0 {name=p8 sig_type=std_logic lab=swn[0:9]} +C {devices/lab_wire.sym} 420 -350 0 0 {name=p9 sig_type=std_logic lab=vcm} +C {devices/lab_wire.sym} 420 -430 0 0 {name=p10 sig_type=std_logic lab=vcm} +C {devices/lab_wire.sym} 420 -550 0 0 {name=p11 sig_type=std_logic lab=vcm} +C {devices/lab_wire.sym} 420 -590 0 0 {name=p12 sig_type=std_logic lab=cf[0:9]} +C {devices/lab_wire.sym} 420 -470 0 0 {name=p13 sig_type=std_logic lab=cf[0:9]} +C {devices/lab_wire.sym} 420 -570 0 0 {name=p14 sig_type=std_logic lab=swp_in[0:9]} +C {devices/lab_wire.sym} 420 -450 0 0 {name=p15 sig_type=std_logic lab=swn_in[0:9]} +C {devices/lab_wire.sym} 720 -350 0 1 {name=p16 sig_type=std_logic lab=vcp} +C {devices/lab_wire.sym} 720 -270 0 1 {name=p17 sig_type=std_logic lab=vcn} +C {devices/ipin.sym} 180 -620 0 0 {name=p18 lab=vdref} +C {devices/ipin.sym} 180 -590 0 0 {name=p19 lab=cf[0:11]} +C {devices/ipin.sym} 180 -560 0 0 {name=p20 lab=swp_in[0:11]} +C {devices/ipin.sym} 180 -530 0 0 {name=p21 lab=swn_in[0:11]} +C {devices/ipin.sym} 180 -500 0 0 {name=p22 lab=vcm} +C {devices/ipin.sym} 180 -470 0 0 {name=p23 lab=vsref} +C {devices/iopin.sym} 160 -440 0 0 {name=p24 lab=vcp} +C {devices/iopin.sym} 160 -410 0 0 {name=p25 lab=vcn} +C {10b_cap_array.sym} 570 -260 0 0 {name=x2} +C {devices/lab_wire.sym} 420 -270 0 0 {name=p27 sig_type=std_logic lab=vcm} diff --git a/xschem/ckc_shifter.sch b/xschem/ckc_shifter.sch index c429677..eb366fe 100644 --- a/xschem/ckc_shifter.sch +++ b/xschem/ckc_shifter.sch @@ -5,6 +5,12 @@ K {} V {} S {} E {} +N 680 -310 750 -310 { +lab=#net1} +N 750 -310 750 -260 { +lab=#net1} +N 750 -260 760 -260 { +lab=#net1} C {sky130_stdcells/dfrbp_2.sym} 290 -170 0 0 {name=x1 VGND=VSSD VNB=VSSD VPB=VDDD VPWR=VDDD prefix=sky130_fd_sc_hd__ } C {devices/lab_wire.sym} 200 -190 0 0 {name=p1 sig_type=std_logic lab=CLK} C {devices/lab_wire.sym} 200 -170 0 0 {name=p2 sig_type=std_logic lab=FB0} @@ -13,18 +19,19 @@ C {devices/lab_wire.sym} 380 -190 0 1 {name=p4 sig_type=std_logic lab=CLK_1} C {devices/lab_wire.sym} 200 -150 0 0 {name=p5 sig_type=std_logic lab=VDDD} C {sky130_stdcells/dfrbp_2.sym} 590 -290 0 0 {name=x2 VGND=VSSD VNB=VSSD VPB=VDDD VPWR=VDDD prefix=sky130_fd_sc_hd__ } C {devices/lab_wire.sym} 500 -190 0 0 {name=p6 sig_type=std_logic lab=FB0} -C {devices/lab_wire.sym} 500 -290 0 0 {name=p7 sig_type=std_logic lab=CLK_S} -C {devices/lab_wire.sym} 680 -290 0 1 {name=p8 sig_type=std_logic lab=CLK_S} -C {devices/noconn.sym} 680 -310 0 1 {name=l9 sig_type=std_logic lab=CLK_1} +C {devices/lab_wire.sym} 680 -190 0 1 {name=p8 sig_type=std_logic lab=CLK_S} C {devices/lab_wire.sym} 500 -270 0 0 {name=p10 sig_type=std_logic lab=VDDD} C {sky130_stdcells/dfrbp_2.sym} 590 -170 0 0 {name=x3 VGND=VSSD VNB=VSSD VPB=VDDD VPWR=VDDD prefix=sky130_fd_sc_hd__ } C {devices/lab_wire.sym} 500 -310 0 0 {name=p11 sig_type=std_logic lab=CLK_1} C {devices/lab_wire.sym} 500 -170 0 0 {name=p12 sig_type=std_logic lab=FB1} C {devices/lab_wire.sym} 680 -170 0 1 {name=p13 sig_type=std_logic lab=FB1} -C {devices/lab_wire.sym} 680 -190 0 1 {name=p14 sig_type=std_logic lab=CLK_NS} +C {devices/lab_wire.sym} 840 -260 0 1 {name=p14 sig_type=std_logic lab=CLK_NS} C {devices/lab_wire.sym} 500 -150 0 0 {name=p15 sig_type=std_logic lab=VDDD} C {devices/ipin.sym} 80 -320 0 0 {name=p19 sig_type=std_logic lab=CLK} C {devices/ipin.sym} 80 -340 0 0 {name=p20 sig_type=std_logic lab=VDDD} C {devices/ipin.sym} 80 -300 0 0 {name=p22 sig_type=std_logic lab=VSSD} C {devices/opin.sym} 60 -260 0 0 {name=p23 sig_type=std_logic lab=CLK_NS} C {devices/opin.sym} 60 -240 0 0 {name=p24 sig_type=std_logic lab=CLK_S} +C {devices/lab_wire.sym} 680 -290 0 1 {name=p9 sig_type=std_logic lab=FB2} +C {devices/lab_wire.sym} 500 -290 0 0 {name=p7 sig_type=std_logic lab=FB2} +C {sky130_stdcells/inv_4.sym} 800 -260 0 0 {name=x4 VGND=VSSD VNB=VSSD VPB=VDDD VPWR=VDDD prefix=sky130_fd_sc_hd__ } diff --git a/xschem/epc.sch b/xschem/epc.sch index 876ac6d..d743522 100644 --- a/xschem/epc.sch +++ b/xschem/epc.sch @@ -22,18 +22,18 @@ lab=#net2} N 810 -380 1080 -380 { lab=#net2} N 470 -570 540 -570 { -lab=#net3} +lab=VP} N 490 -550 540 -550 { -lab=#net4} +lab=VN} N 810 -360 850 -360 { -lab=#net5} +lab=VN} N 810 -340 840 -340 { -lab=#net6} -C {sky130_stdcells/nand2_1.sym} 1020 -590 0 0 {name=x9 VGND=VSSA VNB=VSSA VPB=VDDA VPWR=VDDA prefix=sky130_fd_sc_hd__ } -C {sky130_stdcells/nand2_1.sym} 360 -380 0 1 {name=x10 VGND=VSSA VNB=VSSA VPB=VDDA VPWR=VDDA prefix=sky130_fd_sc_hd__ } +lab=VP} +C {sky130_stdcells/nand2_1.sym} 1020 -590 0 0 {name=x9 VGND=VSSD VNB=VSSD VPB=VDDD VPWR=VDDD prefix=sky130_fd_sc_hd__ } +C {sky130_stdcells/nand2_1.sym} 360 -380 0 1 {name=x10 VGND=VSSD VNB=VSSD VPB=VDDD VPWR=VDDD prefix=sky130_fd_sc_hd__ } C {devices/lab_wire.sym} 420 -360 0 1 {name=p25 sig_type=std_logic lab=START} C {devices/lab_wire.sym} 960 -570 0 0 {name=p26 sig_type=std_logic lab=START} -C {devices/ipin.sym} 410 -210 0 0 {name=p27 lab=VDDA} +C {devices/ipin.sym} 410 -210 0 0 {name=p27 lab=VDDD} C {devices/ipin.sym} 410 -180 0 0 {name=p28 lab=VP} C {devices/ipin.sym} 410 -150 0 0 {name=p29 lab=VN} C {devices/ipin.sym} 410 -90 0 0 {name=p30 lab=VSSA} @@ -54,3 +54,5 @@ C {devices/lab_wire.sym} 470 -570 0 0 {name=p3 sig_type=std_logic lab=VP} C {devices/lab_wire.sym} 840 -340 0 1 {name=p5 sig_type=std_logic lab=VP} C {devices/lab_wire.sym} 850 -360 0 1 {name=p6 sig_type=std_logic lab=VN} C {devices/lab_wire.sym} 490 -550 0 0 {name=p7 sig_type=std_logic lab=VN} +C {devices/ipin.sym} 410 -240 0 0 {name=p10 lab=VDDA} +C {devices/ipin.sym} 410 -60 0 0 {name=p11 lab=VSSD} diff --git a/xschem/epc.spice b/xschem/epc.spice deleted file mode 100644 index c36cc67..0000000 --- a/xschem/epc.spice +++ /dev/null @@ -1,57 +0,0 @@ -** sch_path: /home/mthudaa/Documents/UNIC-CASS-TSAR-ADC-ITS/xschem/epc.sch -**.subckt epc VDDA OUTP VP OUTN VN START VSSA -*.ipin VDDA -*.ipin VP -*.ipin VN -*.ipin VSSA -*.opin OUTP -*.ipin START -*.opin OUTN -x9 OUTP START VSSA VSSA VDDA VDDA net2 sky130_fd_sc_hd__nand2_1 -x10 OUTN START VSSA VSSA VDDA VDDA net1 sky130_fd_sc_hd__nand2_1 -x1 VDDA net1 VP VN VSSA OUTP epc_delay_line -x2 VDDA net2 VN VP VSSA OUTN epc_delay_line -**.ends - -* expanding symbol: epc_delay_line.sym # of pins=6 -** sym_path: /home/mthudaa/Documents/UNIC-CASS-TSAR-ADC-ITS/xschem/epc_delay_line.sym -** sch_path: /home/mthudaa/Documents/UNIC-CASS-TSAR-ADC-ITS/xschem/epc_delay_line.sch -.subckt epc_delay_line vdd in vp vn vss out -*.ipin vdd -*.ipin in -*.ipin vp -*.ipin vn -*.ipin vss -*.opin out -x1 in net1 vp vdd vss epc_delay -x2 net1 net2 vn vdd vss epc_delay -x3 net2 net3 vp vdd vss epc_delay -x4 net3 net4 vn vdd vss epc_delay -x5 net4 net5 vp vdd vss epc_delay -x6 net5 net6 vn vdd vss epc_delay -x7 net6 net7 vp vdd vss epc_delay -x8 net7 out vn vdd vss epc_delay -.ends - - -* expanding symbol: epc_delay.sym # of pins=5 -** sym_path: /home/mthudaa/Documents/UNIC-CASS-TSAR-ADC-ITS/xschem/epc_delay.sym -** sch_path: /home/mthudaa/Documents/UNIC-CASS-TSAR-ADC-ITS/xschem/epc_delay.sch -.subckt epc_delay IN OUT VIN VDD VSS -*.ipin VDD -*.ipin VIN -*.ipin IN -*.ipin VSS -*.opin OUT -.param W_N=0.5 L_N=0.5 W_P=1.0 L_P=0.5 -XM1 net2 VIN VDD VDD sky130_fd_pr__pfet_01v8_lvt L=L_P W=W_P nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM2 OUT IN net2 VDD sky130_fd_pr__pfet_01v8_lvt L=L_P W=W_P nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM3 OUT IN net1 VSS sky130_fd_pr__nfet_01v8_lvt L=L_N W=W_N nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM4 net1 VIN VSS VSS sky130_fd_pr__nfet_01v8_lvt L=L_N W=W_N nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -.ends - -.end diff --git a/xschem/epc.sym b/xschem/epc.sym index e5ebf48..bcdbc0d 100644 --- a/xschem/epc.sym +++ b/xschem/epc.sym @@ -4,23 +4,26 @@ format="@name @pinlist @symname" template="name=x1" } T {@symname} -31.5 -6 0 0 0.3 0.3 {} -T {@name} 135 -62 0 0 0.2 0.2 {} -L 4 -130 -50 130 -50 {} -L 4 -130 50 130 50 {} -L 4 -130 -50 -130 50 {} -L 4 130 -50 130 50 {} -B 5 -152.5 -42.5 -147.5 -37.5 {name=VDDA dir=in} +T {@name} 135 -82 0 0 0.2 0.2 {} +L 4 -130 -70 130 -70 {} +L 4 -130 70 130 70 {} +L 4 -130 -70 -130 70 {} +L 4 130 -70 130 70 {} +B 5 -152.5 -62.5 -147.5 -57.5 {name=VDDA dir=in} +L 4 -150 -60 -130 -60 {} +T {VDDA} -125 -64 0 0 0.2 0.2 {} +B 5 -152.5 -42.5 -147.5 -37.5 {name=VDDD dir=in} L 4 -150 -40 -130 -40 {} -T {VDDA} -125 -44 0 0 0.2 0.2 {} -B 5 147.5 -42.5 152.5 -37.5 {name=OUTP dir=out} -L 4 130 -40 150 -40 {} -T {OUTP} 125 -44 0 1 0.2 0.2 {} +T {VDDD} -125 -44 0 0 0.2 0.2 {} +B 5 147.5 -62.5 152.5 -57.5 {name=OUTP dir=out} +L 4 130 -60 150 -60 {} +T {OUTP} 125 -64 0 1 0.2 0.2 {} B 5 -152.5 -22.5 -147.5 -17.5 {name=VP dir=in} L 4 -150 -20 -130 -20 {} T {VP} -125 -24 0 0 0.2 0.2 {} -B 5 147.5 -22.5 152.5 -17.5 {name=OUTN dir=out} -L 4 130 -20 150 -20 {} -T {OUTN} 125 -24 0 1 0.2 0.2 {} +B 5 147.5 -42.5 152.5 -37.5 {name=OUTN dir=out} +L 4 130 -40 150 -40 {} +T {OUTN} 125 -44 0 1 0.2 0.2 {} B 5 -152.5 -2.5 -147.5 2.5 {name=VN dir=in} L 4 -150 0 -130 0 {} T {VN} -125 -4 0 0 0.2 0.2 {} @@ -30,3 +33,6 @@ T {START} -125 16 0 0 0.2 0.2 {} B 5 -152.5 37.5 -147.5 42.5 {name=VSSA dir=in} L 4 -150 40 -130 40 {} T {VSSA} -125 36 0 0 0.2 0.2 {} +B 5 -152.5 57.5 -147.5 62.5 {name=VSSD dir=in} +L 4 -150 60 -130 60 {} +T {VSSD} -125 56 0 0 0.2 0.2 {} diff --git a/xschem/epc_delay.sch b/xschem/epc_delay.sch index 471bd1c..d82515b 100644 --- a/xschem/epc_delay.sch +++ b/xschem/epc_delay.sch @@ -36,7 +36,8 @@ C {devices/ipin.sym} 530 -280 0 0 {name=p12 lab=VIN} C {devices/ipin.sym} 530 -340 0 0 {name=p13 lab=IN} C {devices/ipin.sym} 530 -220 0 0 {name=p14 lab=VSS} C {devices/opin.sym} 510 -310 0 0 {name=p19 lab=OUT} -C {devices/param.sym} 430 -370 0 0 {name=s1 value="W_N=0.5 L_N=0.5 W_P=1.0 L_P=0.5"} +C {devices/param.sym} 400 -490 0 0 {name=s1 +value="W_P=9 W_N=3 L_N=0.4 L_P=0.4"} C {sky130_fd_pr/pfet_01v8_lvt.sym} 180 -400 0 0 {name=M1 L=L_P W=W_P diff --git a/xschem/epc_delay_line.sch b/xschem/epc_delay_line.sch index fda8da6..b5a779f 100644 --- a/xschem/epc_delay_line.sch +++ b/xschem/epc_delay_line.sch @@ -19,6 +19,8 @@ N 2260 -350 2300 -350 { lab=#net6} N 2600 -350 2640 -350 { lab=#net7} +N 2940 -350 2980 -350 { +lab=#net8} C {epc_delay.sym} 410 -320 0 0 {name=x1} C {devices/lab_wire.sym} 260 -310 0 0 {name=p1 sig_type=std_logic lab=vdd} C {devices/lab_wire.sym} 260 -330 0 0 {name=p2 sig_type=std_logic lab=vp @@ -69,11 +71,11 @@ C {devices/lab_wire.sym} 2640 -290 0 0 {name=p24 sig_type=std_logic lab=vss } C {devices/lab_wire.sym} 260 -350 0 0 {name=p25 sig_type=std_logic lab=in } -C {devices/lab_wire.sym} 2940 -350 0 1 {name=p26 sig_type=std_logic lab=out -} C {devices/ipin.sym} 120 -380 0 0 {name=p27 lab=vdd} C {devices/ipin.sym} 120 -360 0 0 {name=p28 lab=in} C {devices/ipin.sym} 120 -340 0 0 {name=p29 lab=vp} C {devices/ipin.sym} 120 -320 0 0 {name=p30 lab=vn} C {devices/ipin.sym} 120 -300 0 0 {name=p31 lab=vss} C {devices/opin.sym} 100 -280 0 0 {name=p32 lab=out} +C {devices/lab_wire.sym} 2980 -350 0 1 {name=p58 sig_type=std_logic lab=out +} diff --git a/xschem/epc_value_processor.sch b/xschem/epc_value_processor.sch index e640e8c..23e9aa3 100644 --- a/xschem/epc_value_processor.sch +++ b/xschem/epc_value_processor.sch @@ -7,24 +7,20 @@ S {} E {} N 360 -180 400 -180 { lab=#net1} -N 540 -200 560 -200 { -lab=#net2} N 260 -220 400 -220 { lab=COMP_N} N 260 -180 280 -180 { lab=COMP_P} -N 520 -200 540 -200 { -lab=#net2} +N 520 -200 560 -200 { +lab=buf} C {sky130_stdcells/inv_1.sym} 320 -180 0 0 {name=x1 VGND=VSSD VNB=VSSD VPB=VDDD VPWR=VDDD prefix=sky130_fd_sc_hd__ } C {sky130_stdcells/nand2_1.sym} 460 -200 0 0 {name=x2 VGND=VSSD VNB=VSSD VPB=VDDD VPWR=VDDD prefix=sky130_fd_sc_hd__ } -C {sky130_stdcells/dfrtp_2.sym} 650 -200 0 0 {name=x3 VGND=VSSD VNB=VSSD VPB=VDDD VPWR=VDDD prefix=sky130_fd_sc_hd__ } C {devices/ipin.sym} 80 -240 0 0 {name=p19 sig_type=std_logic lab=COMP_P} C {devices/ipin.sym} 80 -260 0 0 {name=p20 sig_type=std_logic lab=VDDD} C {devices/ipin.sym} 80 -180 0 0 {name=p22 sig_type=std_logic lab=VSSD} C {devices/opin.sym} 60 -160 0 0 {name=p23 sig_type=std_logic lab=COMP} C {devices/opin.sym} 60 -140 0 0 {name=p24 sig_type=std_logic lab=RDY} C {devices/lab_wire.sym} 560 -220 0 0 {name=p8 sig_type=std_logic lab=CLK_S} -C {devices/lab_wire.sym} 560 -180 0 0 {name=p1 sig_type=std_logic lab=VDDD} C {devices/lab_wire.sym} 740 -220 0 1 {name=p2 sig_type=std_logic lab=COMP} C {devices/lab_wire.sym} 260 -220 0 0 {name=p3 sig_type=std_logic lab=COMP_N} C {devices/lab_wire.sym} 260 -180 0 0 {name=p4 sig_type=std_logic lab=COMP_P} @@ -33,3 +29,6 @@ C {devices/lab_wire.sym} 440 -120 0 0 {name=p5 sig_type=std_logic lab=CLK_S} C {devices/lab_wire.sym} 520 -120 0 1 {name=p6 sig_type=std_logic lab=RDY} C {devices/ipin.sym} 80 -220 0 0 {name=p7 sig_type=std_logic lab=COMP_N} C {devices/ipin.sym} 80 -200 0 0 {name=p9 sig_type=std_logic lab=CLK_S} +C {devices/lab_wire.sym} 560 -180 0 0 {name=p1 sig_type=std_logic lab=VDDD} +C {devices/lab_wire.sym} 560 -200 0 0 {name=p10 sig_type=std_logic lab=buf} +C {sky130_stdcells/dfrtp_4.sym} 650 -200 0 0 {name=x3 VGND=VSSD VNB=VSSD VPB=VDDD VPWR=VDDD prefix=sky130_fd_sc_hd__ } diff --git a/xschem/tcmp.sch b/xschem/tcmp.sch new file mode 100644 index 0000000..a2cced9 --- /dev/null +++ b/xschem/tcmp.sch @@ -0,0 +1,153 @@ +v {xschem version=3.4.5 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +B 2 1490 -530 2160 -20 {flags=graph +y1 = 0.1696 +y2 = 1.4576 +divy = 5 +subdivy=1 +x1=7.7704273e-05 +x2=0.00011964731 +divx=4 +subdivx=4 +node="comp +vinp +vinn +comp_p +comp_n" +color="4 5 6 12 13" unity=1 +dataset=-1 +sim_type=tran +hilight_wave=3} +B 2 2220 -530 2890 -20 {flags=graph +y1 = -1.3132893 +y2 = 2.9209297 +divy = 5 +subdivy=1 +x1=7.7704273e-05 +x2=0.00011964731 +divx=4 +subdivx=4 +node=comp +color=4 unity=1 +dataset=-1 +sim_type=tran} +B 2 1490 30 2160 540 {flags=graph +y1 = -0.019 +y2 = 1.1 +divy = 5 +subdivy=1 +x1=7.7704273e-05 +x2=0.00011964731 +divx=4 +subdivx=4 +node=comp_p +color=5 unity=1 +dataset=-1 +sim_type=tran +hilight_wave=0} +B 2 2210 30 2880 540 {flags=graph +y1 = 0.89720128 +y2 = 0.90196233 +divy = 5 +subdivy=1 +x1=7.7704273e-05 +x2=0.00011964731 +divx=4 +subdivx=4 + + unity=1 +dataset=-1 +sim_type=tran +color="4 5" +node="vinp +vinn"} +B 2 2940 -530 3610 -20 {flags=graph +y1 = -0.27680889 +y2 = 1.9467538 +divy = 5 +subdivy=1 +x1=7.7704273e-05 +x2=0.00011964731 +divx=4 +subdivx=4 +node="clk +clks" +color="4 5" unity=1 +dataset=-1 +sim_type=tran} +C {devices/vsource.sym} 1220 -50 0 0 {name=V1 value=0 savecurrent=false} +C {devices/vsource.sym} 920 -50 0 0 {name=V2 value="\{VDDA\}" savecurrent=false} +C {devices/vsource.sym} 1220 -210 0 0 {name=V3 value="PULSE(0 \{VDDD\} 10n 50p 50p 0.25u 0.5u)" savecurrent=false} +C {devices/vsource.sym} 1220 -320 0 0 {name=V4 value="PWL(0 \{VINP_start\}, \{t_ramp\} \{VINP_end\})" savecurrent=false} +C {devices/lab_wire.sym} 1220 -80 0 0 {name=p27 sig_type=std_logic lab=vssa} +C {devices/lab_wire.sym} 920 -20 2 0 {name=p28 sig_type=std_logic lab=vssa} +C {devices/lab_wire.sym} 1220 -180 2 0 {name=p29 sig_type=std_logic lab=vssa} +C {devices/lab_wire.sym} 1220 -290 2 0 {name=p30 sig_type=std_logic lab=vssa} +C {devices/lab_wire.sym} 920 -80 0 0 {name=p31 sig_type=std_logic lab=vdda} +C {devices/gnd.sym} 1220 -20 0 0 {name=l1 lab=GND} +C {devices/lab_wire.sym} 1220 -240 0 0 {name=p32 sig_type=std_logic lab=start} +C {devices/lab_wire.sym} 1220 -390 2 0 {name=p33 sig_type=std_logic lab=vssa} +C {devices/vsource.sym} 1220 -420 0 0 {name=V5 value="\{VIN_nominal\}" savecurrent=false} +C {devices/lab_wire.sym} 1220 -350 0 0 {name=p34 sig_type=std_logic lab=vinp} +C {devices/lab_wire.sym} 1220 -450 0 0 {name=p35 sig_type=std_logic lab=vinn} +C {devices/code.sym} 485 -125 0 0 {name=TT_MODELS +only_toplevel=true +format="tcleval( @value )" +value=" +** opencircuitdesign pdks install +.lib $::SKYWATER_MODELS/sky130.lib.spice tt_mm +.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice +" +spice_ignore=false} +C {devices/code.sym} 625 -125 0 0 {name=s2 only_toplevel=false value=" +.option wnflag=1 +.option savecurrents +.control +tran 1n 0.2u +write tcmp.raw +remzerovec +*quit 0 +.endc"} +C {devices/launcher.sym} 1555 -565 0 0 {name=h4 +descr="load waves" +tclcommand="xschem raw_read $netlist_dir/tcmp.raw tran" +} +C {epc_value_processor.sym} 650 -340 0 0 {name=x1} +C {epc.sym} 650 -480 0 0 {name=x2} +C {devices/lab_wire.sym} 500 -380 0 0 {name=p1 sig_type=std_logic lab=vddd} +C {devices/lab_wire.sym} 500 -540 0 0 {name=p2 sig_type=std_logic lab=vdda} +C {devices/lab_wire.sym} 500 -300 0 0 {name=p3 sig_type=std_logic lab=vssa} +C {devices/lab_wire.sym} 500 -440 0 0 {name=p4 sig_type=std_logic lab=vssa} +C {devices/lab_wire.sym} 500 -500 0 0 {name=p5 sig_type=std_logic lab=vinp} +C {devices/lab_wire.sym} 500 -480 0 0 {name=p6 sig_type=std_logic lab=vinn} +C {devices/lab_wire.sym} 500 -610 0 0 {name=p7 sig_type=std_logic lab=start} +C {devices/lab_wire.sym} 800 -540 0 1 {name=p8 sig_type=std_logic lab=comp_p} +C {devices/lab_wire.sym} 800 -520 0 1 {name=p9 sig_type=std_logic lab=comp_n} +C {devices/lab_wire.sym} 500 -360 0 0 {name=p10 sig_type=std_logic lab=comp_p} +C {devices/lab_wire.sym} 500 -340 0 0 {name=p11 sig_type=std_logic lab=comp_n} +C {devices/lab_wire.sym} 800 -380 0 1 {name=p12 sig_type=std_logic lab=comp} +C {devices/lab_wire.sym} 800 -360 0 1 {name=p13 sig_type=std_logic lab=rdy} +C {ckc_shifter.sym} 650 -610 0 0 {name=x3} +C {devices/lab_wire.sym} 500 -630 0 0 {name=p14 sig_type=std_logic lab=vddd} +C {devices/lab_wire.sym} 500 -590 0 0 {name=p15 sig_type=std_logic lab=vssa} +C {devices/lab_wire.sym} 500 -460 0 0 {name=p16 sig_type=std_logic lab=clk} +C {devices/lab_wire.sym} 800 -630 0 1 {name=p17 sig_type=std_logic lab=clk} +C {devices/lab_wire.sym} 800 -610 0 1 {name=p18 sig_type=std_logic lab=clks} +C {devices/lab_wire.sym} 500 -320 0 0 {name=p19 sig_type=std_logic lab=clks} +C {devices/vsource.sym} 1060 -50 0 0 {name=V6 value="\{VDDD\}" savecurrent=false} +C {devices/lab_wire.sym} 1060 -20 2 0 {name=p20 sig_type=std_logic lab=vssa} +C {devices/lab_wire.sym} 1060 -80 0 0 {name=p21 sig_type=std_logic lab=vddd} +C {devices/lab_wire.sym} 500 -420 0 0 {name=p22 sig_type=std_logic lab=vssa} +C {devices/lab_wire.sym} 500 -520 0 0 {name=p23 sig_type=std_logic lab=vddd} +C {devices/param.sym} 240 -140 0 0 {name=s1 value="VDDA=1.8 ++VDDD=1.8 ++VIN_nominal=0.9 ++VINP_start=0.89 ++VINP_end=0.91 ++t_ramp=0.2m +"} diff --git a/xschem/tdc_epc.sch b/xschem/tdc_epc.sch new file mode 100644 index 0000000..fc5ca41 --- /dev/null +++ b/xschem/tdc_epc.sch @@ -0,0 +1,40 @@ +v {xschem version=3.4.5 file_version=1.2 +} +G {} +K {} +V {} +S {} +E {} +C {epc_value_processor.sym} 650 -340 0 0 {name=x1} +C {epc.sym} 650 -480 0 0 {name=x2} +C {devices/lab_wire.sym} 500 -380 0 0 {name=p1 sig_type=std_logic lab=vddd} +C {devices/lab_wire.sym} 500 -540 0 0 {name=p2 sig_type=std_logic lab=vdda} +C {devices/lab_wire.sym} 500 -300 0 0 {name=p3 sig_type=std_logic lab=vssd} +C {devices/lab_wire.sym} 500 -440 0 0 {name=p4 sig_type=std_logic lab=vssa} +C {devices/lab_wire.sym} 500 -500 0 0 {name=p5 sig_type=std_logic lab=vinp} +C {devices/lab_wire.sym} 500 -480 0 0 {name=p6 sig_type=std_logic lab=vinn} +C {devices/lab_wire.sym} 500 -600 0 0 {name=p7 sig_type=std_logic lab=ckc} +C {devices/lab_wire.sym} 800 -540 0 1 {name=p8 sig_type=std_logic lab=comp_p} +C {devices/lab_wire.sym} 800 -520 0 1 {name=p9 sig_type=std_logic lab=comp_n} +C {devices/lab_wire.sym} 500 -360 0 0 {name=p10 sig_type=std_logic lab=comp_p} +C {devices/lab_wire.sym} 500 -340 0 0 {name=p11 sig_type=std_logic lab=comp_n} +C {devices/lab_wire.sym} 800 -380 0 1 {name=p12 sig_type=std_logic lab=comp} +C {devices/lab_wire.sym} 800 -360 0 1 {name=p13 sig_type=std_logic lab=rdy} +C {ckc_shifter.sym} 650 -600 0 0 {name=x3} +C {devices/lab_wire.sym} 500 -620 0 0 {name=p14 sig_type=std_logic lab=vddd} +C {devices/lab_wire.sym} 500 -580 0 0 {name=p15 sig_type=std_logic lab=vssa} +C {devices/lab_wire.sym} 500 -460 0 0 {name=p16 sig_type=std_logic lab=clk} +C {devices/lab_wire.sym} 800 -620 0 1 {name=p17 sig_type=std_logic lab=clk} +C {devices/lab_wire.sym} 800 -600 0 1 {name=p18 sig_type=std_logic lab=clks} +C {devices/lab_wire.sym} 500 -320 0 0 {name=p19 sig_type=std_logic lab=clks} +C {devices/lab_wire.sym} 500 -420 0 0 {name=p22 sig_type=std_logic lab=vssd} +C {devices/lab_wire.sym} 500 -520 0 0 {name=p23 sig_type=std_logic lab=vddd} +C {devices/ipin.sym} 240 -560 0 0 {name=p20 sig_type=std_logic lab=vddd} +C {devices/ipin.sym} 240 -540 0 0 {name=p21 sig_type=std_logic lab=vdda} +C {devices/ipin.sym} 240 -520 0 0 {name=p24 sig_type=std_logic lab=ckc} +C {devices/ipin.sym} 240 -500 0 0 {name=p25 sig_type=std_logic lab=vinp} +C {devices/ipin.sym} 240 -480 0 0 {name=p26 sig_type=std_logic lab=vinn} +C {devices/ipin.sym} 240 -460 0 0 {name=p27 sig_type=std_logic lab=vssd} +C {devices/ipin.sym} 240 -440 0 0 {name=p28 sig_type=std_logic lab=vssa} +C {devices/opin.sym} 220 -400 0 0 {name=p29 sig_type=std_logic lab=comp} +C {devices/opin.sym} 220 -380 0 0 {name=p30 sig_type=std_logic lab=rdy} diff --git a/xschem/tdc_epc.sym b/xschem/tdc_epc.sym new file mode 100644 index 0000000..d719513 --- /dev/null +++ b/xschem/tdc_epc.sym @@ -0,0 +1,38 @@ +v {xschem version=3.4.5 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +T {@symname} -49.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -82 0 0 0.2 0.2 {} +L 4 -130 -70 130 -70 {} +L 4 -130 70 130 70 {} +L 4 -130 -70 -130 70 {} +L 4 130 -70 130 70 {} +B 5 -152.5 -62.5 -147.5 -57.5 {name=vddd sig_type=std_logic dir=in} +L 4 -150 -60 -130 -60 {} +T {vddd} -125 -64 0 0 0.2 0.2 {} +B 5 -152.5 -42.5 -147.5 -37.5 {name=vdda sig_type=std_logic dir=in} +L 4 -150 -40 -130 -40 {} +T {vdda} -125 -44 0 0 0.2 0.2 {} +B 5 -152.5 -22.5 -147.5 -17.5 {name=ckc sig_type=std_logic dir=in} +L 4 -150 -20 -130 -20 {} +T {ckc} -125 -24 0 0 0.2 0.2 {} +B 5 -152.5 -2.5 -147.5 2.5 {name=vinp sig_type=std_logic dir=in} +L 4 -150 0 -130 0 {} +T {vinp} -125 -4 0 0 0.2 0.2 {} +B 5 -152.5 17.5 -147.5 22.5 {name=vinn sig_type=std_logic dir=in} +L 4 -150 20 -130 20 {} +T {vinn} -125 16 0 0 0.2 0.2 {} +B 5 -152.5 37.5 -147.5 42.5 {name=vssd sig_type=std_logic dir=in} +L 4 -150 40 -130 40 {} +T {vssd} -125 36 0 0 0.2 0.2 {} +B 5 -152.5 57.5 -147.5 62.5 {name=vssa sig_type=std_logic dir=in} +L 4 -150 60 -130 60 {} +T {vssa} -125 56 0 0 0.2 0.2 {} +B 5 147.5 -62.5 152.5 -57.5 {name=comp sig_type=std_logic dir=out} +L 4 130 -60 150 -60 {} +T {comp} 125 -64 0 1 0.2 0.2 {} +B 5 147.5 -42.5 152.5 -37.5 {name=rdy sig_type=std_logic dir=out} +L 4 130 -40 150 -40 {} +T {rdy} 125 -44 0 1 0.2 0.2 {}