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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<p>Header package containing a collection of 128-bit SIMD operations over 8-bit integer (char) elements.
<a href="#details">More...</a></p>
<div class="textblock"><code>#include <<a class="el" href="vec__common__ppc_8h_source.html">pveclib/vec_common_ppc.h</a>></code><br />
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<p><a href="vec__char__ppc_8h_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:a3eca950eb052ce1b0ad7a8d20ce3f971"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__char__ppc_8h.html#a3eca950eb052ce1b0ad7a8d20ce3f971">vec_absdub</a> (<a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vra, <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vrb)</td></tr>
<tr class="memdesc:a3eca950eb052ce1b0ad7a8d20ce3f971"><td class="mdescLeft"> </td><td class="mdescRight">Vector Absolute Difference Unsigned byte. <a href="vec__char__ppc_8h.html#a3eca950eb052ce1b0ad7a8d20ce3f971">More...</a><br /></td></tr>
<tr class="separator:a3eca950eb052ce1b0ad7a8d20ce3f971"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a29190093e687e416c846b885eb2c10c6"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__char__ppc_8h.html#a29190093e687e416c846b885eb2c10c6">vec_clzb</a> (<a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vra)</td></tr>
<tr class="memdesc:a29190093e687e416c846b885eb2c10c6"><td class="mdescLeft"> </td><td class="mdescRight">Vector Count Leading Zeros Byte for a unsigned char (byte) elements. <a href="vec__char__ppc_8h.html#a29190093e687e416c846b885eb2c10c6">More...</a><br /></td></tr>
<tr class="separator:a29190093e687e416c846b885eb2c10c6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a81643bfed966830dd480cdcaada06e1b"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__char__ppc_8h.html#a81643bfed966830dd480cdcaada06e1b">vec_ctzb</a> (<a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vra)</td></tr>
<tr class="memdesc:a81643bfed966830dd480cdcaada06e1b"><td class="mdescLeft"> </td><td class="mdescRight">Vector Count Trailing Zeros Byte for a unsigned char (byte) elements. <a href="vec__char__ppc_8h.html#a81643bfed966830dd480cdcaada06e1b">More...</a><br /></td></tr>
<tr class="separator:a81643bfed966830dd480cdcaada06e1b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a04af2798abe4f5e568e8fd527bef3b02"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__char__ppc_8h.html#a04af2798abe4f5e568e8fd527bef3b02">vec_isalnum</a> (<a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_str)</td></tr>
<tr class="memdesc:a04af2798abe4f5e568e8fd527bef3b02"><td class="mdescLeft"> </td><td class="mdescRight">Vector isalpha. <a href="vec__char__ppc_8h.html#a04af2798abe4f5e568e8fd527bef3b02">More...</a><br /></td></tr>
<tr class="separator:a04af2798abe4f5e568e8fd527bef3b02"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab6ea0723c4ae1ce1b4137a25eae1a15e"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__char__ppc_8h.html#ab6ea0723c4ae1ce1b4137a25eae1a15e">vec_isalpha</a> (<a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_str)</td></tr>
<tr class="memdesc:ab6ea0723c4ae1ce1b4137a25eae1a15e"><td class="mdescLeft"> </td><td class="mdescRight">Vector isalnum. <a href="vec__char__ppc_8h.html#ab6ea0723c4ae1ce1b4137a25eae1a15e">More...</a><br /></td></tr>
<tr class="separator:ab6ea0723c4ae1ce1b4137a25eae1a15e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0152053aed21f65166488df7e6b6c2a9"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__char__ppc_8h.html#a0152053aed21f65166488df7e6b6c2a9">vec_isdigit</a> (<a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_str)</td></tr>
<tr class="memdesc:a0152053aed21f65166488df7e6b6c2a9"><td class="mdescLeft"> </td><td class="mdescRight">Vector isdigit. <a href="vec__char__ppc_8h.html#a0152053aed21f65166488df7e6b6c2a9">More...</a><br /></td></tr>
<tr class="separator:a0152053aed21f65166488df7e6b6c2a9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab2ec8f3ed5b75f1e1b21998484d878e8"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__char__ppc_8h.html#ab2ec8f3ed5b75f1e1b21998484d878e8">vec_mrgahb</a> (<a class="el" href="vec__common__ppc_8h.html#afb47075b07673afbf78f8c60298f3712">vui16_t</a> vra, <a class="el" href="vec__common__ppc_8h.html#afb47075b07673afbf78f8c60298f3712">vui16_t</a> vrb)</td></tr>
<tr class="memdesc:ab2ec8f3ed5b75f1e1b21998484d878e8"><td class="mdescLeft"> </td><td class="mdescRight">Vector Merge Algebraic High Byte operation. <a href="vec__char__ppc_8h.html#ab2ec8f3ed5b75f1e1b21998484d878e8">More...</a><br /></td></tr>
<tr class="separator:ab2ec8f3ed5b75f1e1b21998484d878e8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af07f90ac64ed898a5add48932b8ac010"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__char__ppc_8h.html#af07f90ac64ed898a5add48932b8ac010">vec_mrgalb</a> (<a class="el" href="vec__common__ppc_8h.html#afb47075b07673afbf78f8c60298f3712">vui16_t</a> vra, <a class="el" href="vec__common__ppc_8h.html#afb47075b07673afbf78f8c60298f3712">vui16_t</a> vrb)</td></tr>
<tr class="memdesc:af07f90ac64ed898a5add48932b8ac010"><td class="mdescLeft"> </td><td class="mdescRight">Vector Merge Algebraic Low Byte operation. <a href="vec__char__ppc_8h.html#af07f90ac64ed898a5add48932b8ac010">More...</a><br /></td></tr>
<tr class="separator:af07f90ac64ed898a5add48932b8ac010"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab8a776401631aedafdaf371e268fcfe7"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__char__ppc_8h.html#ab8a776401631aedafdaf371e268fcfe7">vec_mrgeb</a> (<a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vra, <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vrb)</td></tr>
<tr class="memdesc:ab8a776401631aedafdaf371e268fcfe7"><td class="mdescLeft"> </td><td class="mdescRight">Vector Merge Even Bytes operation. <a href="vec__char__ppc_8h.html#ab8a776401631aedafdaf371e268fcfe7">More...</a><br /></td></tr>
<tr class="separator:ab8a776401631aedafdaf371e268fcfe7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memdesc:a562bddfc070386aabced80167b4571af"><td class="mdescLeft"> </td><td class="mdescRight">Vector Merge Odd Halfwords operation. <a href="vec__char__ppc_8h.html#a562bddfc070386aabced80167b4571af">More...</a><br /></td></tr>
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<tr class="memdesc:a5b81ae683c42ead33d58b422ee8f85cb"><td class="mdescLeft"> </td><td class="mdescRight">Vector Multiply High Signed Bytes. <a href="vec__char__ppc_8h.html#a5b81ae683c42ead33d58b422ee8f85cb">More...</a><br /></td></tr>
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<tr class="memdesc:a81a67dcc2623020b065eb244bc54511c"><td class="mdescLeft"> </td><td class="mdescRight">Vector Multiply High Unsigned Bytes. <a href="vec__char__ppc_8h.html#a81a67dcc2623020b065eb244bc54511c">More...</a><br /></td></tr>
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<tr class="memitem:a425151e5a82ee9e204ffd81b1ec7a92c"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__char__ppc_8h.html#a425151e5a82ee9e204ffd81b1ec7a92c">vec_mulubm</a> (<a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vra, <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vrb)</td></tr>
<tr class="memdesc:a425151e5a82ee9e204ffd81b1ec7a92c"><td class="mdescLeft"> </td><td class="mdescRight">Vector Multiply Unsigned Byte Modulo. <a href="vec__char__ppc_8h.html#a425151e5a82ee9e204ffd81b1ec7a92c">More...</a><br /></td></tr>
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<tr class="memdesc:ae0c33360f34cc31ca2e381bf2e7c9ce6"><td class="mdescLeft"> </td><td class="mdescRight">Vector Population Count byte. <a href="vec__char__ppc_8h.html#ae0c33360f34cc31ca2e381bf2e7c9ce6">More...</a><br /></td></tr>
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<tr class="memdesc:a37d73a433e11ee7b67b12081a80c21f2"><td class="mdescLeft"> </td><td class="mdescRight">Vector Set Bool from Signed Byte. <a href="vec__char__ppc_8h.html#a37d73a433e11ee7b67b12081a80c21f2">More...</a><br /></td></tr>
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<tr class="memdesc:a095741b255775d4ccf6228a5655599a2"><td class="mdescLeft"> </td><td class="mdescRight">Vector Shift left Byte Immediate. <a href="vec__char__ppc_8h.html#a095741b255775d4ccf6228a5655599a2">More...</a><br /></td></tr>
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<tr class="memdesc:a253a59f286f91817dfac89459ccbeac6"><td class="mdescLeft"> </td><td class="mdescRight">Vector Shift Right Algebraic Byte Immediate. <a href="vec__char__ppc_8h.html#a253a59f286f91817dfac89459ccbeac6">More...</a><br /></td></tr>
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<tr class="memitem:a495109a7d46f4a97b56f22bb315ac567"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__char__ppc_8h.html#a495109a7d46f4a97b56f22bb315ac567">vec_srbi</a> (<a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vra, const unsigned int shb)</td></tr>
<tr class="memdesc:a495109a7d46f4a97b56f22bb315ac567"><td class="mdescLeft"> </td><td class="mdescRight">Vector Shift Right Byte Immediate. <a href="vec__char__ppc_8h.html#a495109a7d46f4a97b56f22bb315ac567">More...</a><br /></td></tr>
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<tr class="memdesc:a949a5b375e69a85e76a06e68831cb59a"><td class="mdescLeft"> </td><td class="mdescRight">Shift left double quadword by octet. Return a vector unsigned char that is the left most 16 chars after shifting left 0-15 octets (chars) of the 32 char double vector (vrw||vrx). The octet shift amount is from bits 121:124 of vrb. <a href="vec__char__ppc_8h.html#a949a5b375e69a85e76a06e68831cb59a">More...</a><br /></td></tr>
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<tr class="memdesc:a73501120e1af14864b7621e318645426"><td class="mdescLeft"> </td><td class="mdescRight">Vector tolower. <a href="vec__char__ppc_8h.html#a73501120e1af14864b7621e318645426">More...</a><br /></td></tr>
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<tr class="memitem:a86c23ce0e18ad18d46d27f80c40f465e"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__char__ppc_8h.html#a86c23ce0e18ad18d46d27f80c40f465e">vec_vmrgeb</a> (<a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vra, <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vrb)</td></tr>
<tr class="memdesc:a86c23ce0e18ad18d46d27f80c40f465e"><td class="mdescLeft"> </td><td class="mdescRight">Vector Merge Even Bytes. <a href="vec__char__ppc_8h.html#a86c23ce0e18ad18d46d27f80c40f465e">More...</a><br /></td></tr>
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<tr class="memdesc:a122434ec49f77cf6968e2cb9523e68d2"><td class="mdescLeft"> </td><td class="mdescRight">Vector Merge Odd Byte. <a href="vec__char__ppc_8h.html#a122434ec49f77cf6968e2cb9523e68d2">More...</a><br /></td></tr>
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</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Header package containing a collection of 128-bit SIMD operations over 8-bit integer (char) elements. </p>
<p>Most of these operations are implemented in a single VMX or VSX instruction on newer (POWER6/POWER7/POWER8/POWER9) processors. This header serves to fill in functional gaps for older (POWER7, POWER8) processors and provides in-line assembler implementations for older compilers that do not provide the build-ins.</p>
<p>Most vector char (8-bit integer) operations are are already covered by the original VMX (AKA Altivec) instructions. VMX intrinsic (compiler built-ins) operations are defined in <altivec.h> and described in the compiler documentation. PowerISA 2.07B (POWER8) added several useful byte operations (count leading zeros, population count) not included in the original VMX. PowerISA 3.0B (POWER9) adds several more (absolute difference, compare not equal, count trailing zeros, extend sign, extract/insert, and reverse bytes). Most of these intrinsic (compiler built-ins) operations are defined in <altivec.h> and described in the compiler documentation.</p>
<dl class="section note"><dt>Note</dt><dd>The compiler disables associated <altivec.h> built-ins if the <b>mcpu</b> target does not enable the specific instruction. For example if you compile with <b>-mcpu=power7</b>, vec_vclz and vec_vclzb will not be defined. But vec_clzb is always defined in this header, will generate the minimum code, appropriate for the target, and produce correct results.</dd></dl>
<p>This header covers operations that are either:</p>
<ul>
<li>Implemented in later processors and useful to programmers if the same operations are available on slightly older processors. This is required even if the operation is defined in the OpenPOWER ABI or <altivec.h>, as the compiler disables the associated built-ins if the <b>mcpu</b> target does not enable the instruction.</li>
<li>Defined in the OpenPOWER ABI but <em>not</em> yet defined in <altivec.n> provided by available compilers in common use. Examples include Count Leading Zeros and Population Count.</li>
<li>Commonly used operations, not covered by the ABI or <altivec.h>, and require multiple instructions or are not obvious. Examples include the multiply high, ASCII character tests, and shift immediate operations.</li>
</ul>
<h1><a class="anchor" id="i8_endian_issues_0_0"></a>
Endian problems with byte operations</h1>
<p>It would be useful to provide a vector multiply high byte (return the high order 8-bits of the 16-bit product) operation. This can be used for multiplicative inverse (effectively integer divide) operations. Neither integer multiply high nor divide are available as vector instructions. However the multiply high byte operation can be composed from the existing multiply even/odd byte operations followed by the vector merge even byte operation. Similarly a multiply low (modulo) byte operation can be composed from the existing multiply even/odd byte operations followed by the vector merge odd byte operation.</p>
<p>As a prerequisite we need to provide the merge even/odd byte operations. While PowerISA has added these operations for word and doubleword, instructions are not defined for byte and halfword. Fortunately vector merge operations are just a special case of vector permute. So the <a class="el" href="vec__char__ppc_8h.html#a122434ec49f77cf6968e2cb9523e68d2" title="Vector Merge Odd Byte.">vec_vmrgob()</a> and <a class="el" href="vec__char__ppc_8h.html#a86c23ce0e18ad18d46d27f80c40f465e" title="Vector Merge Even Bytes.">vec_vmrgeb()</a> implementation can use vec_perm and appropriate selection vectors to provide these merge operations.</p>
<p>As described for other element sizes this is complicated by <em>little-endian</em> (LE) support as specified in the OpenPOWER ABI and as implemented in the compilers. Little-endian changes the effective vector element numbering and the location of even and odd elements. This means that the vector built-ins provided by altivec.h may not generate the instructions you would expect. </p><dl class="section see"><dt>See also</dt><dd><a class="el" href="vec__int16__ppc_8h.html#i16_endian_issues_0_0">Endian problems with halfword operations</a> </dd>
<dd>
<a class="el" href="index.html#mainpage_endian_issues_1_1">General Endian Issues</a></dd></dl>
<p>So this header defines endian independent byte operations <a class="el" href="vec__char__ppc_8h.html#a86c23ce0e18ad18d46d27f80c40f465e" title="Vector Merge Even Bytes.">vec_vmrgeb()</a> and <a class="el" href="vec__char__ppc_8h.html#a122434ec49f77cf6968e2cb9523e68d2" title="Vector Merge Odd Byte.">vec_vmrgob()</a>. These operations are used in the implementation of the endian sensitive <a class="el" href="vec__char__ppc_8h.html#ab8a776401631aedafdaf371e268fcfe7" title="Vector Merge Even Bytes operation.">vec_mrgeb()</a> and <a class="el" href="vec__char__ppc_8h.html#a562bddfc070386aabced80167b4571af" title="Vector Merge Odd Halfwords operation.">vec_mrgob()</a>. These support the OpenPOWER ABI mandated merge even/odd semantic.</p>
<p>We also provide the merge algebraic high/low operations <a class="el" href="vec__char__ppc_8h.html#ab2ec8f3ed5b75f1e1b21998484d878e8" title="Vector Merge Algebraic High Byte operation.">vec_mrgahb()</a> and <a class="el" href="vec__char__ppc_8h.html#af07f90ac64ed898a5add48932b8ac010" title="Vector Merge Algebraic Low Byte operation.">vec_mrgalb()</a> to simplify extended precision arithmetic. These implementations use <a class="el" href="vec__char__ppc_8h.html#a86c23ce0e18ad18d46d27f80c40f465e" title="Vector Merge Even Bytes.">vec_vmrgeb()</a> and <a class="el" href="vec__char__ppc_8h.html#a122434ec49f77cf6968e2cb9523e68d2" title="Vector Merge Odd Byte.">vec_vmrgob()</a> as extended precision byte order does not change with endian. These operations are used in turn to implement multiply byte high/low/modulo (<a class="el" href="vec__char__ppc_8h.html#a5b81ae683c42ead33d58b422ee8f85cb" title="Vector Multiply High Signed Bytes.">vec_mulhsb()</a>, <a class="el" href="vec__char__ppc_8h.html#a81a67dcc2623020b065eb244bc54511c" title="Vector Multiply High Unsigned Bytes.">vec_mulhub()</a>, <a class="el" href="vec__char__ppc_8h.html#a425151e5a82ee9e204ffd81b1ec7a92c" title="Vector Multiply Unsigned Byte Modulo.">vec_mulubm()</a>).</p>
<p>These operations provide a basis for using the multiplicative inverse as a alternative to integer divide. </p><dl class="section see"><dt>See also</dt><dd><a class="el" href="vec__int16__ppc_8h.html#int16_examples_0_1">Examples, Divide by integer constant</a></dd></dl>
<h1><a class="anchor" id="int8_perf_0_0"></a>
Performance data.</h1>
<p>The performance characteristics of the merge and multiply byte operations are very similar to the halfword implementations. (see <a class="el" href="vec__int16__ppc_8h.html#int16_perf_0_0">Performance data.</a>).</p>
<h2><a class="anchor" id="int8_perf_0_1"></a>
More information.</h2>
<p>High level performance estimates are provided as an aid to function selection when evaluating algorithms. For background on how <em>Latency</em> and <em>Throughput</em> are derived see: <a class="el" href="index.html#perf_data">Performance data.</a> </p>
</div><h2 class="groupheader">Function Documentation</h2>
<a id="a3eca950eb052ce1b0ad7a8d20ce3f971"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3eca950eb052ce1b0ad7a8d20ce3f971">◆ </a></span>vec_absdub()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_absdub </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
<td class="paramname"><em>vra</em>, </td>
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<p>Vector Absolute Difference Unsigned byte. </p>
<p>Compute the absolute difference for each byte. For each unsigned byte, subtract B[i] from A[i] and return the absolute value of the difference.</p>
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<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">4 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
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<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">3 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vra</td><td>vector of 16 unsigned bytes </td></tr>
<tr><td class="paramname">vrb</td><td>vector of 16 unsigned bytes </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>vector of the absolute difference. </dd></dl>
</div>
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<a id="a29190093e687e416c846b885eb2c10c6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a29190093e687e416c846b885eb2c10c6">◆ </a></span>vec_clzb()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_clzb </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
<td class="paramname"><em>vra</em></td><td>)</td>
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<p>Vector Count Leading Zeros Byte for a unsigned char (byte) elements. </p>
<p>Count the number of leading '0' bits (0-7) within each byte element of a 128-bit vector.</p>
<p>For POWER8 (PowerISA 2.07B) or later use the Vector Count Leading Zeros Byte instruction <b>vclzb</b>. Otherwise use sequence of pre 2.07 VMX instructions. SIMDized count leading zeros inspired by:</p>
<p>Warren, Henry S. Jr and <em>Hacker's Delight</em>, 2nd Edition, Addison Wesley, 2013. Chapter 5 Counting Bits, Figure 5-12.</p>
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<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">2 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
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<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">3 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vra</td><td>128-bit vector treated as 16 x 8-bit unsigned integer (byte) elements. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>128-bit vector with the leading zeros count for each byte element. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a81643bfed966830dd480cdcaada06e1b">◆ </a></span>vec_ctzb()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_ctzb </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
<td class="paramname"><em>vra</em></td><td>)</td>
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<p>Vector Count Trailing Zeros Byte for a unsigned char (byte) elements. </p>
<p>Count the number of trailing '0' bits (0-8) within each byte element of a 128-bit vector.</p>
<p>For POWER9 (PowerISA 3.0B) or later use the Vector Count Trailing Zeros Byte instruction <b>vctzb</b>. Otherwise use a sequence of pre ISA 3.0 VMX instructions. SIMDized count trailing zeros inspired by:</p>
<p>Warren, Henry S. Jr and <em>Hacker's Delight</em>, 2nd Edition, Addison Wesley, 2013. Chapter 5 Counting Bits, Section 5-4.</p>
<table class="markdownTable">
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<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">6-8 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
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<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">3 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vra</td><td>128-bit vector treated as 16 x 8-bit unsigned char (byte) elements. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>128-bit vector with the trailing zeros count for each byte element. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a04af2798abe4f5e568e8fd527bef3b02">◆ </a></span>vec_isalnum()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_isalnum </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
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<p>Vector isalpha. </p>
<p>Return a vector boolean char with a true indicator for any character that is either Lower Case Alpha ASCII or Upper Case ASCII. False otherwise.</p>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">10-20 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
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<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">11-21 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramname">vec_str</td><td>vector of 16 ASCII characters </td></tr>
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</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>vector bool char of the isalpha operation applied to each character of vec_str. For each byte 0xff indicates true (isalpha), 0x00 indicates false. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ab6ea0723c4ae1ce1b4137a25eae1a15e">◆ </a></span>vec_isalpha()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_isalpha </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
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<p>Vector isalnum. </p>
<p>Return a vector boolean char with a true indicator for any character that is either Lower Case Alpha ASCII, Upper Case ASCII, or numeric ASCII. False otherwise.</p>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">9-18 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
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<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">10-19 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramname">vec_str</td><td>vector of 16 ASCII characters </td></tr>
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</dd>
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<dl class="section return"><dt>Returns</dt><dd>vector bool char of the isalnum operation applied to each character of vec_str. For each byte 0xff indicates true (isalpha), 0x00 indicates false. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a0152053aed21f65166488df7e6b6c2a9">◆ </a></span>vec_isdigit()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_isdigit </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
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<p>Vector isdigit. </p>
<p>Return a vector boolean char with a true indicator for any character that is ASCII decimal digit. False otherwise.</p>
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<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">4-13 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
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<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">5-14 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramname">vec_str</td><td>vector of 16 ASCII characters </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>vector bool char of the isdigit operation applied to each character of vec_str. For each byte 0xff indicates true (isdigit), 0x00 indicates false. </dd></dl>
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<a id="ab2ec8f3ed5b75f1e1b21998484d878e8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab2ec8f3ed5b75f1e1b21998484d878e8">◆ </a></span>vec_mrgahb()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_mrgahb </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#afb47075b07673afbf78f8c60298f3712">vui16_t</a> </td>
<td class="paramname"><em>vra</em>, </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#afb47075b07673afbf78f8c60298f3712">vui16_t</a> </td>
<td class="paramname"><em>vrb</em> </td>
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<p>Vector Merge Algebraic High Byte operation. </p>
<p>Merge only the high byte from 16 x Algebraic halfwords across vectors vra and vrb. This is effectively the Vector Merge Even Byte operation that is not modified for Endian.</p>
<p>For example merge the high 8-bits from each of 16 x 16-bit products as generated by vec_muleub/vec_muloub. This result is effectively a vector multiply high unsigned byte.</p>
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<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">2-13 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">3-14 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vra</td><td>128-bit vector unsigned short. </td></tr>
<tr><td class="paramname">vrb</td><td>128-bit vector unsigned short. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>A vector merge from only the high bytes of the 16 x Algebraic halfwords across vra and vrb. </dd></dl>
</div>
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<a id="af07f90ac64ed898a5add48932b8ac010"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af07f90ac64ed898a5add48932b8ac010">◆ </a></span>vec_mrgalb()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_mrgalb </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#afb47075b07673afbf78f8c60298f3712">vui16_t</a> </td>
<td class="paramname"><em>vra</em>, </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#afb47075b07673afbf78f8c60298f3712">vui16_t</a> </td>
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<p>Vector Merge Algebraic Low Byte operation. </p>
<p>Merge only the low bytes from 16 x Algebraic halfwords across vectors vra and vrb. This is effectively the Vector Merge Odd Bytes operation that is not modified for Endian.</p>
<p>For example merge the low 8-bits from each of 16 x 16-bit products as generated by vec_muleub/vec_muloub. This result is effectively a vector multiply low unsigned byte.</p>
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<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">2-13 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
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<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">3-14 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vra</td><td>128-bit vector unsigned int. </td></tr>
<tr><td class="paramname">vrb</td><td>128-bit vector unsigned int. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>A vector merge from only the high halfwords of the 8 x Algebraic words across vra and vrb. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ab8a776401631aedafdaf371e268fcfe7">◆ </a></span>vec_mrgeb()</h2>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
<td class="paramname"><em>vra</em>, </td>
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<p>Vector Merge Even Bytes operation. </p>
<p>Merge the even byte elements from the concatenation of 2 x vectors (vra and vrb).</p>
<dl class="section note"><dt>Note</dt><dd>The element numbering changes between Big and Little Endian. So the compiler and this implementation adjusts the generated code to reflect this.</dd></dl>
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<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">2-13 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
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<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">3-14 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vra</td><td>128-bit vector unsigned char. </td></tr>
<tr><td class="paramname">vrb</td><td>128-bit vector unsigned char. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>A vector merge from only the even bytes of vra and vrb. </dd></dl>
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<a id="a562bddfc070386aabced80167b4571af"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a562bddfc070386aabced80167b4571af">◆ </a></span>vec_mrgob()</h2>
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<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
<td class="paramname"><em>vra</em>, </td>
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<p>Vector Merge Odd Halfwords operation. </p>
<p>Merge the odd halfword elements from the concatenation of 2 x vectors (vra and vrb).</p>
<dl class="section note"><dt>Note</dt><dd>The element numbering changes between Big and Little Endian. So the compiler and this implementation adjusts the generated code to reflect this.</dd></dl>
<table class="markdownTable">
<tr class="markdownTableHead">
<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">2-13 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">3-14 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vra</td><td>128-bit vector unsigned char. </td></tr>
<tr><td class="paramname">vrb</td><td>128-bit vector unsigned char. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>A vector merge from only the odd bytes of vra and vrb. </dd></dl>
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</div>
<a id="a5b81ae683c42ead33d58b422ee8f85cb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5b81ae683c42ead33d58b422ee8f85cb">◆ </a></span>vec_mulhsb()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#a748bbf6563e6ab1ddcb694c86e2aaef4">vi8_t</a> vec_mulhsb </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#a748bbf6563e6ab1ddcb694c86e2aaef4">vi8_t</a> </td>
<td class="paramname"><em>vra</em>, </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#a748bbf6563e6ab1ddcb694c86e2aaef4">vi8_t</a> </td>
<td class="paramname"><em>vrb</em> </td>
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<p>Vector Multiply High Signed Bytes. </p>
<p>Multiple the corresponding byte elements of two vector signed char values and return the high order 8-bits, for each 16-bit product element.</p>
<table class="markdownTable">
<tr class="markdownTableHead">
<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">9-13 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">10-14 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vra</td><td>128-bit vector signed char. </td></tr>
<tr><td class="paramname">vrb</td><td>128-bit vector signed char. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>vector of the high order 8-bits of the product of the byte elements from vra and vrb. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a81a67dcc2623020b065eb244bc54511c">◆ </a></span>vec_mulhub()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_mulhub </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
<td class="paramname"><em>vra</em>, </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
<td class="paramname"><em>vrb</em> </td>
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<p>Vector Multiply High Unsigned Bytes. </p>
<p>Multiple the corresponding byte elements of two vector unsigned char values and return the high order 8-bits, for each 16-bit product element.</p>
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<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">9-13 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">10-14 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vra</td><td>128-bit vector unsigned char. </td></tr>
<tr><td class="paramname">vrb</td><td>128-bit vector unsigned char. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>vector of the high order 8-bits of the product of the byte elements from vra and vrb. </dd></dl>
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<a id="a425151e5a82ee9e204ffd81b1ec7a92c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a425151e5a82ee9e204ffd81b1ec7a92c">◆ </a></span>vec_mulubm()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_mulubm </td>
<td>(</td>
<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
<td class="paramname"><em>vra</em>, </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
<td class="paramname"><em>vrb</em> </td>
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<p>Vector Multiply Unsigned Byte Modulo. </p>
<p>Multiple the corresponding byte elements of two vector unsigned char values and return the low order 8-bits of the 16-bit product for each element.</p>
<dl class="section note"><dt>Note</dt><dd>vec_mulubm can be used for unsigned or signed char integers. It is the vector equivalent of Multiply Low Byte.</dd></dl>
<table class="markdownTable">
<tr class="markdownTableHead">
<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">9-13 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">10-14 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
</table>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vra</td><td>128-bit vector unsigned char. </td></tr>
<tr><td class="paramname">vrb</td><td>128-bit vector unsigned char. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>vector of the low order 8-bits of the unsigned product of the byte elements from vra and vrb. </dd></dl>
</div>
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<a id="ae0c33360f34cc31ca2e381bf2e7c9ce6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae0c33360f34cc31ca2e381bf2e7c9ce6">◆ </a></span>vec_popcntb()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_popcntb </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
<td class="paramname"><em>vra</em></td><td>)</td>
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<p>Vector Population Count byte. </p>
<p>Count the number of '1' bits (0-8) within each byte element of a 128-bit vector.</p>
<p>For POWER8 (PowerISA 2.07B) or later use the Vector Population Count Byte instruction. Otherwise use simple Vector (VMX) instructions to count bits in bytes in parallel. SIMDized population count inspired by:</p>
<p>Warren, Henry S. Jr and <em>Hacker's Delight</em>, 2nd Edition, Addison Wesley, 2013. Chapter 5 Counting Bits, Figure 5-2.</p>
<table class="markdownTable">
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<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">2 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
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<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">3 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vra</td><td>128-bit vector treated as 16 x 8-bit integers (byte) elements. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>128-bit vector with the population count for each byte element. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a37d73a433e11ee7b67b12081a80c21f2">◆ </a></span>vec_setb_sb()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#ab6d921b672d847662016cb3cbbe58f17">vb8_t</a> vec_setb_sb </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#a748bbf6563e6ab1ddcb694c86e2aaef4">vi8_t</a> </td>
<td class="paramname"><em>vra</em></td><td>)</td>
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<p>Vector Set Bool from Signed Byte. </p>
<p>For each byte, propagate the sign bit to all 8-bits of that byte. The result is vector bool char reflecting the sign bit of each 8-bit byte.</p>
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<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">2-4 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
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<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">2-5 </td><td class="markdownTableBodyLeft">2/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramname">vra</td><td>Vector signed char. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>vector bool char reflecting the sign bit of each byte. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a949a5b375e69a85e76a06e68831cb59a">◆ </a></span>vec_shift_leftdo()</h2>
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<td class="memname">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> vec_shift_leftdo </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
<td class="paramname"><em>vrw</em>, </td>
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<td class="paramtype"><a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td>
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<p>Shift left double quadword by octet. Return a vector unsigned char that is the left most 16 chars after shifting left 0-15 octets (chars) of the 32 char double vector (vrw||vrx). The octet shift amount is from bits 121:124 of vrb. </p>
<p>This sequence can be used to align a unaligned 16 char substring based on the result of a vector count leading zero of of the compare boolean.</p>
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<th class="markdownTableHeadRight">processor </th><th class="markdownTableHeadCenter">Latency </th><th class="markdownTableHeadLeft">Throughput </th></tr>
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<td class="markdownTableBodyRight">power8 </td><td class="markdownTableBodyCenter">6-8 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
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<td class="markdownTableBodyRight">power9 </td><td class="markdownTableBodyCenter">8-9 </td><td class="markdownTableBodyLeft">1/cycle </td></tr>
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<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">vrw</td><td>upper 16-bytes of the 32-byte double vector. </td></tr>
<tr><td class="paramname">vrx</td><td>lower 16-bytes of the 32-byte double vector. </td></tr>
<tr><td class="paramname">vrb</td><td>Shift amount in bits 121:124. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>upper 16-bytes of left shifted double vector. </dd></dl>