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vec__f128__ppc_8h.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<title>POWER Vector Library Manual: src/pveclib/vec_f128_ppc.h File Reference</title>
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 <span id="projectnumber">1.0.4</span>
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<div class="title">vec_f128_ppc.h File Reference</div> </div>
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<p>Header package containing a collection of 128-bit SIMD operations over Quad-Precision floating point elements.
<a href="#details">More...</a></p>
<div class="textblock"><code>#include <<a class="el" href="vec__common__ppc_8h_source.html">pveclib/vec_common_ppc.h</a>></code><br />
<code>#include <<a class="el" href="vec__int128__ppc_8h_source.html">pveclib/vec_int128_ppc.h</a>></code><br />
<code>#include <<a class="el" href="vec__f64__ppc_8h_source.html">pveclib/vec_f64_ppc.h</a>></code><br />
</div>
<p><a href="vec__f128__ppc_8h_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
Classes</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="union____VF__128.html">__VF_128</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Union used to transfer 128-bit data between vector and __float128 types. <a href="union____VF__128.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:a5c0751a2b64a9a560e9a964294f63166"><td class="memItemLeft" align="right" valign="top"><a id="a5c0751a2b64a9a560e9a964294f63166"></a>
typedef <a class="el" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a5c0751a2b64a9a560e9a964294f63166">vf128_t</a></td></tr>
<tr class="memdesc:a5c0751a2b64a9a560e9a964294f63166"><td class="mdescLeft"> </td><td class="mdescRight">vector of 128-bit binary128 element. Same as __float128 for PPC. <br />
<br /></td></tr>
<tr class="separator:a5c0751a2b64a9a560e9a964294f63166"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5f89d266b82d1a8f300348cf99b9ae3f"><td class="memItemLeft" align="right" valign="top"><a id="a5f89d266b82d1a8f300348cf99b9ae3f"></a>
typedef <a class="el" href="vec__f128__ppc_8h.html#a5c0751a2b64a9a560e9a964294f63166">vf128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a5f89d266b82d1a8f300348cf99b9ae3f">__Float128</a></td></tr>
<tr class="memdesc:a5f89d266b82d1a8f300348cf99b9ae3f"><td class="mdescLeft"> </td><td class="mdescRight">Define __Float128 if not defined by the compiler. Same as __float128 for PPC. <br />
<br /></td></tr>
<tr class="separator:a5f89d266b82d1a8f300348cf99b9ae3f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a443a43ae34ab3b78564d2a8277503cac"><td class="memItemLeft" align="right" valign="top"><a id="a443a43ae34ab3b78564d2a8277503cac"></a>
typedef <a class="el" href="vec__f128__ppc_8h.html#a5c0751a2b64a9a560e9a964294f63166">vf128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a></td></tr>
<tr class="memdesc:a443a43ae34ab3b78564d2a8277503cac"><td class="mdescLeft"> </td><td class="mdescRight">Define __binary128 if not defined by the compiler. Same as __float128 for PPC. <br />
<br /></td></tr>
<tr class="separator:a443a43ae34ab3b78564d2a8277503cac"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4af2270bedc312f7d99c0605358cd28c"><td class="memItemLeft" align="right" valign="top"><a id="a4af2270bedc312f7d99c0605358cd28c"></a>
typedef <a class="el" href="vec__f128__ppc_8h.html#a5c0751a2b64a9a560e9a964294f63166">vf128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a4af2270bedc312f7d99c0605358cd28c">__float128</a></td></tr>
<tr class="memdesc:a4af2270bedc312f7d99c0605358cd28c"><td class="mdescLeft"> </td><td class="mdescRight">Define __float128 if not defined by the compiler. Same as __float128 for PPC. <br />
<br /></td></tr>
<tr class="separator:a4af2270bedc312f7d99c0605358cd28c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a55019fe6dc8271e91613db7b1ae96721"><td class="memItemLeft" align="right" valign="top"><a id="a55019fe6dc8271e91613db7b1ae96721"></a>
typedef long double </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a55019fe6dc8271e91613db7b1ae96721">__IBM128</a></td></tr>
<tr class="memdesc:a55019fe6dc8271e91613db7b1ae96721"><td class="mdescLeft"> </td><td class="mdescRight">Define __IBM128 if not defined by the compiler. Same as old long double for PPC. <br />
<br /></td></tr>
<tr class="separator:a55019fe6dc8271e91613db7b1ae96721"><td class="memSeparator" colspan="2"> </td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:a380ba36beb77c11beb7050698a62fd23"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a380ba36beb77c11beb7050698a62fd23">vec_const64_f128_128</a> (void)</td></tr>
<tr class="memdesc:a380ba36beb77c11beb7050698a62fd23"><td class="mdescLeft"> </td><td class="mdescRight">Generate doubleword splat constant 128. <a href="vec__f128__ppc_8h.html#a380ba36beb77c11beb7050698a62fd23">More...</a><br /></td></tr>
<tr class="separator:a380ba36beb77c11beb7050698a62fd23"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a173efeafba080313d50e8b018c26c611"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a173efeafba080313d50e8b018c26c611">vec_const128_f128_128</a> (void)</td></tr>
<tr class="memdesc:a173efeafba080313d50e8b018c26c611"><td class="mdescLeft"> </td><td class="mdescRight">Generate Quadword constant 128. <a href="vec__f128__ppc_8h.html#a173efeafba080313d50e8b018c26c611">More...</a><br /></td></tr>
<tr class="separator:a173efeafba080313d50e8b018c26c611"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae1ef1a77f575bd319d6cf90e1b81765b"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#ae1ef1a77f575bd319d6cf90e1b81765b">vec_mask64_f128exp</a> (void)</td></tr>
<tr class="memdesc:ae1ef1a77f575bd319d6cf90e1b81765b"><td class="mdescLeft"> </td><td class="mdescRight">Generate Doubleword Quad-Precision exponent mask. <a href="vec__f128__ppc_8h.html#ae1ef1a77f575bd319d6cf90e1b81765b">More...</a><br /></td></tr>
<tr class="separator:ae1ef1a77f575bd319d6cf90e1b81765b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a553edc28189515110f96a6ab6531927f"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a553edc28189515110f96a6ab6531927f">vec_mask128_f128exp</a> (void)</td></tr>
<tr class="memdesc:a553edc28189515110f96a6ab6531927f"><td class="mdescLeft"> </td><td class="mdescRight">Generate Quadword Quad-Precision exponent mask. <a href="vec__f128__ppc_8h.html#a553edc28189515110f96a6ab6531927f">More...</a><br /></td></tr>
<tr class="separator:a553edc28189515110f96a6ab6531927f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5751b5c36a7a3d73c81abd7759e51594"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a5751b5c36a7a3d73c81abd7759e51594">vec_mask128_f128mag</a> (void)</td></tr>
<tr class="memdesc:a5751b5c36a7a3d73c81abd7759e51594"><td class="mdescLeft"> </td><td class="mdescRight">Generate Quadword Quad-Precision magnitude mask. <a href="vec__f128__ppc_8h.html#a5751b5c36a7a3d73c81abd7759e51594">More...</a><br /></td></tr>
<tr class="separator:a5751b5c36a7a3d73c81abd7759e51594"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a42ca6322cc3885264ca350a66b4e1bff"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a42ca6322cc3885264ca350a66b4e1bff">vec_mask128_f128sig</a> (void)</td></tr>
<tr class="memdesc:a42ca6322cc3885264ca350a66b4e1bff"><td class="mdescLeft"> </td><td class="mdescRight">Generate Quadword Quad-Precision significand mask. <a href="vec__f128__ppc_8h.html#a42ca6322cc3885264ca350a66b4e1bff">More...</a><br /></td></tr>
<tr class="separator:a42ca6322cc3885264ca350a66b4e1bff"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac94c7ddb75a8fc5f543e65e31e03f1c1"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#ac94c7ddb75a8fc5f543e65e31e03f1c1">vec_mask128_f128sign</a> (void)</td></tr>
<tr class="memdesc:ac94c7ddb75a8fc5f543e65e31e03f1c1"><td class="mdescLeft"> </td><td class="mdescRight">Generate Quadword Quad-Precision Sign-bit mask. <a href="vec__f128__ppc_8h.html#ac94c7ddb75a8fc5f543e65e31e03f1c1">More...</a><br /></td></tr>
<tr class="separator:ac94c7ddb75a8fc5f543e65e31e03f1c1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2ba9852d8733f6861d799a10027e1e95"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a2ba9852d8733f6861d799a10027e1e95">vec_mask128_f128Cbit</a> (void)</td></tr>
<tr class="memdesc:a2ba9852d8733f6861d799a10027e1e95"><td class="mdescLeft"> </td><td class="mdescRight">Generate Quadword C-bit mask Immediate. <a href="vec__f128__ppc_8h.html#a2ba9852d8733f6861d799a10027e1e95">More...</a><br /></td></tr>
<tr class="separator:a2ba9852d8733f6861d799a10027e1e95"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a29201a75ecd86b135dbb013dbd2ced75"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a29201a75ecd86b135dbb013dbd2ced75">vec_mask128_f128Lbit</a> (void)</td></tr>
<tr class="memdesc:a29201a75ecd86b135dbb013dbd2ced75"><td class="mdescLeft"> </td><td class="mdescRight">Generate Quadword L-bit mask Immediate. <a href="vec__f128__ppc_8h.html#a29201a75ecd86b135dbb013dbd2ced75">More...</a><br /></td></tr>
<tr class="separator:a29201a75ecd86b135dbb013dbd2ced75"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a619b1beb77d75c62ea9913e527bb0cf1"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a619b1beb77d75c62ea9913e527bb0cf1">vec_mask128_f128Qbit</a> (void)</td></tr>
<tr class="memdesc:a619b1beb77d75c62ea9913e527bb0cf1"><td class="mdescLeft"> </td><td class="mdescRight">Generate Quadword QNaN-bit mask Immediate. <a href="vec__f128__ppc_8h.html#a619b1beb77d75c62ea9913e527bb0cf1">More...</a><br /></td></tr>
<tr class="separator:a619b1beb77d75c62ea9913e527bb0cf1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2843ee28bf45b6e7589f2b1d073a2187"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a2843ee28bf45b6e7589f2b1d073a2187">vec_sel_bin128_2_bin128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb, <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> mask)</td></tr>
<tr class="memdesc:a2843ee28bf45b6e7589f2b1d073a2187"><td class="mdescLeft"> </td><td class="mdescRight">Select and Transfer from one of two __binary128 scalars under a 128-bit mask. The result is a __binary128 of the selected value. <a href="vec__f128__ppc_8h.html#a2843ee28bf45b6e7589f2b1d073a2187">More...</a><br /></td></tr>
<tr class="separator:a2843ee28bf45b6e7589f2b1d073a2187"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aae0e62b9910ec833dfc20719d09e526e"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aae0e62b9910ec833dfc20719d09e526e">vec_and_bin128_2_vui32t</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128, <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> mask)</td></tr>
<tr class="memdesc:aae0e62b9910ec833dfc20719d09e526e"><td class="mdescLeft"> </td><td class="mdescRight">Transfer a quadword from a __binary128 scalar to a vector int and logical AND with a mask. <a href="vec__f128__ppc_8h.html#aae0e62b9910ec833dfc20719d09e526e">More...</a><br /></td></tr>
<tr class="separator:aae0e62b9910ec833dfc20719d09e526e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aedfcf3adea80e0407b40c6ec0e851aab"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aedfcf3adea80e0407b40c6ec0e851aab">vec_andc_bin128_2_vui32t</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128, <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> mask)</td></tr>
<tr class="memdesc:aedfcf3adea80e0407b40c6ec0e851aab"><td class="mdescLeft"> </td><td class="mdescRight">Transfer a quadword from a __binary128 scalar to a vector int and logical AND Compliment with mask. <a href="vec__f128__ppc_8h.html#aedfcf3adea80e0407b40c6ec0e851aab">More...</a><br /></td></tr>
<tr class="separator:aedfcf3adea80e0407b40c6ec0e851aab"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3612e915d9043c23eeaac6eb5e129312"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a3612e915d9043c23eeaac6eb5e129312">vec_or_bin128_2_vui32t</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128, <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> mask)</td></tr>
<tr class="memdesc:a3612e915d9043c23eeaac6eb5e129312"><td class="mdescLeft"> </td><td class="mdescRight">Transfer a quadword from a __binary128 scalar to a vector int and logical OR with mask. <a href="vec__f128__ppc_8h.html#a3612e915d9043c23eeaac6eb5e129312">More...</a><br /></td></tr>
<tr class="separator:a3612e915d9043c23eeaac6eb5e129312"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7de75d3d010fe5ac7310322e2abea122"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a7de75d3d010fe5ac7310322e2abea122">vec_xor_bin128_2_vui32t</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128, <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> mask)</td></tr>
<tr class="memdesc:a7de75d3d010fe5ac7310322e2abea122"><td class="mdescLeft"> </td><td class="mdescRight">Transfer a quadword from a __binary128 scalar to a vector int and logical Exclusive OR with mask. <a href="vec__f128__ppc_8h.html#a7de75d3d010fe5ac7310322e2abea122">More...</a><br /></td></tr>
<tr class="separator:a7de75d3d010fe5ac7310322e2abea122"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a796440333ee623aa782ef3eb5a021587"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a796440333ee623aa782ef3eb5a021587">vec_andc_bin128_2_vui128t</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128, <a class="el" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> mask)</td></tr>
<tr class="memdesc:a796440333ee623aa782ef3eb5a021587"><td class="mdescLeft"> </td><td class="mdescRight">Transfer a quadword from a __binary128 scalar to a vector __int128 and logical AND Compliment with mask. <a href="vec__f128__ppc_8h.html#a796440333ee623aa782ef3eb5a021587">More...</a><br /></td></tr>
<tr class="separator:a796440333ee623aa782ef3eb5a021587"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a57dc5b9171d5ce3d49f0f12795659c1a"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a57dc5b9171d5ce3d49f0f12795659c1a">vec_xfer_bin128_2_vui8t</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a57dc5b9171d5ce3d49f0f12795659c1a"><td class="mdescLeft"> </td><td class="mdescRight">Transfer function from a __binary128 scalar to a vector char. <a href="vec__f128__ppc_8h.html#a57dc5b9171d5ce3d49f0f12795659c1a">More...</a><br /></td></tr>
<tr class="separator:a57dc5b9171d5ce3d49f0f12795659c1a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aff0629194f4f63bb083c271844459072"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#afb47075b07673afbf78f8c60298f3712">vui16_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aff0629194f4f63bb083c271844459072">vec_xfer_bin128_2_vui16t</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:aff0629194f4f63bb083c271844459072"><td class="mdescLeft"> </td><td class="mdescRight">Transfer function from a __binary128 scalar to a vector short int. <a href="vec__f128__ppc_8h.html#aff0629194f4f63bb083c271844459072">More...</a><br /></td></tr>
<tr class="separator:aff0629194f4f63bb083c271844459072"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8043c2c5ac35d2b0a8bd8f33779c91a6"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a8043c2c5ac35d2b0a8bd8f33779c91a6">vec_xfer_bin128_2_vui32t</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a8043c2c5ac35d2b0a8bd8f33779c91a6"><td class="mdescLeft"> </td><td class="mdescRight">Transfer function from a __binary128 scalar to a vector int. <a href="vec__f128__ppc_8h.html#a8043c2c5ac35d2b0a8bd8f33779c91a6">More...</a><br /></td></tr>
<tr class="separator:a8043c2c5ac35d2b0a8bd8f33779c91a6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1dff4f515dc0b37a4411401a44aa5157"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a1dff4f515dc0b37a4411401a44aa5157">vec_mrgh_bin128_2_vui64t</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a1dff4f515dc0b37a4411401a44aa5157"><td class="mdescLeft"> </td><td class="mdescRight">Merge High and Transfer function from a pair of __binary128 scalars to a vector long long int. <a href="vec__f128__ppc_8h.html#a1dff4f515dc0b37a4411401a44aa5157">More...</a><br /></td></tr>
<tr class="separator:a1dff4f515dc0b37a4411401a44aa5157"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afc2ac713dcb43499b47410c02b6c854c"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#afc2ac713dcb43499b47410c02b6c854c">vec_mrgl_bin128_2_vui64t</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:afc2ac713dcb43499b47410c02b6c854c"><td class="mdescLeft"> </td><td class="mdescRight">Merge Low and Transfer function from a pair of __binary128 scalars to a vector long long int. <a href="vec__f128__ppc_8h.html#afc2ac713dcb43499b47410c02b6c854c">More...</a><br /></td></tr>
<tr class="separator:afc2ac713dcb43499b47410c02b6c854c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:acac5809f5f651e45113de8410664f2c7"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#acac5809f5f651e45113de8410664f2c7">vec_xfer_bin128_2_vui64t</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:acac5809f5f651e45113de8410664f2c7"><td class="mdescLeft"> </td><td class="mdescRight">Transfer function from a __binary128 scalar to a vector long long int. <a href="vec__f128__ppc_8h.html#acac5809f5f651e45113de8410664f2c7">More...</a><br /></td></tr>
<tr class="separator:acac5809f5f651e45113de8410664f2c7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aec6e44a75847d3d3e5611b89eed71c0a"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aec6e44a75847d3d3e5611b89eed71c0a">vec_xfer_bin128_2_vui128t</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:aec6e44a75847d3d3e5611b89eed71c0a"><td class="mdescLeft"> </td><td class="mdescRight">Transfer function from a __binary128 scalar to a vector __int128. <a href="vec__f128__ppc_8h.html#aec6e44a75847d3d3e5611b89eed71c0a">More...</a><br /></td></tr>
<tr class="separator:aec6e44a75847d3d3e5611b89eed71c0a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a047b7dc5b55b2d13e2fd826c63872ea9"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a047b7dc5b55b2d13e2fd826c63872ea9">vec_xfer_vui8t_2_bin128</a> (<a class="el" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> f128)</td></tr>
<tr class="memdesc:a047b7dc5b55b2d13e2fd826c63872ea9"><td class="mdescLeft"> </td><td class="mdescRight">Transfer a vector unsigned char to __binary128 scalar. <a href="vec__f128__ppc_8h.html#a047b7dc5b55b2d13e2fd826c63872ea9">More...</a><br /></td></tr>
<tr class="separator:a047b7dc5b55b2d13e2fd826c63872ea9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3dec5c23a659b2fca1c219fe783f88eb"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a3dec5c23a659b2fca1c219fe783f88eb">vec_xfer_vui16t_2_bin128</a> (<a class="el" href="vec__common__ppc_8h.html#afb47075b07673afbf78f8c60298f3712">vui16_t</a> f128)</td></tr>
<tr class="memdesc:a3dec5c23a659b2fca1c219fe783f88eb"><td class="mdescLeft"> </td><td class="mdescRight">Transfer a vector unsigned short to __binary128 scalar. <a href="vec__f128__ppc_8h.html#a3dec5c23a659b2fca1c219fe783f88eb">More...</a><br /></td></tr>
<tr class="separator:a3dec5c23a659b2fca1c219fe783f88eb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af0596ab318ba6d1ec5e7ed40871255a9"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#af0596ab318ba6d1ec5e7ed40871255a9">vec_xfer_vui32t_2_bin128</a> (<a class="el" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> f128)</td></tr>
<tr class="memdesc:af0596ab318ba6d1ec5e7ed40871255a9"><td class="mdescLeft"> </td><td class="mdescRight">Transfer a vector unsigned int to __binary128 scalar. <a href="vec__f128__ppc_8h.html#af0596ab318ba6d1ec5e7ed40871255a9">More...</a><br /></td></tr>
<tr class="separator:af0596ab318ba6d1ec5e7ed40871255a9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ae8002c29875a226d11ec57a42b5b3955"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#ae8002c29875a226d11ec57a42b5b3955">vec_xfer_vui64t_2_bin128</a> (<a class="el" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> f128)</td></tr>
<tr class="memdesc:ae8002c29875a226d11ec57a42b5b3955"><td class="mdescLeft"> </td><td class="mdescRight">Transfer a vector unsigned long long to __binary128 scalar. <a href="vec__f128__ppc_8h.html#ae8002c29875a226d11ec57a42b5b3955">More...</a><br /></td></tr>
<tr class="separator:ae8002c29875a226d11ec57a42b5b3955"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a91b99b632646aaca91de6834e2b1da26"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a91b99b632646aaca91de6834e2b1da26">vec_xfer_vui128t_2_bin128</a> (<a class="el" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> f128)</td></tr>
<tr class="memdesc:a91b99b632646aaca91de6834e2b1da26"><td class="mdescLeft"> </td><td class="mdescRight">Transfer a vector unsigned __int128 to __binary128 scalar. <a href="vec__f128__ppc_8h.html#a91b99b632646aaca91de6834e2b1da26">More...</a><br /></td></tr>
<tr class="separator:a91b99b632646aaca91de6834e2b1da26"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:add641f5a217eff45f0e836fa98613584"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#add641f5a217eff45f0e836fa98613584">vec_absf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:add641f5a217eff45f0e836fa98613584"><td class="mdescLeft"> </td><td class="mdescRight">Absolute Quad-Precision. <a href="vec__f128__ppc_8h.html#add641f5a217eff45f0e836fa98613584">More...</a><br /></td></tr>
<tr class="separator:add641f5a217eff45f0e836fa98613584"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a946ffd501b32f3ec96563ab101afbfad"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a946ffd501b32f3ec96563ab101afbfad">vec_all_isfinitef128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a946ffd501b32f3ec96563ab101afbfad"><td class="mdescLeft"> </td><td class="mdescRight">Return true if the __float128 value is Finite (Not NaN nor Inf). <a href="vec__f128__ppc_8h.html#a946ffd501b32f3ec96563ab101afbfad">More...</a><br /></td></tr>
<tr class="separator:a946ffd501b32f3ec96563ab101afbfad"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a66fc4e7c94d0b30bb3515931aaf723da"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a66fc4e7c94d0b30bb3515931aaf723da">vec_all_isinff128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a66fc4e7c94d0b30bb3515931aaf723da"><td class="mdescLeft"> </td><td class="mdescRight">Return true if the __float128 value is infinity. <a href="vec__f128__ppc_8h.html#a66fc4e7c94d0b30bb3515931aaf723da">More...</a><br /></td></tr>
<tr class="separator:a66fc4e7c94d0b30bb3515931aaf723da"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af06b73ac57985011c558670adc283e89"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#af06b73ac57985011c558670adc283e89">vec_all_isnanf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:af06b73ac57985011c558670adc283e89"><td class="mdescLeft"> </td><td class="mdescRight">Return true if the __float128 value is Not a Number (NaN). <a href="vec__f128__ppc_8h.html#af06b73ac57985011c558670adc283e89">More...</a><br /></td></tr>
<tr class="separator:af06b73ac57985011c558670adc283e89"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afc830b382bd45dc0ff815024c1bfb26d"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#afc830b382bd45dc0ff815024c1bfb26d">vec_all_isnormalf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:afc830b382bd45dc0ff815024c1bfb26d"><td class="mdescLeft"> </td><td class="mdescRight">Return true if the __float128 value is normal (Not NaN, Inf, denormal, or zero). <a href="vec__f128__ppc_8h.html#afc830b382bd45dc0ff815024c1bfb26d">More...</a><br /></td></tr>
<tr class="separator:afc830b382bd45dc0ff815024c1bfb26d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:adf1a94cccdb3f106a0e6399e2f034718"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#adf1a94cccdb3f106a0e6399e2f034718">vec_all_issubnormalf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:adf1a94cccdb3f106a0e6399e2f034718"><td class="mdescLeft"> </td><td class="mdescRight">Return true if the __float128 value is subnormal (denormal). <a href="vec__f128__ppc_8h.html#adf1a94cccdb3f106a0e6399e2f034718">More...</a><br /></td></tr>
<tr class="separator:adf1a94cccdb3f106a0e6399e2f034718"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2bee3fac5a163513bae170a54ac641ca"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a2bee3fac5a163513bae170a54ac641ca">vec_all_isunorderedf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a2bee3fac5a163513bae170a54ac641ca"><td class="mdescLeft"> </td><td class="mdescRight">Return true if either __float128 value (vra, vrb) is NaN. <a href="vec__f128__ppc_8h.html#a2bee3fac5a163513bae170a54ac641ca">More...</a><br /></td></tr>
<tr class="separator:a2bee3fac5a163513bae170a54ac641ca"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac554a9d0d12fca036772aaaee5908414"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#ac554a9d0d12fca036772aaaee5908414">vec_all_iszerof128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:ac554a9d0d12fca036772aaaee5908414"><td class="mdescLeft"> </td><td class="mdescRight">Return true if the __float128 value is +-0.0. <a href="vec__f128__ppc_8h.html#ac554a9d0d12fca036772aaaee5908414">More...</a><br /></td></tr>
<tr class="separator:ac554a9d0d12fca036772aaaee5908414"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:adfb73eac40698921735bad8ac4ce560e"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#adfb73eac40698921735bad8ac4ce560e">vec_copysignf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128x, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128y)</td></tr>
<tr class="memdesc:adfb73eac40698921735bad8ac4ce560e"><td class="mdescLeft"> </td><td class="mdescRight">Copy the sign bit from f128x and merge with the magnitude from f128y. The merged result is returned as a __float128 value. <a href="vec__f128__ppc_8h.html#adfb73eac40698921735bad8ac4ce560e">More...</a><br /></td></tr>
<tr class="separator:adfb73eac40698921735bad8ac4ce560e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0a30726ccfb216e4d2e1ede3854ab96b"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a0a30726ccfb216e4d2e1ede3854ab96b">vec_const_huge_valf128</a> ()</td></tr>
<tr class="memdesc:a0a30726ccfb216e4d2e1ede3854ab96b"><td class="mdescLeft"> </td><td class="mdescRight">return a positive infinity. <a href="vec__f128__ppc_8h.html#a0a30726ccfb216e4d2e1ede3854ab96b">More...</a><br /></td></tr>
<tr class="separator:a0a30726ccfb216e4d2e1ede3854ab96b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9c68f73f69c4776bb054d42915e7103d"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a9c68f73f69c4776bb054d42915e7103d">vec_const_inff128</a> ()</td></tr>
<tr class="memdesc:a9c68f73f69c4776bb054d42915e7103d"><td class="mdescLeft"> </td><td class="mdescRight">return a positive infinity. <a href="vec__f128__ppc_8h.html#a9c68f73f69c4776bb054d42915e7103d">More...</a><br /></td></tr>
<tr class="separator:a9c68f73f69c4776bb054d42915e7103d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af7fb1013dfcf633156cd7f855a11fb56"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#af7fb1013dfcf633156cd7f855a11fb56">vec_const_nanf128</a> ()</td></tr>
<tr class="memdesc:af7fb1013dfcf633156cd7f855a11fb56"><td class="mdescLeft"> </td><td class="mdescRight">return a quiet NaN. <a href="vec__f128__ppc_8h.html#af7fb1013dfcf633156cd7f855a11fb56">More...</a><br /></td></tr>
<tr class="separator:af7fb1013dfcf633156cd7f855a11fb56"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aac806c62ebaae6ab8faca87794cb917c"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aac806c62ebaae6ab8faca87794cb917c">vec_const_nansf128</a> ()</td></tr>
<tr class="memdesc:aac806c62ebaae6ab8faca87794cb917c"><td class="mdescLeft"> </td><td class="mdescRight">return a signaling NaN. <a href="vec__f128__ppc_8h.html#aac806c62ebaae6ab8faca87794cb917c">More...</a><br /></td></tr>
<tr class="separator:aac806c62ebaae6ab8faca87794cb917c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aec73dba497304699389a168256f32d29"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aec73dba497304699389a168256f32d29">vec_cmpeqtoqp</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:aec73dba497304699389a168256f32d29"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Equal (Total-order) Quad-Precision. <a href="vec__f128__ppc_8h.html#aec73dba497304699389a168256f32d29">More...</a><br /></td></tr>
<tr class="separator:aec73dba497304699389a168256f32d29"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a83177380e5feaacb1da72c99df1c6d82"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a83177380e5feaacb1da72c99df1c6d82">vec_cmpequzqp</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a83177380e5feaacb1da72c99df1c6d82"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Equal (Zero-unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a83177380e5feaacb1da72c99df1c6d82">More...</a><br /></td></tr>
<tr class="separator:a83177380e5feaacb1da72c99df1c6d82"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7e3f85b4c3fe43ae58df0c72d1f29920"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a7e3f85b4c3fe43ae58df0c72d1f29920">vec_cmpequqp</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a7e3f85b4c3fe43ae58df0c72d1f29920"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Equal (Unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a7e3f85b4c3fe43ae58df0c72d1f29920">More...</a><br /></td></tr>
<tr class="separator:a7e3f85b4c3fe43ae58df0c72d1f29920"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa40f7a997a4c92eb55203444434c070e"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aa40f7a997a4c92eb55203444434c070e">vec_cmpgetoqp</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:aa40f7a997a4c92eb55203444434c070e"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Greater Than or Equal (Total-order) Quad-Precision. <a href="vec__f128__ppc_8h.html#aa40f7a997a4c92eb55203444434c070e">More...</a><br /></td></tr>
<tr class="separator:aa40f7a997a4c92eb55203444434c070e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a6b31351604fbca85ace1c1efc8bd6506"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a6b31351604fbca85ace1c1efc8bd6506">vec_cmpgeuzqp</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a6b31351604fbca85ace1c1efc8bd6506"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Greater Than Or Equal (Zero-unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a6b31351604fbca85ace1c1efc8bd6506">More...</a><br /></td></tr>
<tr class="separator:a6b31351604fbca85ace1c1efc8bd6506"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a870bc0f51bb3931039fec799a7c3605a"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a870bc0f51bb3931039fec799a7c3605a">vec_cmpgeuqp</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a870bc0f51bb3931039fec799a7c3605a"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Greater Than or Equal (Unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a870bc0f51bb3931039fec799a7c3605a">More...</a><br /></td></tr>
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<tr class="memdesc:ae320639a93f8bc42359d9214a5e9c17e"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Greater Than (Total-order) Quad-Precision. <a href="vec__f128__ppc_8h.html#ae320639a93f8bc42359d9214a5e9c17e">More...</a><br /></td></tr>
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<tr class="memdesc:a4bd8774bd68a914ac0fe3f66d16a8965"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Greater Than (Unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a4bd8774bd68a914ac0fe3f66d16a8965">More...</a><br /></td></tr>
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<tr class="memdesc:a2034138934ee70e2ed25978ecb18ebc0"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Less Than or Equal (Total-order) Quad-Precision. <a href="vec__f128__ppc_8h.html#a2034138934ee70e2ed25978ecb18ebc0">More...</a><br /></td></tr>
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<tr class="memdesc:ae776b348d6c4c4a45966b451aa72072c"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Less Than or Equal (Zero-unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#ae776b348d6c4c4a45966b451aa72072c">More...</a><br /></td></tr>
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<tr class="memdesc:a4a72e3eb8f3d96e537e940cc7583b3c7"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Less Than or Equal (Unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a4a72e3eb8f3d96e537e940cc7583b3c7">More...</a><br /></td></tr>
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<tr class="memdesc:a82c672a1a0bcd3005acdfff33e70e782"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Less Than (Total-order) Quad-Precision. <a href="vec__f128__ppc_8h.html#a82c672a1a0bcd3005acdfff33e70e782">More...</a><br /></td></tr>
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<tr class="memdesc:a1e3242d44d78984694295087f9f415e8"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Less Than (Zero-unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a1e3242d44d78984694295087f9f415e8">More...</a><br /></td></tr>
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<tr class="memdesc:a388307f4693587b9e49148fbe95d8da5"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Less Than (Unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a388307f4693587b9e49148fbe95d8da5">More...</a><br /></td></tr>
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<tr class="memdesc:aa2a23cbeeb063d30316ab3e7bdd77fd7"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Not Equal (Total-order) Quad-Precision. <a href="vec__f128__ppc_8h.html#aa2a23cbeeb063d30316ab3e7bdd77fd7">More...</a><br /></td></tr>
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<tr class="memdesc:a4ffa4be24c8714347ded9340de33e999"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Not Equal (Zero-unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a4ffa4be24c8714347ded9340de33e999">More...</a><br /></td></tr>
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<tr class="memdesc:ab3e270eb83aa8d90a2459b0097fec944"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Not Equal (Unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#ab3e270eb83aa8d90a2459b0097fec944">More...</a><br /></td></tr>
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<tr class="memitem:a44c233f656fb0ef554dfbdfb23e66954"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a44c233f656fb0ef554dfbdfb23e66954">vec_cmpqp_all_toeq</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a44c233f656fb0ef554dfbdfb23e66954"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Equal (Total-order) Quad-Precision. <a href="vec__f128__ppc_8h.html#a44c233f656fb0ef554dfbdfb23e66954">More...</a><br /></td></tr>
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<tr class="memitem:a4c7d9eb6f3ee5d504bddd9f4b9171bfd"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a4c7d9eb6f3ee5d504bddd9f4b9171bfd">vec_cmpqp_all_uzeq</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a4c7d9eb6f3ee5d504bddd9f4b9171bfd"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Equal (Zero-unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a4c7d9eb6f3ee5d504bddd9f4b9171bfd">More...</a><br /></td></tr>
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<tr class="memitem:ab50ec5ca14b23861c520e99f9b24a11f"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#ab50ec5ca14b23861c520e99f9b24a11f">vec_cmpqp_all_eq</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:ab50ec5ca14b23861c520e99f9b24a11f"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Equal (Unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#ab50ec5ca14b23861c520e99f9b24a11f">More...</a><br /></td></tr>
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<tr class="memitem:a9a4f2f83695c9980679e8a2488ed2c55"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a9a4f2f83695c9980679e8a2488ed2c55">vec_cmpqp_all_toge</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a9a4f2f83695c9980679e8a2488ed2c55"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Greater Than Or Equal (Total-order) Quad-Precision. <a href="vec__f128__ppc_8h.html#a9a4f2f83695c9980679e8a2488ed2c55">More...</a><br /></td></tr>
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<tr class="memitem:a59a13069849f5ac559db634deab32d0e"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a59a13069849f5ac559db634deab32d0e">vec_cmpqp_all_uzge</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a59a13069849f5ac559db634deab32d0e"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Greater Than Or Equal (Zero-unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a59a13069849f5ac559db634deab32d0e">More...</a><br /></td></tr>
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<tr class="memitem:a01aef626eb6cd826f5874f3324dd7217"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a01aef626eb6cd826f5874f3324dd7217">vec_cmpqp_all_ge</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a01aef626eb6cd826f5874f3324dd7217"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Greater Than Or Equal (Unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a01aef626eb6cd826f5874f3324dd7217">More...</a><br /></td></tr>
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<tr class="memitem:a926a5e7b9a23e7464d70d9fa6ae49dda"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a926a5e7b9a23e7464d70d9fa6ae49dda">vec_cmpqp_all_togt</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a926a5e7b9a23e7464d70d9fa6ae49dda"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Greater Than (Total-order) Quad-Precision. <a href="vec__f128__ppc_8h.html#a926a5e7b9a23e7464d70d9fa6ae49dda">More...</a><br /></td></tr>
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<tr class="memitem:ab0dcb860a9015e36ade2d6a9fac55c62"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#ab0dcb860a9015e36ade2d6a9fac55c62">vec_cmpqp_all_uzgt</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:ab0dcb860a9015e36ade2d6a9fac55c62"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Greater Than (Zero-unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#ab0dcb860a9015e36ade2d6a9fac55c62">More...</a><br /></td></tr>
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<tr class="memitem:a253c27dd7f4fe852a4f0c6dce45d886b"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a253c27dd7f4fe852a4f0c6dce45d886b">vec_cmpqp_all_gt</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a253c27dd7f4fe852a4f0c6dce45d886b"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Greater Than (Unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a253c27dd7f4fe852a4f0c6dce45d886b">More...</a><br /></td></tr>
<tr class="separator:a253c27dd7f4fe852a4f0c6dce45d886b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8171c3fa6a0ecdf7b19be3df8227cbf6"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a8171c3fa6a0ecdf7b19be3df8227cbf6">vec_cmpqp_all_tole</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a8171c3fa6a0ecdf7b19be3df8227cbf6"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare All Less Than Or Equal (Total-order) Quad-Precision. <a href="vec__f128__ppc_8h.html#a8171c3fa6a0ecdf7b19be3df8227cbf6">More...</a><br /></td></tr>
<tr class="separator:a8171c3fa6a0ecdf7b19be3df8227cbf6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a75d444218effcb971289efb1e02a3dc9"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a75d444218effcb971289efb1e02a3dc9">vec_cmpqp_all_uzle</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a75d444218effcb971289efb1e02a3dc9"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Less Than Or Equal (Zero-unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a75d444218effcb971289efb1e02a3dc9">More...</a><br /></td></tr>
<tr class="separator:a75d444218effcb971289efb1e02a3dc9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a19dca4ec505a30c52361dff6300fdba7"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a19dca4ec505a30c52361dff6300fdba7">vec_cmpqp_all_le</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a19dca4ec505a30c52361dff6300fdba7"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Less Than Or Equal (Unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a19dca4ec505a30c52361dff6300fdba7">More...</a><br /></td></tr>
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<tr class="memitem:a9d466774a32ef558f6e3ea64dd6b3cdd"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a9d466774a32ef558f6e3ea64dd6b3cdd">vec_cmpqp_all_tolt</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a9d466774a32ef558f6e3ea64dd6b3cdd"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare All Less Than (Total-order) Quad-Precision. <a href="vec__f128__ppc_8h.html#a9d466774a32ef558f6e3ea64dd6b3cdd">More...</a><br /></td></tr>
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<tr class="memitem:a95dde3d0847b947b1f422afef46fbfc6"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a95dde3d0847b947b1f422afef46fbfc6">vec_cmpqp_all_uzlt</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a95dde3d0847b947b1f422afef46fbfc6"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Less Than (Zero-unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a95dde3d0847b947b1f422afef46fbfc6">More...</a><br /></td></tr>
<tr class="separator:a95dde3d0847b947b1f422afef46fbfc6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a630f6cef8a6cdcc6dd22d3c1ece138b7"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a630f6cef8a6cdcc6dd22d3c1ece138b7">vec_cmpqp_all_lt</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a630f6cef8a6cdcc6dd22d3c1ece138b7"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Less Than (Unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a630f6cef8a6cdcc6dd22d3c1ece138b7">More...</a><br /></td></tr>
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<tr class="memitem:ad8d272e77ab3c69808ad3efac20afb36"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#ad8d272e77ab3c69808ad3efac20afb36">vec_cmpqp_all_tone</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:ad8d272e77ab3c69808ad3efac20afb36"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Not-Equal (Total-order) Quad-Precision. <a href="vec__f128__ppc_8h.html#ad8d272e77ab3c69808ad3efac20afb36">More...</a><br /></td></tr>
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<tr class="memitem:aa147fd8c1d3da47a2786b6b745a9e1a6"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aa147fd8c1d3da47a2786b6b745a9e1a6">vec_cmpqp_all_uzne</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:aa147fd8c1d3da47a2786b6b745a9e1a6"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Not-Equal (Zero-unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#aa147fd8c1d3da47a2786b6b745a9e1a6">More...</a><br /></td></tr>
<tr class="separator:aa147fd8c1d3da47a2786b6b745a9e1a6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3d858ca0228e20b1e7f3bec686021fb6"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a3d858ca0228e20b1e7f3bec686021fb6">vec_cmpqp_all_ne</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a3d858ca0228e20b1e7f3bec686021fb6"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare all Not-Equal (Unordered) Quad-Precision. <a href="vec__f128__ppc_8h.html#a3d858ca0228e20b1e7f3bec686021fb6">More...</a><br /></td></tr>
<tr class="separator:a3d858ca0228e20b1e7f3bec686021fb6"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1e6c52eb3208f4d9ed851ee48f773d68"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a1e6c52eb3208f4d9ed851ee48f773d68">vec_cmpqp_exp_eq</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a1e6c52eb3208f4d9ed851ee48f773d68"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Quad-Precision Exponents for Equal. <a href="vec__f128__ppc_8h.html#a1e6c52eb3208f4d9ed851ee48f773d68">More...</a><br /></td></tr>
<tr class="separator:a1e6c52eb3208f4d9ed851ee48f773d68"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abf2d90d67cb3f605fbc9598f133b0305"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#abf2d90d67cb3f605fbc9598f133b0305">vec_cmpqp_exp_gt</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:abf2d90d67cb3f605fbc9598f133b0305"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Exponents Quad-Precision for Greater Than. <a href="vec__f128__ppc_8h.html#abf2d90d67cb3f605fbc9598f133b0305">More...</a><br /></td></tr>
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<tr class="memitem:a3eb9b92be998695424107de6a60890a8"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a3eb9b92be998695424107de6a60890a8">vec_cmpqp_exp_lt</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a3eb9b92be998695424107de6a60890a8"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Exponents Quad-Precision for Less Than. <a href="vec__f128__ppc_8h.html#a3eb9b92be998695424107de6a60890a8">More...</a><br /></td></tr>
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<tr class="memitem:a3014214c103453a34372cc52e6d79073"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a3014214c103453a34372cc52e6d79073">vec_cmpqp_exp_unordered</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a3014214c103453a34372cc52e6d79073"><td class="mdescLeft"> </td><td class="mdescRight">Vector Compare Exponents Quad-Precision for Unordered. <a href="vec__f128__ppc_8h.html#a3014214c103453a34372cc52e6d79073">More...</a><br /></td></tr>
<tr class="separator:a3014214c103453a34372cc52e6d79073"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ad1668ff13922ca04059f1844a7a1464f"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#ad1668ff13922ca04059f1844a7a1464f">vec_isfinitef128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:ad1668ff13922ca04059f1844a7a1464f"><td class="mdescLeft"> </td><td class="mdescRight">Return 128-bit vector boolean true if the __float128 value is Finite (Not NaN nor Inf). <a href="vec__f128__ppc_8h.html#ad1668ff13922ca04059f1844a7a1464f">More...</a><br /></td></tr>
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<tr class="memitem:aebd9706acb775392282cfe4d4e3a03aa"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aebd9706acb775392282cfe4d4e3a03aa">vec_isinf_signf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:aebd9706acb775392282cfe4d4e3a03aa"><td class="mdescLeft"> </td><td class="mdescRight">Return true (nonzero) value if the __float128 value is infinity. If infinity, indicate the sign as +1 for positive infinity and -1 for negative infinity. <a href="vec__f128__ppc_8h.html#aebd9706acb775392282cfe4d4e3a03aa">More...</a><br /></td></tr>
<tr class="separator:aebd9706acb775392282cfe4d4e3a03aa"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a94f9c7429c2ebd9b9f32ad6e98689ebb"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a94f9c7429c2ebd9b9f32ad6e98689ebb">vec_isinff128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a94f9c7429c2ebd9b9f32ad6e98689ebb"><td class="mdescLeft"> </td><td class="mdescRight">Return a 128-bit vector boolean true if the __float128 value is infinity. <a href="vec__f128__ppc_8h.html#a94f9c7429c2ebd9b9f32ad6e98689ebb">More...</a><br /></td></tr>
<tr class="separator:a94f9c7429c2ebd9b9f32ad6e98689ebb"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a11c410994f958a6b4ac9583878a55a72"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a11c410994f958a6b4ac9583878a55a72">vec_isnanf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a11c410994f958a6b4ac9583878a55a72"><td class="mdescLeft"> </td><td class="mdescRight">Return 128-bit vector boolean true if the __float128 value is Not a Number (NaN). <a href="vec__f128__ppc_8h.html#a11c410994f958a6b4ac9583878a55a72">More...</a><br /></td></tr>
<tr class="separator:a11c410994f958a6b4ac9583878a55a72"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa25185c83b69f6af3f3d9399199c8a57"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aa25185c83b69f6af3f3d9399199c8a57">vec_isnormalf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:aa25185c83b69f6af3f3d9399199c8a57"><td class="mdescLeft"> </td><td class="mdescRight">Return 128-bit vector boolean true if the __float128 value is normal (Not NaN, Inf, denormal, or zero). <a href="vec__f128__ppc_8h.html#aa25185c83b69f6af3f3d9399199c8a57">More...</a><br /></td></tr>
<tr class="separator:aa25185c83b69f6af3f3d9399199c8a57"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9670e4655a9c7888c80343780cd7abf9"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a9670e4655a9c7888c80343780cd7abf9">vec_issubnormalf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a9670e4655a9c7888c80343780cd7abf9"><td class="mdescLeft"> </td><td class="mdescRight">Return 128-bit vector boolean true value, if the __float128 value is subnormal (denormal). <a href="vec__f128__ppc_8h.html#a9670e4655a9c7888c80343780cd7abf9">More...</a><br /></td></tr>
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<tr class="memitem:aec9148af78b075f253c9848945df6135"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aec9148af78b075f253c9848945df6135">vec_isunorderedf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:aec9148af78b075f253c9848945df6135"><td class="mdescLeft"> </td><td class="mdescRight">Return 128-bit vector boolean true value, if either __float128 value (vra, vrb) is NaN. <a href="vec__f128__ppc_8h.html#aec9148af78b075f253c9848945df6135">More...</a><br /></td></tr>
<tr class="separator:aec9148af78b075f253c9848945df6135"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a598a822d22b02ba0d2c2a1095a4e700d"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a598a822d22b02ba0d2c2a1095a4e700d">vec_iszerof128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a598a822d22b02ba0d2c2a1095a4e700d"><td class="mdescLeft"> </td><td class="mdescRight">Return 128-bit vector boolean true value, if the value that is +-0.0. <a href="vec__f128__ppc_8h.html#a598a822d22b02ba0d2c2a1095a4e700d">More...</a><br /></td></tr>
<tr class="separator:a598a822d22b02ba0d2c2a1095a4e700d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7c2297dc22a6a3120491e1721648c0e7"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a7c2297dc22a6a3120491e1721648c0e7">vec_nabsf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a7c2297dc22a6a3120491e1721648c0e7"><td class="mdescLeft"> </td><td class="mdescRight">Negative Absolute value Quad-Precision. <a href="vec__f128__ppc_8h.html#a7c2297dc22a6a3120491e1721648c0e7">More...</a><br /></td></tr>
<tr class="separator:a7c2297dc22a6a3120491e1721648c0e7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3323b6fb0b379a21f3dd70f7f204bd2a"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a3323b6fb0b379a21f3dd70f7f204bd2a">vec_negf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a3323b6fb0b379a21f3dd70f7f204bd2a"><td class="mdescLeft"> </td><td class="mdescRight">Negate the sign bit of a __float128 input and return the resulting __float128 value. <a href="vec__f128__ppc_8h.html#a3323b6fb0b379a21f3dd70f7f204bd2a">More...</a><br /></td></tr>
<tr class="separator:a3323b6fb0b379a21f3dd70f7f204bd2a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a47637906e95a7c94cffc093bc2e57dbf"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a47637906e95a7c94cffc093bc2e57dbf">vec_self128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb, <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> mask)</td></tr>
<tr class="memdesc:a47637906e95a7c94cffc093bc2e57dbf"><td class="mdescLeft"> </td><td class="mdescRight">Select and Transfer from one of two __binary128 scalars under a 128-bit mask. The result is a __binary128 of the selected value. <a href="vec__f128__ppc_8h.html#a47637906e95a7c94cffc093bc2e57dbf">More...</a><br /></td></tr>
<tr class="separator:a47637906e95a7c94cffc093bc2e57dbf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4d5b388cfc9af26418bdd4ec8e4e6f73"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a4d5b388cfc9af26418bdd4ec8e4e6f73">vec_setb_qp</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a4d5b388cfc9af26418bdd4ec8e4e6f73"><td class="mdescLeft"> </td><td class="mdescRight">Vector Set Bool from Quadword Floating-point. <a href="vec__f128__ppc_8h.html#a4d5b388cfc9af26418bdd4ec8e4e6f73">More...</a><br /></td></tr>
<tr class="separator:a4d5b388cfc9af26418bdd4ec8e4e6f73"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4ca7749d334c2a2c17a4d2a98b5bf755"><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a4ca7749d334c2a2c17a4d2a98b5bf755">vec_signbitf128</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a4ca7749d334c2a2c17a4d2a98b5bf755"><td class="mdescLeft"> </td><td class="mdescRight">Return int boolean true if the __float128 value is negative (sign bit is '1'). <a href="vec__f128__ppc_8h.html#a4ca7749d334c2a2c17a4d2a98b5bf755">More...</a><br /></td></tr>
<tr class="separator:a4ca7749d334c2a2c17a4d2a98b5bf755"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa3bff7954c22b5d85f976f046290f37b"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aa3bff7954c22b5d85f976f046290f37b">vec_xsaddqpo</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:aa3bff7954c22b5d85f976f046290f37b"><td class="mdescLeft"> </td><td class="mdescRight">VSX Scalar Add Quad-Precision using round to Odd. <a href="vec__f128__ppc_8h.html#aa3bff7954c22b5d85f976f046290f37b">More...</a><br /></td></tr>
<tr class="separator:aa3bff7954c22b5d85f976f046290f37b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5f8e71a4362e87704c5172b751ecbc6f"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a5f8e71a4362e87704c5172b751ecbc6f">vec_xssubqpo</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a5f8e71a4362e87704c5172b751ecbc6f"><td class="mdescLeft"> </td><td class="mdescRight">VSX Scalar Subtract Quad-Precision using round to Odd. <a href="vec__f128__ppc_8h.html#a5f8e71a4362e87704c5172b751ecbc6f">More...</a><br /></td></tr>
<tr class="separator:a5f8e71a4362e87704c5172b751ecbc6f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1a8ceb0eb2c47892371a12502d14f170"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a1a8ceb0eb2c47892371a12502d14f170">vec_xscvdpqp</a> (<a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> f64)</td></tr>
<tr class="memdesc:a1a8ceb0eb2c47892371a12502d14f170"><td class="mdescLeft"> </td><td class="mdescRight">VSX Scalar Convert Double-Precision to Quad-Precision format. <a href="vec__f128__ppc_8h.html#a1a8ceb0eb2c47892371a12502d14f170">More...</a><br /></td></tr>
<tr class="separator:a1a8ceb0eb2c47892371a12502d14f170"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5e3c778a7c90b6e6a2d89cd5a1012061"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#ae5cccc22e004bddbb80a51117c448675">vf64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a5e3c778a7c90b6e6a2d89cd5a1012061">vec_xscvqpdpo</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a5e3c778a7c90b6e6a2d89cd5a1012061"><td class="mdescLeft"> </td><td class="mdescRight">VSX Scalar Convert with round Quad-Precision to Double-Precision (using round to odd). <a href="vec__f128__ppc_8h.html#a5e3c778a7c90b6e6a2d89cd5a1012061">More...</a><br /></td></tr>
<tr class="separator:a5e3c778a7c90b6e6a2d89cd5a1012061"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a73ad56c509ea22f26fb2d47217bc5e51"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a73ad56c509ea22f26fb2d47217bc5e51">vec_xscvqpudz</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a73ad56c509ea22f26fb2d47217bc5e51"><td class="mdescLeft"> </td><td class="mdescRight">VSX Scalar Convert with round to zero Quad-Precision to Unsigned doubleword. <a href="vec__f128__ppc_8h.html#a73ad56c509ea22f26fb2d47217bc5e51">More...</a><br /></td></tr>
<tr class="separator:a73ad56c509ea22f26fb2d47217bc5e51"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aaf9d4ad5a60e9ffaa0ca16d29f90c092"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#aaf9d4ad5a60e9ffaa0ca16d29f90c092">vec_xscvqpuqz</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:aaf9d4ad5a60e9ffaa0ca16d29f90c092"><td class="mdescLeft"> </td><td class="mdescRight">VSX Scalar Convert with round to zero Quad-Precision to Unsigned Quadword. <a href="vec__f128__ppc_8h.html#aaf9d4ad5a60e9ffaa0ca16d29f90c092">More...</a><br /></td></tr>
<tr class="separator:aaf9d4ad5a60e9ffaa0ca16d29f90c092"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:acc58cb3be351ea2bf163aeb8dbb5709c"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#acc58cb3be351ea2bf163aeb8dbb5709c">vec_xscvsdqp</a> (<a class="el" href="vec__common__ppc_8h.html#a0c3abdfe41178c152e0a2130c20476ff">vi64_t</a> int64)</td></tr>
<tr class="memdesc:acc58cb3be351ea2bf163aeb8dbb5709c"><td class="mdescLeft"> </td><td class="mdescRight">VSX Scalar Convert Signed-Doubleword to Quad-Precision format. <a href="vec__f128__ppc_8h.html#acc58cb3be351ea2bf163aeb8dbb5709c">More...</a><br /></td></tr>
<tr class="separator:acc58cb3be351ea2bf163aeb8dbb5709c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1eadadc05fe1873deadaef16926f6c86"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a1eadadc05fe1873deadaef16926f6c86">vec_xscvudqp</a> (<a class="el" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> int64)</td></tr>
<tr class="memdesc:a1eadadc05fe1873deadaef16926f6c86"><td class="mdescLeft"> </td><td class="mdescRight">VSX Scalar Convert Unsigned-Doubleword to Quad-Precision format. <a href="vec__f128__ppc_8h.html#a1eadadc05fe1873deadaef16926f6c86">More...</a><br /></td></tr>
<tr class="separator:a1eadadc05fe1873deadaef16926f6c86"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a27bfd64d7eefd8e84619950f19f827ba"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a27bfd64d7eefd8e84619950f19f827ba">vec_xscvsqqp</a> (<a class="el" href="vec__common__ppc_8h.html#a3b2bbf9f23490ccca3bdc08bc1dc7831">vi128_t</a> int128)</td></tr>
<tr class="memdesc:a27bfd64d7eefd8e84619950f19f827ba"><td class="mdescLeft"> </td><td class="mdescRight">VSX Scalar Convert Signed-Quadword to Quad-Precision format. <a href="vec__f128__ppc_8h.html#a27bfd64d7eefd8e84619950f19f827ba">More...</a><br /></td></tr>
<tr class="separator:a27bfd64d7eefd8e84619950f19f827ba"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a24b1f22552fd177d10af1dbc0f43d5f8"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a24b1f22552fd177d10af1dbc0f43d5f8">vec_xscvuqqp</a> (<a class="el" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> int128)</td></tr>
<tr class="memdesc:a24b1f22552fd177d10af1dbc0f43d5f8"><td class="mdescLeft"> </td><td class="mdescRight">VSX Scalar Convert Unsigned-Quadword to Quad-Precision format. <a href="vec__f128__ppc_8h.html#a24b1f22552fd177d10af1dbc0f43d5f8">More...</a><br /></td></tr>
<tr class="separator:a24b1f22552fd177d10af1dbc0f43d5f8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af62c779fc5de06a954a55d9c0ddd3baf"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#af62c779fc5de06a954a55d9c0ddd3baf">vec_xsmulqpo</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:af62c779fc5de06a954a55d9c0ddd3baf"><td class="mdescLeft"> </td><td class="mdescRight">VSX Scalar Multiply Quad-Precision using round to Odd. <a href="vec__f128__ppc_8h.html#af62c779fc5de06a954a55d9c0ddd3baf">More...</a><br /></td></tr>
<tr class="separator:af62c779fc5de06a954a55d9c0ddd3baf"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af95c675ceebc0627c777d2c7e2daef0b"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#af95c675ceebc0627c777d2c7e2daef0b">vec_xsiexpqp</a> (<a class="el" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> sig, <a class="el" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> exp)</td></tr>
<tr class="memdesc:af95c675ceebc0627c777d2c7e2daef0b"><td class="mdescLeft"> </td><td class="mdescRight">Scalar Insert Exponent Quad-Precision. <a href="vec__f128__ppc_8h.html#af95c675ceebc0627c777d2c7e2daef0b">More...</a><br /></td></tr>
<tr class="separator:af95c675ceebc0627c777d2c7e2daef0b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3d78e42d9cc58491fa46149bf5798167"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a3d78e42d9cc58491fa46149bf5798167">vec_xsxexpqp</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:a3d78e42d9cc58491fa46149bf5798167"><td class="mdescLeft"> </td><td class="mdescRight">Scalar Extract Exponent Quad-Precision. <a href="vec__f128__ppc_8h.html#a3d78e42d9cc58491fa46149bf5798167">More...</a><br /></td></tr>
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<tr class="memitem:ab1eb10beac182e936d7e49d491c34fe0"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#ab1eb10beac182e936d7e49d491c34fe0">vec_xsxsigqp</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</td></tr>
<tr class="memdesc:ab1eb10beac182e936d7e49d491c34fe0"><td class="mdescLeft"> </td><td class="mdescRight">Scalar Extract Significand Quad-Precision. <a href="vec__f128__ppc_8h.html#ab1eb10beac182e936d7e49d491c34fe0">More...</a><br /></td></tr>
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<tr class="memitem:a93a77b974dcb698d916828f5986ea9cd"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="vec__f128__ppc_8h.html#a93a77b974dcb698d916828f5986ea9cd">vec_xxxexpqpp</a> (<a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfa, <a class="el" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> vfb)</td></tr>
<tr class="memdesc:a93a77b974dcb698d916828f5986ea9cd"><td class="mdescLeft"> </td><td class="mdescRight">Vector Extract Exponent Quad-Precision Pair. <a href="vec__f128__ppc_8h.html#a93a77b974dcb698d916828f5986ea9cd">More...</a><br /></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Header package containing a collection of 128-bit SIMD operations over Quad-Precision floating point elements. </p>
<p>PowerISA 3.0B added Quad-Precision floating point type and operations to the Vector-Scalar Extension (VSX) facility. The first hardware implementation is available in POWER9.</p>
<p>PowerISA 3.1 added new min/max/compare Quad-Precision operations. Also added new quadword (128-bit) integer operations including converts between quadword integer and Quad-Precision floating point. The first hardware implementation is available in POWER10.</p>
<p>While all Quad-Precision operations are on 128-bit vector registers, they are defined as scalars in the PowerISA. The OpenPOWER ABI also treats the __float128 type as scalar that just happens to use vector registers for parameter passing and operations. As such no operations using __float128 (_Float128, or __ieee128) as parameter or return value are defined as vector built-ins in the ABI or <altivec.h>.</p>
<dl class="section note"><dt>Note</dt><dd>GCC 8.2 does document some built-ins, using the <em>scalar</em> prefix (scalar_extract_exp, scalar_extract_sig, scalar_test_data_class), that do accept the __ieee128 type. This work seems to be incomplete as scalar_exp_cmp_* for the __ieee128 type are not present. GCC 7.3 defines vector and scalar forms of the extract/insert_exp for float and double but not for __ieee128. These built-ins are not defined in GCC 6.4. See <a href="https://gcc.gnu.org/onlinedocs/">compiler documentation</a>. These are useful operations and can be implemented in a few vector logical instructions for earlier machines. So it seems reasonable to add these to pveclib for both vector and scalar forms.</dd></dl>
<p>Quad-Precision is not supported in hardware until POWER9. However the compiler and runtime supports the __float128 type and arithmetic operations via soft-float emulation for earlier processors. The soft-float implementation follows the ABI and passes __float128 parameters and return values in vector registers.</p>
<dl class="section note"><dt>Note</dt><dd>The performance of the libgcc soft-float (KF Mode) runtime for __float128 varies between releases of GCC. Some GCC versions introduced a bug that miss-compiled the transfer of __float128 parameters to GPR pairs as required for generic soft-float implementation. For POWER8 this results in a significant performance hit.</dd></dl>
<p>The PowerISA 3.0 also defines a number of useful quad-precision operations using the "round-to-odd" override. This is useful when the results of quad-precision arithmetic must be rounded to a shorter precision while avoiding double rounding. Recent GCC compilers support these operations as built-ins for the POWER9 target, but they not supported by the C language or GCC runtime library. This means that round-to-odd is not easily available to libraries that need to support IEEE-128 on POWER8. Again it may be reasonable to add these to pveclib.</p>
<dl class="section note"><dt>Note</dt><dd>See <a href="https://www.exploringbinary.com/gcc-avoids-double-rounding-errors-with-round-to-odd/">GCC Avoids Double Rounding Errors With Round-To-Odd</a></dd></dl>
<p>Another issue is the performance of GCC soft-float runtime for IEEE-128 (KF mode). There seem to be a number of issues with code generation for transfers from __float128 to 64-bit integer GPRs. This is required to match the ABI (vector) parameters to the soft-float runtime using integer scalars. For POWER8 targets the GCC compiler generates store vector followed by two load doubleword instructions. This generates high frequencies of load-hit-store rejects at runtime. It also looks like there is significant instruction latency associated with the XER carry bit required for extended (128-bit) integer arithmetic. </p><dl class="section note"><dt>Note</dt><dd>The first issue (parameter store reload) is a compiler bug. The second issue is an attribute of the hardware implementation and associate trade-offs. Both of these issues can be avoided by providing a soft-float implementation for __float128 using VSX vector 128-bit arithmetic and logical operations.</dd></dl>
<p>For the QP operations that have libgcc implementations and we have corresponding PVECLIB implementations we can do direct performance comparisons. So far micro-benchmarks show a significant performance gain for the PVECLIB vector implementations vs the GCC KF mode runtime.</p>
<table class="markdownTable">
<tr class="markdownTableHead">
<th class="markdownTableHeadRight">Power8 QP </th><th class="markdownTableHeadCenter">cmpqp </th><th class="markdownTableHeadCenter">cvtdpqp </th><th class="markdownTableHeadCenter">cvtqpdp </th><th class="markdownTableHeadCenter">cvtuqqp </th><th class="markdownTableHeadCenter">cvtqpuq </th><th class="markdownTableHeadCenter">mulqp </th><th class="markdownTableHeadLeft">addqp </th></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyRight">%improvement </td><td class="markdownTableBodyCenter">22.4 </td><td class="markdownTableBodyCenter">60.7 </td><td class="markdownTableBodyCenter">46.2* </td><td class="markdownTableBodyCenter">28.9 </td><td class="markdownTableBodyCenter">72.4 </td><td class="markdownTableBodyCenter">1.8* </td><td class="markdownTableBodyLeft">10.1* </td></tr>
</table>
<dl class="section note"><dt>Note</dt><dd>These micro-benchmarks and others are included in src/testsuite. Specifically files vec_perf_f128.c and vec_f128_dummy.c. Make check will compile the appropriate files and link them into the pveclib_perf executable. Items marked with "*" compare the pveclib round-to-odd implementation to the soft-float default rounding mode. The libgcc soft-float runtime does not implement round-to-odd.</dd></dl>
<p>There are number of __float128 operations that should generate a single instruction for POWER9 and few (less than 10) instructions for POWER8. This includes all of the __float128 classification functions (isnormal/subnormal/finite/inf/nan/zero). Unfortunately for POWER8 the compilers will generate calls to the GCC runtime (__unordkf2, __gekf2, ...) for these functions. In many cases the code size generated for the runtime calls far exceeds any in-line VSX code PVECLIB will generate.</p>
<p>So it is not unreasonable for this header to provide vector forms of the __float128 classification functions (isnormal/subnormal/finite/inf/nan/zero). It is little additional effort to include the sign bit manipulation operations (copysign, abs, nabs, and neg).</p>
<p>These functions can be implemented directly using (one or more) POWER9 instructions, or a few vector logical and integer compare instructions for POWER7/8. Each is comfortably small enough to be in-lined and inherently faster than the equivalent POSIX or compiler built-in runtime functions. Performing these operations in-line and directly in vector registers (VRs) avoids call/return and VR <-> GPR transfer overhead. It also seems reasonable to provide Quad-Precision extract/insert exponent/significand and compare exponent operations for POWER7/8.</p>
<p>The PVECLIB implementations for quad-precision arithmetic and conversion operations are large enough that most applications will want to call a library. PVECLIB will build and release the appropriate CPU tuned libraries. This will follow the general design used for multiple quadword integer multiply functions (<a class="el" href="vec__int512__ppc_8h.html" title="Header package containing a collection of multiple precision quadword integer computation functions i...">vec_int512_ppc.h</a>).</p>
<dl class="section note"><dt>Note</dt><dd>At this time, PVECLIB does not intend to replace existing GCC/libm IEEE-128 runtime APIs and will maintain it own unique name-space. However if the maintainers of these projects want to leverage PVECLIB they are allowed under the terms of the <a href="http://www.apache.org/licenses/LICENSE-2.0">Apache License, Version 2.0.</a></dd></dl>
<p>These PVECLIB operations should be useful for applications using Quad-Precision while needing to still support POWER8 but also build for POWER9/10. An important goal is to allow applications and libraries to safely substitute PVECLIB operations for C language and math.h __float128 operators and functions as point optimizations. The largest gains will be seen for builds targeting POWER8 without degrading performance when targeting POWER9/10. They should also be useful and improve performance of soft-float implementations of Quad-Precision math library functions.</p>
<dl class="section note"><dt>Note</dt><dd>The compiler disables associated <altivec.h> built-ins if the <b>mcpu</b> target does not enable the specific instruction. For example if you compile with <b>-mcpu=power8</b>, Quad-Precision floating-point built-ins operations useful for floating point classification are not defined. This header provides the appropriate substitutions, will generate the minimum code, appropriate for the target, and produce correct results.</dd>
<dd>
Most ppc64le compilers will default to <b>-mcpu=</b><em>power8</em> if <b>-mcpu</b> is not specified.</dd></dl>
<p>This header covers operations that are any of the following:</p>
<ul>
<li>Implemented in hardware instructions in newer processors, but useful to programmers on slightly older processors (even if the equivalent function requires more instructions).</li>
<li>Defined in the OpenPOWER ABI but <em>not</em> yet defined in <altivec.h> provided by available compilers in common use. Examples include scalar_test_neg, scalar_test_data_class, etc.</li>
<li>Defined for POWER9 (as built-ins) but not supported in the soft-float runtime implementation provided for POWER8. Examples include the arithmetic/conversion operations supporting the <em>round-to-odd</em> override.</li>
<li>Providing vector float tests for special conditions without generating extraneous floating-point exceptions. This is important for implementing __float128 forms of ISO C99 Math functions. Examples include vector isnan, isinf, etc.</li>
<li>Commonly used operations, not covered by the ABI or <altivec.h>, and require multiple instructions or are not obvious.</li>
</ul>
<h1><a class="anchor" id="f128_softfloat_0_0"></a>
Vector implementation of Quad-Precision Soft-float</h1>
<p>The discussion above raises a interesting question. If we can provide useful implementations of Quad-Precision; classification, extract/insert, and compare exponent operations, why not continue with Quad-Precision compare, convert to/from integer, and arithmetic operations?</p>
<p>This raises the stakes in complexity and size of implementation. Providing a vector soft-float implementation equivalent to the GCC run-time libgcc <b>__addkf3/__divkf3/__mulkf3/__subkf3</b> would be a substantial effort. The IEEE standard is exacting about rounding and exception handling. Comparisons require special handling of; signed zero, infinities, and NaNs. Even float/integer conversions require correct rounding and return special values for overflow. Also it is not clear how such an effort would be accepted.</p>
<p>The good news is PVECLIB already provides a strong quadword integer operations set. Integer Add, subtract, and multiply are covered with the usual compare/shift/rotate operations (See <a class="el" href="vec__int128__ppc_8h.html" title="Header package containing a collection of 128-bit computation functions implemented with PowerISA VMX...">vec_int128_ppc.h</a> and <a class="el" href="vec__int64__ppc_8h.html" title="Header package containing a collection of 128-bit SIMD operations over 64-bit integer elements.">vec_int64_ppc.h</a>). The weak spot is general quadword integer divide. Until recently, integer divide has not been part of the vector ISA. But the introduction of Vector Divide Signed/Unsigned Quadword in POWER10 raises the priority of vector integer divide for PVECLIB.</p>
<p>For now we propose a phased approach, starting with enablers and infrastructure, building up layers, starting simple and adding complexity.</p>
<ul>
<li>Basic enablers; classification, extract/insert exponent, compare exponent.</li>
<li>Quad-Precision comparison operators.<ul>
<li>Initially ignore special cases and exceptions</li>
<li>Add Signed Zero, Infinity. and NaN special cases</li>
<li>Exceptions (FPSCR) when someone asks</li>
</ul>
</li>
<li>Quad-Precision from/to integer word/doubleword/quadword.<ul>
<li>Cases that don't require rounding (i.e truncate and DW to QP).</li>
<li>Cases that require rounding<ul>
<li>Round to odd.</li>
<li>Round to Nearest/Even</li>
<li>Others if asked</li>
</ul>
</li>
</ul>
</li>
<li>Quad-Precision arithmetic<ul>
<li>Add/Sub/Mul<ul>
<li>Round-to-Odd first</li>
</ul>
</li>
<li>Fused Multiply-Add<ul>
<li>Round-to-Odd first</li>
</ul>
</li>
<li>Divide<ul>
<li>Round-to-Odd first</li>
<li>Will need <a class="el" href="vec__int128__ppc_8h.html" title="Header package containing a collection of 128-bit computation functions implemented with PowerISA VMX...">vec_int128_ppc.h</a> implementation of vec_divuq()</li>
</ul>
</li>
<li>Signed Zero, Infinity. and NaN special cases</li>
<li>Other rounding modes</li>
<li>Exceptions (FPSCR) when someone asks</li>
</ul>
</li>
</ul>
<p>The intent is that such PVECLIB operations can be mixed in with or substituted for C Language _FLoat128 expressions or functions. The in-lined operations should have performance advantages over equivalent library functions on both POWER8/9.</p>
<p>This is a big list. It is TBD how far I will get given my current limited resources.</p>
<dl class="section note"><dt>Note</dt><dd>We are focusing on POWER8 here because the implementation gets a lot harder for POWER7 and earlier. POWER7 is missing:<ul>
<li>Vector Quadword integer add/sub with carry extend.</li>
<li>Vector Doubleword integer arithmetic, compares. and count-leading zeros.</li>
<li>Vector Word integer multiply.</li>
<li>Direct transfer between VRs and GPRs.</li>
</ul>
</dd></dl>
<h2><a class="anchor" id="f128_softfloat_0_0_0"></a>
Quad-Precision data class and exponent access for POWER8</h2>
<p>Most math library functions need to test the data class (normal, infinity, NaN, etc) and or range of input values. This usually involves separating the sign, exponent, and significand out from __float128 values, and comparing one or more of these parts, to special integer values.</p>
<p>PowerISA 3.0B (POWER9) provides instructions for these in addition to a comprehensive set of arithmetic and compare instructions. These operations are also useful for the soft-float implementation of __float128 for POWER8 and earlier. The OpenPOWER ABI specifies __float128 parameters are in VRs and are immediately accessible to VMX/VSR instructions. This is important as the cost of transferring values between VRs and GPRs is quite high on POWER8 and even higher for POWER7 and earlier (which requires store to temporaries and reload).</p>
<p>Fortunately these operations only require logical (and/or/xor), shift and integer compare operations to implement. These are available as vector intrinsics or provides by PVECLIB (see <a class="el" href="vec__int128__ppc_8h.html" title="Header package containing a collection of 128-bit computation functions implemented with PowerISA VMX...">vec_int128_ppc.h</a>).</p>
<p>The operations in this group include:</p><ul>
<li>Altivec like predicates; <a class="el" href="vec__f128__ppc_8h.html#a946ffd501b32f3ec96563ab101afbfad" title="Return true if the __float128 value is Finite (Not NaN nor Inf).">vec_all_isfinitef128()</a>, <a class="el" href="vec__f128__ppc_8h.html#a66fc4e7c94d0b30bb3515931aaf723da" title="Return true if the __float128 value is infinity.">vec_all_isinff128()</a>, <a class="el" href="vec__f128__ppc_8h.html#af06b73ac57985011c558670adc283e89" title="Return true if the __float128 value is Not a Number (NaN).">vec_all_isnanf128()</a>, <a class="el" href="vec__f128__ppc_8h.html#afc830b382bd45dc0ff815024c1bfb26d" title="Return true if the __float128 value is normal (Not NaN, Inf, denormal, or zero).">vec_all_isnormalf128()</a>, <a class="el" href="vec__f128__ppc_8h.html#adf1a94cccdb3f106a0e6399e2f034718" title="Return true if the __float128 value is subnormal (denormal).">vec_all_issubnormalf128()</a>, <a class="el" href="vec__f128__ppc_8h.html#ac554a9d0d12fca036772aaaee5908414" title="Return true if the __float128 value is +-0.0.">vec_all_iszerof128()</a>, <a class="el" href="vec__f128__ppc_8h.html#a4ca7749d334c2a2c17a4d2a98b5bf755" title="Return int boolean true if the __float128 value is negative (sign bit is '1').">vec_signbitf128()</a>.</li>
<li>Vector boolean predicates; <a class="el" href="vec__f128__ppc_8h.html#ad1668ff13922ca04059f1844a7a1464f" title="Return 128-bit vector boolean true if the __float128 value is Finite (Not NaN nor Inf).">vec_isfinitef128()</a>, <a class="el" href="vec__f128__ppc_8h.html#a94f9c7429c2ebd9b9f32ad6e98689ebb" title="Return a 128-bit vector boolean true if the __float128 value is infinity.">vec_isinff128()</a>, <a class="el" href="vec__f128__ppc_8h.html#a11c410994f958a6b4ac9583878a55a72" title="Return 128-bit vector boolean true if the __float128 value is Not a Number (NaN).">vec_isnanf128()</a>, <a class="el" href="vec__f128__ppc_8h.html#aa25185c83b69f6af3f3d9399199c8a57" title="Return 128-bit vector boolean true if the __float128 value is normal (Not NaN, Inf,...">vec_isnormalf128()</a>, <a class="el" href="vec__f128__ppc_8h.html#a9670e4655a9c7888c80343780cd7abf9" title="Return 128-bit vector boolean true value, if the __float128 value is subnormal (denormal).">vec_issubnormalf128()</a>, <a class="el" href="vec__f128__ppc_8h.html#a598a822d22b02ba0d2c2a1095a4e700d" title="Return 128-bit vector boolean true value, if the value that is +-0.0.">vec_iszerof128()</a>, <a class="el" href="vec__f128__ppc_8h.html#a4d5b388cfc9af26418bdd4ec8e4e6f73" title="Vector Set Bool from Quadword Floating-point.">vec_setb_qp()</a>.</li>
<li>Sign bit manipulation; <a class="el" href="vec__f128__ppc_8h.html#add641f5a217eff45f0e836fa98613584" title="Absolute Quad-Precision.">vec_absf128()</a>, <a class="el" href="vec__f128__ppc_8h.html#a7c2297dc22a6a3120491e1721648c0e7" title="Negative Absolute value Quad-Precision.">vec_nabsf128()</a>, <a class="el" href="vec__f128__ppc_8h.html#a3323b6fb0b379a21f3dd70f7f204bd2a" title="Negate the sign bit of a __float128 input and return the resulting __float128 value.">vec_negf128()</a>, <a class="el" href="vec__f128__ppc_8h.html#adfb73eac40698921735bad8ac4ce560e" title="Copy the sign bit from f128x and merge with the magnitude from f128y. The merged result is returned a...">vec_copysignf128()</a>.</li>
<li>Data manipulation; <a class="el" href="vec__f128__ppc_8h.html#af95c675ceebc0627c777d2c7e2daef0b" title="Scalar Insert Exponent Quad-Precision.">vec_xsiexpqp()</a>, <a class="el" href="vec__f128__ppc_8h.html#a3d78e42d9cc58491fa46149bf5798167" title="Scalar Extract Exponent Quad-Precision.">vec_xsxexpqp()</a>, <a class="el" href="vec__f128__ppc_8h.html#a93a77b974dcb698d916828f5986ea9cd" title="Vector Extract Exponent Quad-Precision Pair.">vec_xxxexpqpp()</a>, <a class="el" href="vec__f128__ppc_8h.html#ab1eb10beac182e936d7e49d491c34fe0" title="Scalar Extract Significand Quad-Precision.">vec_xsxsigqp()</a>.</li>
<li>Exponent Compare; <a class="el" href="vec__f128__ppc_8h.html#a1e6c52eb3208f4d9ed851ee48f773d68" title="Vector Compare Quad-Precision Exponents for Equal.">vec_cmpqp_exp_eq()</a>, <a class="el" href="vec__f128__ppc_8h.html#abf2d90d67cb3f605fbc9598f133b0305" title="Vector Compare Exponents Quad-Precision for Greater Than.">vec_cmpqp_exp_gt()</a>, <a class="el" href="vec__f128__ppc_8h.html#a3eb9b92be998695424107de6a60890a8" title="Vector Compare Exponents Quad-Precision for Less Than.">vec_cmpqp_exp_lt()</a>, <a class="el" href="vec__f128__ppc_8h.html#a3014214c103453a34372cc52e6d79073" title="Vector Compare Exponents Quad-Precision for Unordered.">vec_cmpqp_exp_unordered()</a>.</li>
</ul>
<p>For example the data class test isnan: </p><div class="fragment"><div class="line"><span class="keyword">static</span> <span class="keyword">inline</span> <a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a></div>
<div class="line"><a class="code" href="vec__f128__ppc_8h.html#a11c410994f958a6b4ac9583878a55a72">vec_isnanf128</a> (<a class="code" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</div>
<div class="line">{</div>
<div class="line"><span class="preprocessor">#if defined (_ARCH_PWR9) && defined (scalar_test_data_class) && \</span></div>
<div class="line"><span class="preprocessor"> defined (__FLOAT128__) && (__GNUC__ > 7)</span></div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> result = <a class="code" href="vec__common__ppc_8h.html#ae4520a89b9b5a292a3e647a6d5b712ad">CONST_VINT128_W</a> (0, 0, 0, 0);</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">if</span> (scalar_test_data_class (f128, 0x40))</div>
<div class="line"> result = <a class="code" href="vec__common__ppc_8h.html#ae4520a89b9b5a292a3e647a6d5b712ad">CONST_VINT128_W</a> (-1, -1, -1, -1);</div>
<div class="line"> </div>
<div class="line"> <span class="keywordflow">return</span> (<a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a>)result;</div>
<div class="line"><span class="preprocessor">#else</span></div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> tmp;</div>
<div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> signmask = <a class="code" href="vec__common__ppc_8h.html#ae4520a89b9b5a292a3e647a6d5b712ad">CONST_VINT128_W</a> (0x80000000, 0, 0, 0);</div>
<div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> expmask = <a class="code" href="vec__common__ppc_8h.html#ae4520a89b9b5a292a3e647a6d5b712ad">CONST_VINT128_W</a> (0x7fff0000, 0, 0, 0);</div>
<div class="line"> </div>
<div class="line"> tmp = <a class="code" href="vec__f128__ppc_8h.html#aedfcf3adea80e0407b40c6ec0e851aab">vec_andc_bin128_2_vui32t</a> (f128, signmask);</div>
<div class="line"> <span class="keywordflow">return</span> <a class="code" href="vec__int128__ppc_8h.html#ad4ce43dcbc14fb34623d5ece8073b86e">vec_cmpgtuq</a> ((<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>)tmp , (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>)expmask);</div>
<div class="line"><span class="preprocessor">#endif</span></div>
<div class="line"><span class="preprocessor">}</span></div>
</div><!-- fragment --><p> Which has implementations for POWER9 (and later) and POWER8 (and earlier).</p>
<p>For POWER9 it generates: </p><div class="fragment"><div class="line">xststdcqp cr0,v2,64</div>
<div class="line">bne .+12</div>
<div class="line">xxspltib vs34,255</div>
<div class="line">b .+8</div>
<div class="line">xxspltib vs34,0</div>
</div><!-- fragment --><p> Which uses the intrinsic scalar_test_data_class() to generate the VSX Scalar Test Data Class Quad-Precision instruction with "data class mask" of <em>class.NaN</em> to set the condition code. If the condition is <em>match</em>, load the 128-bit bool value of all 1's (true). Otherwise load all 0's (false).</p>
<p>For POWER8 it generates </p><div class="fragment"><div class="line">addis r9,r2,@ha.rodata.cst16+0x30</div>
<div class="line">vspltisw v1,-1</div>
<div class="line">vspltisw v12,0</div>
<div class="line">addi r9,r9,@l.rodata.cst16+0x30</div>
<div class="line">vslw v1,v1,v1</div>
<div class="line">lvx v0,0,r9</div>
<div class="line">vsldoi v1,v1,v12,12</div>
<div class="line"> </div>
<div class="line">xxlandc vs33,vs34,vs33</div>
<div class="line">vsubcuq v0,v0,v1</div>
<div class="line">xxspltw vs32,vs32,3</div>
<div class="line">vcmpequw v2,v0,v12</div>
</div><!-- fragment --><p> The first 7 instructions above, load the constant vectors needed by the logic. These constants only need to be generated once per function and can be shared across operations.</p>
<p>In the C code we use a special transfer function combined with logical AND complement (<a class="el" href="vec__f128__ppc_8h.html#aedfcf3adea80e0407b40c6ec0e851aab" title="Transfer a quadword from a __binary128 scalar to a vector int and logical AND Compliment with mask.">vec_andc_bin128_2_vui32t()</a>). This is required because while __float128 values are held in VRs, the compiler considers them to be scalars and will not allow simple casts to (any) vector type. So the PVECLIB implementation provides <em>xfer</em> function using a union to transfer the __float128 value to a vector type. In most case this logical transfer simply serves to make the compiler happy and does not need to generate any code. In this case the <em>xfer</em> function combines the transfer with a vector and complement to mask off the sign bit.</p>
<p>Then compare the masked result as a 128-bit integer value greater than infinity (expmask). Here we use the <a class="el" href="vec__int128__ppc_8h.html#ad4ce43dcbc14fb34623d5ece8073b86e" title="Vector Compare Greater Than Unsigned Quadword.">vec_cmpgtuq()</a> operation from <a class="el" href="vec__int128__ppc_8h.html" title="Header package containing a collection of 128-bit computation functions implemented with PowerISA VMX...">vec_int128_ppc.h</a>. For POWER8, <a class="el" href="vec__int128__ppc_8h.html#ad4ce43dcbc14fb34623d5ece8073b86e" title="Vector Compare Greater Than Unsigned Quadword.">vec_cmpgtuq()</a> generates the Vector Subtract and Write Carry Unsigned Quadword instruction for 128-bit unsigned compares. A '0' carry indicates greater than. The next two instructions (from <a class="el" href="vec__int128__ppc_8h.html#a921647d5b67f0de5006ee32fb3d9c4f1" title="Vector Set Bool from Quadword not Carry.">vec_setb_ncq()</a>) convert the carry bit to the required 128-bit bool value.</p>
<p>While the POWER8 sequence requires more instructions (including the const vector set up) than POWER9, it is not significantly larger. And as mentioned above, the set-up code can be optimized across operations sharing the same constants. The code (less the setup) is only 10 cycles for POWER8 vs 6 for POWER9. Also the code is not any larger than the function call overhead for the libgcc runtime equivalent <b>__unordkf2</b>. And is much faster then the generic soft-float implementation.</p>
<p>Another example, Scalar Extract Exponent Quad-Precision:</p>
<div class="fragment"><div class="line"><span class="keyword">static</span> <span class="keyword">inline</span> <a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a></div>
<div class="line"><a class="code" href="vec__f128__ppc_8h.html#a3d78e42d9cc58491fa46149bf5798167">vec_xsxexpqp</a> (<a class="code" href="vec__f128__ppc_8h.html#a443a43ae34ab3b78564d2a8277503cac">__binary128</a> f128)</div>
<div class="line">{</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> result;</div>
<div class="line"><span class="preprocessor">#if defined (_ARCH_PWR9) && defined (__FLOAT128__) && (__GNUC__ > 7)</span></div>
<div class="line"> __asm__(</div>
<div class="line"> <span class="stringliteral">"xsxexpqp %0,%1"</span></div>
<div class="line"> : <span class="stringliteral">"=v"</span> (result)</div>
<div class="line"> : <span class="stringliteral">"v"</span> (f128)</div>
<div class="line"> : );</div>
<div class="line"> </div>
<div class="line"><span class="preprocessor">#else</span></div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> tmp;</div>
<div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> expmask = <a class="code" href="vec__common__ppc_8h.html#ae4520a89b9b5a292a3e647a6d5b712ad">CONST_VINT128_W</a> (0x7fff0000, 0, 0, 0)</div>
<div class="line"> </div>
<div class="line"> tmp = <a class="code" href="vec__f128__ppc_8h.html#aae0e62b9910ec833dfc20719d09e526e">vec_and_bin128_2_vui32t</a> (f128, expmask);</div>
<div class="line"> result = (<a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a>) vec_sld (tmp, tmp, 10);</div>
<div class="line"><span class="preprocessor">#endif</span></div>
<div class="line"> <span class="keywordflow">return</span> result;</div>
<div class="line">}</div>
</div><!-- fragment --><p> Which has implementations for POWER9 (and later) and POWER8 (and earlier).</p>
<p>For POWER9 it generates the VSX Scalar Extract Exponent Quad-Precision instruction. </p><div class="fragment"><div class="line">xsxexpqp v2,v2</div>
</div><!-- fragment --><dl class="section note"><dt>Note</dt><dd>Would like to use the intrinsic scalar_extract_exp() here but this is not available until GCC 11 (or later). Also GCC defines these scalar built-ins to return integer scalar values in GPRs. This would defeat the purpose of an all vector implementation.</dd></dl>
<p>For POWER8 we generate </p><div class="fragment"><div class="line">addis r9,r2,.rodata.cst16+0xc0@ha</div>
<div class="line">addi r9,r9,.rodata.cst16+0xc0@l</div>
<div class="line">lvx v13,0,r9</div>
<div class="line"> </div>
<div class="line">xxland vs34,vs34,vs45</div>
<div class="line">vsldoi v2,v2,v2,10</div>
</div><!-- fragment --><p> The first 3 instructions above load the constant vector needed by the logic. This constant only needs to be generated once per function and can be shared across operations.</p>
<p>Again we use a special transfer function combined with logical AND (<a class="el" href="vec__f128__ppc_8h.html#aae0e62b9910ec833dfc20719d09e526e" title="Transfer a quadword from a __binary128 scalar to a vector int and logical AND with a mask.">vec_and_bin128_2_vui32t()</a>) to transfer the__float128 to a vector type and mask off all bits except for the 15-bit exponent. Then we rotate the exponent logically right 48-bit to right justify the exponent in vector doubleword 0. This matches the results of the xsxexpqp instruction.</p>
<h2><a class="anchor" id="f128_softfloat_IRRN_0_0"></a>
Intermediate results and Rounding for Quad-Precision</h2>
<p>The IEEE-128 floating-point storage (external) format fits neatly in 128-bits. But this compact format needs to be expanded internally during QP operations. The sign and exponent are normally manipulated separately from the significand. And for finite values the Leading-bit (implied but not included in the storage format) must be restored to take part in arithmetic/rounding/normalization operations.</p>
<dl class="section note"><dt>Note</dt><dd>The <em>Leading</em>, <em>Hidden</em>, and <em>Implicit</em> bits are different names for the most significant bit of the significand. This bit is Hidden or Implicit only for the external or storage format of floating-point numbers. But it needs to be explicitly represented in the internal <em>Intermediate Results (<b>IR</b>)</em>. See Also: PowerISA 3.0 7.3.3 VSX Floating-Point Execution Models.</dd></dl>
<p>For a soft-float implementation of IEEE-128 on POWER8 we want to extract these components into 128-bit vector registers and operate on them using vector instructions. This allows direct use of 128-bit arithmetic/shift/rotate operations (see <a class="el" href="vec__int128__ppc_8h.html" title="Header package containing a collection of 128-bit computation functions implemented with PowerISA VMX...">vec_int128_ppc.h</a>), while avoiding expensive transfers between VRs and GPRs.</p>
<p>To extract the sign-bit we can either AND with a 128-bit mask or use a set-bool operation (<a class="el" href="vec__f128__ppc_8h.html#a4d5b388cfc9af26418bdd4ec8e4e6f73" title="Vector Set Bool from Quadword Floating-point.">vec_setb_qp()</a> or <a class="el" href="vec__int128__ppc_8h.html#af21d01bb19f0ea8605d8c37035837802" title="Vector Set Bool from Signed Quadword.">vec_setb_sq()</a>). The masked sign-bit can be ORed with the final IEEE-128 vector result to set the appropriate sign. The 128-bit vector bool can be used with vec_sel() (<a class="el" href="vec__f128__ppc_8h.html#a47637906e95a7c94cffc093bc2e57dbf" title="Select and Transfer from one of two __binary128 scalars under a 128-bit mask. The result is a __binar...">vec_self128()</a>, <a class="el" href="vec__int128__ppc_8h.html#a9d388d607e331ffb7cecd6dcbdd0d18b" title="Vector Select Signed Quadword.">vec_selsq()</a>, <a class="el" href="vec__int128__ppc_8h.html#a5949bfddc954f2a50922abfbd32176cd" title="Vector Select Unsigned Quadword.">vec_seluq()</a>) to select results based on the sign-bit while avoiding branch logic.</p>
<p>We use <a class="el" href="vec__f128__ppc_8h.html#a3d78e42d9cc58491fa46149bf5798167" title="Scalar Extract Exponent Quad-Precision.">vec_xsxexpqp()</a> to extract the 15-bit exponent into a vector doubleword integer element. The biased exponent is returned in the high doubleword (matching the POWER9 instruction). Depending on the operation, the exponent (or derived values) may need to be transfered/replicated to the low doubleword element. This is easily accomplished using <a class="el" href="vec__int64__ppc_8h.html#a671e86d52ad53adce6a558476c7ffc0c" title="Vector splat doubleword. Duplicate the selected doubleword element across the doubleword elements of ...">vec_splatd()</a>. Operations requiring two Quad-precision operands can combine the extracted exponents into a single vector doubleword using <a class="el" href="vec__int64__ppc_8h.html#acd5bafec6c1c15b0336551e82d1169d4" title="Vector Merge Algebraic High Doublewords.">vec_mrgahd()</a>.</p>
<dl class="section note"><dt>Note</dt><dd>Operations requiring two Quad-precision operands have an opportunity to vectorize the exponent extraction and comparisons (all/any) for finite vs NaN/Infinity. See <a class="el" href="vec__f128__ppc_8h.html#a93a77b974dcb698d916828f5986ea9cd" title="Vector Extract Exponent Quad-Precision Pair.">vec_xxxexpqpp()</a>.</dd></dl>
<p>We use <a class="el" href="vec__f128__ppc_8h.html#ab1eb10beac182e936d7e49d491c34fe0" title="Scalar Extract Significand Quad-Precision.">vec_xsxsigqp()</a> to extract the 113-bit significand into a vector quadword integer. This operation restores the leading-bit for normal (not NaN, Infinity, denormal or zero) values. The significand is returned right-justified in the quadword.</p>
<p>At the end of the operation we can use vec_or() and <a class="el" href="vec__f128__ppc_8h.html#af95c675ceebc0627c777d2c7e2daef0b" title="Scalar Insert Exponent Quad-Precision.">vec_xsiexpqp()</a> to combine these (sign, exponent, and significand) components into a IEEE-128 result.</p>
<h3><a class="anchor" id="f128_softfloat_IRRN_0_1"></a>
Representing Intermediate results for Quad-Precision</h3>
<p>Internal IEEE floating-point operations will need/generate additional bits to support normalization and rounding. The PowerISA describes a <b>VSX Execution Model for IEEE Operations</b> </p><dl class="section see"><dt>See also</dt><dd>PowerISA 3.0B, Book I, Section 7.3.3 VSX Floating-Point Execution Models.</dd></dl>
<p>IEEE quad-precision execution model </p><table class="markdownTable">
<tr class="markdownTableHead">
<th class="markdownTableHeadLeft"></th><th class="markdownTableHeadCenter"></th><th class="markdownTableHeadCenter">0 </th><th class="markdownTableHeadCenter">1 --------------------------— 112 </th><th class="markdownTableHeadCenter"></th><th class="markdownTableHeadCenter"></th><th class="markdownTableHeadRight"></th></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft">S </td><td class="markdownTableBodyCenter">C </td><td class="markdownTableBodyCenter">L </td><td class="markdownTableBodyCenter">FRACTION </td><td class="markdownTableBodyCenter">G </td><td class="markdownTableBodyCenter">R </td><td class="markdownTableBodyRight">X </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft" colspan="7">- Sign bit </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft" colspan="7">- Carry bit </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft" colspan="7">- Leading bit, also called the implicit or hidden bit </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft" colspan="7">- Fraction (112-bits) </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft" colspan="7">- Guard bit </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft" colspan="7">- Round bit </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft" colspan="7">- (X) AKA Sticky bit, logical OR of remaining bits </td></tr>
</table>
<p>This model is a guide for processor design and soft-float implementors. This is also described as the <em>Intermediate result Representation (<b>IR</b>)</em>. As such the implementation may arrange these bits into different registers as dictated by design and performance.</p>
<p>The GRX bits extend the low order bits of the fraction and are required for rounding. Basically these bits encode how <em>near</em> the intermediate result is to a representable result. The GR bits are required for post-normalization of the result and participate in shifts during normalization. For right shifts, bits shift out of the R-bit are logically ORed into the X-bit. For left shifts, 0 bits shifted into the R-bit (the X-bit is ignored).</p>
<p>As mentioned before, it is convenient to keep the sign-bit in a separate vector quadword. This not an extension of the significand but is needed to select results for arithmetic and some rounding modes. The remaining (C through X) bits can be represented in a vector quadword register or a vector register pair.</p>
<h4><a class="anchor" id="f128_softfloat_IRRN_0_1_1"></a>
IR for conversion</h4>
<p>For example integer to QP conversions can be represented in a vector quadword by left justifying the magnitude before normalization and rounding. For example from <a class="el" href="vec__f128__ppc_8h.html#a24b1f22552fd177d10af1dbc0f43d5f8" title="VSX Scalar Convert Unsigned-Quadword to Quad-Precision format.">vec_xscvuqqp()</a>: </p><div class="fragment"><div class="line">{ <span class="comment">// We need to produce a normal QP, so we treat the integer like a</span></div>
<div class="line"> <span class="comment">// denormal, then normalize it.</span></div>
<div class="line"> <span class="comment">// Start with the quad exponent bias + 127 then subtract the count of</span></div>
<div class="line"> <span class="comment">// leading '0's. The 128-bit significand can have 0-127 leading '0's.</span></div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> q_expm = (<a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a>) <a class="code" href="vec__common__ppc_8h.html#af4ffb9244d1aa4482b683d35c3544194">CONST_VINT64_DW</a> (0, (0x3fff + 127));</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> i64_clz = (<a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a>) <a class="code" href="vec__int128__ppc_8h.html#a066cc120c198773a2f8dfd17480b7a49">vec_clzq</a> (q_sig);</div>
<div class="line"> q_sig = <a class="code" href="vec__int128__ppc_8h.html#a49fe2c36fca9911ab99a1f8abb53f0ff">vec_slq</a> (q_sig, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) i64_clz);</div>
<div class="line"> q_exp = <a class="code" href="vec__int64__ppc_8h.html#a0b7aee3c81538f5537680b610d934500">vec_subudm</a> (q_expm, i64_clz);</div>
<div class="line"> <span class="comment">// This is the part that might require rounding.</span></div>
<div class="line"> <span class="comment">// The Significand (including the L-bit) is right justified in</span></div>
<div class="line"> <span class="comment">// in the high-order 113-bits of q_sig.</span></div>
<div class="line"> <span class="comment">// The guard, round, and sticky (GRX) bits are in the low-order</span></div>
<div class="line"> <span class="comment">// 15 bits.</span></div>
<div class="line"> ...</div>
<div class="line">}</div>
</div><!-- fragment --><p>See <a class="el" href="vec__f128__ppc_8h.html#f128_softfloat_IRRN_0_2_1">Examples for Round to Nearest Even</a> and <a class="el" href="vec__f128__ppc_8h.html#f128_softfloat_IRRN_0_2_2">Examples for Round toward Zero</a>.</p>
<p>The <em>Round to Nearest Even</em> case may increment the significand and that may generate a carry from the <b>L-bit</b>. One option is to use <a class="el" href="vec__int128__ppc_8h.html#ad7aaadba249ce46c4c94f78df1020da3" title="Vector Add & write Carry Unsigned Quadword.">vec_addcuq()</a> to capture the carry. For example: </p><div class="fragment"><div class="line">...</div>
<div class="line"><span class="comment">// We add 0x3fff to GRX-bits which may carry into low order sig-bit</span></div>
<div class="line"><span class="comment">// This may result in a carry out from the L-bit into C-bit.</span></div>
<div class="line">q_carry = <a class="code" href="vec__int128__ppc_8h.html#ad7aaadba249ce46c4c94f78df1020da3">vec_addcuq</a> (q_sig, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) RXmask);</div>
<div class="line">q_sig = <a class="code" href="vec__int128__ppc_8h.html#a539de2a4426a84102471306acc571ce8">vec_adduqm</a> (q_sig, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) RXmask);</div>
<div class="line"><span class="comment">// Generate a bool mask from the carry to use in the vsel</span></div>
<div class="line">qcmask = <a class="code" href="vec__int128__ppc_8h.html#af74036e39e72e0f3c29706d30fbb96d1">vec_setb_cyq</a> (q_carry);</div>
<div class="line"><span class="comment">// Two cases; 1) We did carry so shift (double) left 112 bits</span></div>
<div class="line">q_sigc = <a class="code" href="vec__int128__ppc_8h.html#aaa33904ec4de42f54cceab34adb303c5">vec_sldqi</a> (q_carry, q_sig, 112);</div>
<div class="line"><span class="comment">// 2) no carry so shift right 15 bits</span></div>
<div class="line">q_sig = <a class="code" href="vec__int128__ppc_8h.html#ac05c640c6a42770cb95466ff4a2d903c">vec_srqi</a> ((<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) q_sig, 15);</div>
<div class="line"><span class="comment">// Select which based on carry</span></div>
<div class="line">q_sig = (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vec_sel ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) q_sig, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) q_sigc, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) qcmask);</div>
<div class="line"><span class="comment">// Increment the exponent based on the carry</span></div>
<div class="line">q_exp = <a class="code" href="vec__int64__ppc_8h.html#a28052c1907d1f733c9dda8a48039e546">vec_addudm</a> (q_exp, (<a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a>) q_carry);</div>
</div><!-- fragment --><p> In this case having the carry as a separate vector simplifies adjusting the exponent.</p>
<h4><a class="anchor" id="f128_softfloat_IRRN_0_1_2"></a>
IR for addition</h4>
<p>Quad-precision addition and subtraction is a case where right justifying the <b>IR</b> is helpful. For addition/subtraction the <b>IR</b> only needs 117-bits which can be accommodated in a single 128-vector. Significands (which includes the leading/implicit bit) can be converted to <b>IR</b> form by shifting left 3-bits. This still leaves room on the left for the carry-bit. For example: </p><div class="fragment"><div class="line"><span class="comment">// Precondition the significands before add so the GRX bits</span></div>
<div class="line"><span class="comment">// are in the least significant 3 bit.</span></div>
<div class="line">a_sig = <a class="code" href="vec__int128__ppc_8h.html#a070fe972995f3954362835f5b72e5ff6">vec_slqi</a> (a_sig, 3);</div>
<div class="line">b_sig = <a class="code" href="vec__int128__ppc_8h.html#a070fe972995f3954362835f5b72e5ff6">vec_slqi</a> (b_sig, 3);</div>
</div><!-- fragment --><p> In this case we need to insure that any right shifts of the <b>IR</b> collect any bits shifted-away into the X-bit. For example: </p><div class="fragment"><div class="line"><span class="comment">// At this point we can assume that:</span></div>
<div class="line"><span class="comment">// 1) The magnitude (vfa) >= magnitude (vfb)</span></div>
<div class="line"><span class="comment">// 1a) Exponents (a_exp, b_exp) in the range E_min -> E_max</span></div>
<div class="line"><span class="comment">// 1b) The GRX-bits of a_sig/b_sig are still 0b000.</span></div>
<div class="line"><span class="comment">// 2) a_exp >= b_exp</span></div>
<div class="line"><span class="comment">// 2a) If a_exp == b_exp then a_sig >= b_sig</span></div>
<div class="line"><span class="comment">// 2b) If a_exp > b_exp then</span></div>
<div class="line"><span class="comment">// shift (b_sig) right by (a_exp - b_exp) bits</span></div>
<div class="line"><span class="comment">// any bits shifted out of b_sig are ORed into the X-bit</span></div>
<div class="line"><span class="keywordflow">if</span> (<a class="code" href="vec__int64__ppc_8h.html#a55dcb361982b9da13b02373d720d6c7d">vec_cmpud_all_lt</a> (b_exp, a_exp))</div>
<div class="line"> {</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> d_exp, l_exp;</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> t_sig;</div>
<div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a> exp_128 = (<a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a>) <a class="code" href="vec__common__ppc_8h.html#af4ffb9244d1aa4482b683d35c3544194">CONST_VINT64_DW</a>( 128, 128 );</div>
<div class="line"> </div>
<div class="line"> d_exp = <a class="code" href="vec__int64__ppc_8h.html#a0b7aee3c81538f5537680b610d934500">vec_subudm</a> (a_exp, b_exp);</div>
<div class="line"> <span class="keywordflow">if</span> (<a class="code" href="vec__int64__ppc_8h.html#a55dcb361982b9da13b02373d720d6c7d">vec_cmpud_all_lt</a> (d_exp, exp_128))</div>
<div class="line"> {</div>
<div class="line"> l_exp = <a class="code" href="vec__int64__ppc_8h.html#a0b7aee3c81538f5537680b610d934500">vec_subudm</a> (exp_128, d_exp);</div>
<div class="line"> t_sig = <a class="code" href="vec__int128__ppc_8h.html#a0edd172a5656b842d6586c5078284942">vec_srq</a> (b_sig, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) d_exp);</div>
<div class="line"> x_bits = <a class="code" href="vec__int128__ppc_8h.html#a49fe2c36fca9911ab99a1f8abb53f0ff">vec_slq</a> (b_sig, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) l_exp);</div>
<div class="line"> }</div>
<div class="line"> <span class="keywordflow">else</span></div>
<div class="line"> {</div>
<div class="line"> x_bits = b_sig;</div>
<div class="line"> t_sig = (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) q_zero;</div>
<div class="line"> }</div>
<div class="line"> <span class="comment">// Collect any bits shifted-away, into a single carry bit</span></div>
<div class="line"> p_odd = <a class="code" href="vec__int128__ppc_8h.html#ad7aaadba249ce46c4c94f78df1020da3">vec_addcuq</a> (x_bits, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) q_ones);</div>
<div class="line"> <span class="comment">// OR this into the X-bit</span></div>
<div class="line"> b_sig = (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vec_or ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) t_sig, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) p_odd);</div>
<div class="line"> }</div>
</div><!-- fragment --><p> In this case, condition-1 means that, only b_sig needs right shifting before significand addition. The a_sig can be used directly as it had previously been left shifted 3-bits where the GRX-bits were set to 0b000.</p>
<p>A simpler case occurs when addition generates a carry. Here we need to shift right 1-bit while preserving any nonzero X-bit. For example: </p><div class="fragment"><div class="line"><span class="comment">// Check for carry and adjust</span></div>
<div class="line"><span class="keywordflow">if</span> (<a class="code" href="vec__int128__ppc_8h.html#ac93dc5ed8bb3501470cf70c5cb5796a9">vec_cmpuq_all_gt</a> (s_sig, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) sigov))</div>
<div class="line"> {</div>
<div class="line"> p_odd = (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vec_and ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) s_sig, xbitmask);</div>
<div class="line"> s_sig = <a class="code" href="vec__int128__ppc_8h.html#ac05c640c6a42770cb95466ff4a2d903c">vec_srqi</a> (s_sig, 1);</div>
<div class="line"> s_sig = (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vec_or ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) s_sig, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) p_odd);</div>
<div class="line"> q_exp = <a class="code" href="vec__int64__ppc_8h.html#a28052c1907d1f733c9dda8a48039e546">vec_addudm</a> (q_exp, q_one);</div>
<div class="line"> }</div>
</div><!-- fragment --><p> These two sequences preserve the X-bit going into the rounding stage. See <a class="el" href="vec__f128__ppc_8h.html#f128_softfloat_IRRN_0_2_1">Examples for Round to Nearest Even</a> and <a class="el" href="vec__f128__ppc_8h.html#f128_softfloat_IRRN_0_2_6">Examples for Round to Odd</a>.</p>
<h4><a class="anchor" id="f128_softfloat_IRRN_0_1_3"></a>
IR for multiply</h4>
<p>Quad-precision Multiply and Multiply-Add require quadword register pairs to hold the <b>IR</b> product. The product of two 113-bit significands requires 226-bits. This includes the product C-/L-bits but we will need at least 3 additional bits for GRX.</p>
<p>We can use operations from <a class="el" href="vec__int128__ppc_8h.html" title="Header package containing a collection of 128-bit computation functions implemented with PowerISA VMX...">vec_int128_ppc.h</a> to produce the double quadword product. By pre-adjusting the inputs before the multiply we can align the split between the high 114-bits (right justified) and low 112-bits (left justified) of the product to align with the high and low quadword registers. For example: </p><div class="fragment"><div class="line"><span class="comment">// Pre-align the multiply inputs so that the product is split</span></div>
<div class="line"><span class="comment">// with the CL-Fraction-bits in high_sig, and GRX-bits in low_sig.</span></div>
<div class="line">a_sig = <a class="code" href="vec__int128__ppc_8h.html#a070fe972995f3954362835f5b72e5ff6">vec_slqi</a> (a_sig, 8);</div>
<div class="line">b_sig = <a class="code" href="vec__int128__ppc_8h.html#a070fe972995f3954362835f5b72e5ff6">vec_slqi</a> (b_sig, 8);</div>
<div class="line">low_sig = <a class="code" href="vec__int128__ppc_8h.html#aee5c5b2998ef105b4c6f39739748ffa8">vec_muludq</a> (&high_sig, a_sig, b_sig);</div>
</div><!-- fragment --><p> The high_sig includes the C-/L-bits and high-order 112-bits of product fraction. The low_sig includes the low order 112-bits of the fraction followed by 16-bits of zero.</p>
<p>Most of the low-order fraction bits contribute to the X-bit. So we can normally delay collecting x-bits until the rounding stage. Only the most extreme denormals will result in a right shift large enough to require intervention to preserve bits that would otherwise be shifted away.</p>
<p>After normalization the high-order bits of low_sig become the GRX-bits. Actually we can treat the low order 126-bits as uncollected x-bits. We use this to simplify the rounding process. For this case we can manipulate low_sig to generate a carry for rounding up/down/odd and then add/subtract/or this carry to high_sig to produce the rounded product significand. See <a class="el" href="vec__f128__ppc_8h.html#f128_softfloat_IRRN_0_2_1">Examples for Round to Nearest Even</a> and <a class="el" href="vec__f128__ppc_8h.html#f128_softfloat_IRRN_0_2_6">Examples for Round to Odd</a>.</p>
<h3><a class="anchor" id="f128_softfloat_IRRN_0_2"></a>
Rounding for Quad-Precision</h3>
<p>The PowerISA support 6 rounding modes for Quad-Precision</p>
<ul>
<li>Round to Nearest Even</li>
<li>Round towards Zero</li>
<li>Round towards +Infinity</li>
<li>Round towards -Infinity</li>
<li>Round to Nearest Away</li>
<li>Round to Odd</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>See <a href="https://www.exploringbinary.com/gcc-avoids-double-rounding-errors-with-round-to-odd/">GCC Avoids Double Rounding Errors With Round-To-Odd</a></dd></dl>
<p>The first four modes are encoded in the <b>FPSCR<sub>RN</sub></b> rounding mode bits. The last two are encoded in instructions as instruction local overrides. The VSX Scalar Round to Quad-Precision Integer instruction can override the RN and encode any of the six rounding modes.</p>
<p>The rounding mode results are defined in terms of the intermediate result (IR), and how close it is to the <em>representable result</em>, based on the GRX-bits. The IR is either; exact, closer to the next lower (NL) representable result, Midway between, or closer to the next Higher (NH) representable result,</p>
<table class="markdownTable">
<tr class="markdownTableHead">
<th class="markdownTableHeadCenter">G </th><th class="markdownTableHeadCenter">R </th><th class="markdownTableHeadCenter">X </th><th class="markdownTableHeadLeft">interpretation </th></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyLeft">IR is exact </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyCenter">1 </td><td class="markdownTableBodyLeft">IR is closer to NL </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyCenter">1 </td><td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyLeft">IR is closer to NL </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyCenter">1 </td><td class="markdownTableBodyCenter">1 </td><td class="markdownTableBodyLeft">IR is closer to NL </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyCenter">1 </td><td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyLeft">IR is midway between NL and NH </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyCenter">1 </td><td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyCenter">1 </td><td class="markdownTableBodyLeft">IR is closer to NH </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyCenter">1 </td><td class="markdownTableBodyCenter">1 </td><td class="markdownTableBodyCenter">0 </td><td class="markdownTableBodyLeft">IR is closer to NH </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyCenter">1 </td><td class="markdownTableBodyCenter">1 </td><td class="markdownTableBodyCenter">1 </td><td class="markdownTableBodyLeft">IR is closer to NH </td></tr>
</table>
<p>Next lower is effectively truncating the IR (setting GRX = 0b000), while next higher will increment the significand by one.</p>
<ul>
<li>Round to Nearest Even<ul>
<li>If exact chose IR</li>
<li>Otherwise if IR is closer to NL, choose NL</li>
<li>Otherwise if IR is closer to NH, choose NH</li>
<li>Otherwise if IR in midway, choose whichever makes the result even.</li>
</ul>
</li>
<li>Round towards Zero<ul>
<li>If exact chose IR</li>
<li>Otherwise, choose NL</li>
</ul>
</li>
<li>Round towards +Infinity<ul>
<li>If exact chose IR</li>
<li>Otherwise if positive, choose NH</li>
<li>Otherwise if negative, choose NL</li>
</ul>
</li>
<li>Round towards -Infinity<ul>
<li>If exact chose IR</li>
<li>Otherwise if positive, choose NL</li>
<li>Otherwise if negative, choose NH</li>
</ul>
</li>
<li>Round to Nearest Away<ul>
<li>If exact chose IR</li>
<li>Otherwise if G = 0, choose NL</li>
<li>Otherwise if G = 1, choose NH</li>
</ul>
</li>
<li>Round to Odd<ul>
<li>If exact chose IR</li>
<li>Otherwise, choose NL, and if G=1, or R=1, or X=1, set the least significant bit to 1.</li>
</ul>
</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>The coding examples that follow are incomplete. More examples will be provided are more operation are completed and tested.</dd></dl>
<p>The exact coding for rounding modes depends on how the <b>IR</b> is represented in vector registers and this may differ by operation. Conversions, addition, and subtraction tend to use a single vector register where the GRX resides in the low-order bits. While Multiplies generate double quadword results and so use vector register pairs. Here the CL and Fraction bits are right justified in a high_sig vector. While the low-order fraction/GRX bits are left justified in a low_sig vector.</p>
<h4><a class="anchor" id="f128_softfloat_IRRN_0_2_1"></a>
Examples for Round to Nearest Even</h4>
<p>Example for Convert to Quad-precision: </p><div class="fragment"><div class="line">...</div>
<div class="line"><span class="comment">// We add 0x3fff to GRX-bits which may carry into low order sig-bit</span></div>
<div class="line"><span class="comment">// This may result in a carry out from the L-bit into C-bit.</span></div>
<div class="line">q_carry = <a class="code" href="vec__int128__ppc_8h.html#ad7aaadba249ce46c4c94f78df1020da3">vec_addcuq</a> (q_sig, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) RXmask);</div>
<div class="line">q_sig = <a class="code" href="vec__int128__ppc_8h.html#a539de2a4426a84102471306acc571ce8">vec_adduqm</a> (q_sig, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) RXmask);</div>
<div class="line"><span class="comment">// Generate a bool mask from the carry to use in the vsel</span></div>
<div class="line">qcmask = <a class="code" href="vec__int128__ppc_8h.html#af74036e39e72e0f3c29706d30fbb96d1">vec_setb_cyq</a> (q_carry);</div>
<div class="line"><span class="comment">// Two cases; 1) We did carry so shift (double) left 112 bits</span></div>
<div class="line">q_sigc = <a class="code" href="vec__int128__ppc_8h.html#aaa33904ec4de42f54cceab34adb303c5">vec_sldqi</a> (q_carry, q_sig, 112);</div>
<div class="line"><span class="comment">// 2) no carry so shift right 15 bits</span></div>
<div class="line">q_sig = <a class="code" href="vec__int128__ppc_8h.html#ac05c640c6a42770cb95466ff4a2d903c">vec_srqi</a> ((<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) q_sig, 15);</div>
<div class="line"><span class="comment">// Select which based on carry</span></div>
<div class="line">q_sig = (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vec_sel ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) q_sig, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) q_sigc, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) qcmask);</div>
<div class="line"><span class="comment">// Increment the exponent based on the carry</span></div>
<div class="line">q_exp = <a class="code" href="vec__int64__ppc_8h.html#a28052c1907d1f733c9dda8a48039e546">vec_addudm</a> (q_exp, (<a class="code" href="vec__common__ppc_8h.html#a52a773b6353c69a546bdc2e8686a50ec">vui64_t</a>) q_carry);</div>
</div><!-- fragment --><p> This code runs about 16 instructions.</p>
<p>Example for Add/Subtract Quad-precision: </p><div class="fragment"><div class="line"><span class="comment">// Round to nearest even from low_sig bits</span></div>
<div class="line"><span class="comment">// For "round to Nearest, ties to even".</span></div>
<div class="line"><span class="comment">// GRX = 0b001 - 0b011; truncate</span></div>
<div class="line"><span class="comment">// GRX = 0b100 and bit-127 is odd; round up, otherwise truncate</span></div>
<div class="line"><span class="comment">// GRX = 0b100 - 0b111; round up</span></div>
<div class="line"> </div>
<div class="line"><span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> rmask = <a class="code" href="vec__common__ppc_8h.html#ae4520a89b9b5a292a3e647a6d5b712ad">CONST_VINT128_W</a>(0, 0, 0, 3);</div>
<div class="line"><a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> p_rnd;</div>
<div class="line"><span class="comment">// We can simplify by copying the low order fraction bit (p_odd)</span></div>
<div class="line"><span class="comment">// and ADD it to the bit-X. This forces a tie into rounding up</span></div>
<div class="line"><span class="comment">// if the current fraction is odd, making it even.</span></div>
<div class="line"><span class="comment">// This simplifies to (s_sig + rmask + p_odd)</span></div>
<div class="line"><span class="comment">// Rounding will generate a carry into the low order fraction bit</span></div>
<div class="line"><span class="comment">// if and only if GRX > 0b100 or (GRX == 0b100) && (bit-127 == 1)</span></div>
<div class="line"> </div>
<div class="line">p_tmp = <a class="code" href="vec__int128__ppc_8h.html#ac05c640c6a42770cb95466ff4a2d903c">vec_srqi</a> (s_sig, 3);</div>
<div class="line">p_odd = (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vec_and ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) p_tmp, onemask);</div>
<div class="line">s_sig = <a class="code" href="vec__int128__ppc_8h.html#af18b98d2d73f1afbc439e1407c78f305">vec_addecuq</a> (s_sig, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) rmask, p_odd);</div>
<div class="line">q_sig = <a class="code" href="vec__int128__ppc_8h.html#ac05c640c6a42770cb95466ff4a2d903c">vec_srqi</a> (s_sig, 3);</div>
</div><!-- fragment --><p> Adding 3 plus the fraction odd bit to thex GRX-bits generates a carry into the low-order fraction bit for rounding. In this case we use the extend form of add quadword to effect a 3 way add. After rounding convert the <b>IR</b> into a significand by shifting right 3 bits.</p>
<p>Example for Multiply Quad-precision: </p><div class="fragment"><div class="line"><span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> rmask = <a class="code" href="vec__common__ppc_8h.html#ae4520a89b9b5a292a3e647a6d5b712ad">CONST_VINT128_W</a>(0x7fffffff, -1, -1, -1);</div>
<div class="line"><a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> p_rnd;</div>
<div class="line"><span class="comment">// We can simplify by copying the low order bit (p_odd) of high_sig</span></div>
<div class="line"><span class="comment">// and OR it with the bit-X. This forces a tie into rounding up</span></div>
<div class="line"><span class="comment">// if the current fraction is odd, making it even.</span></div>
<div class="line"><span class="comment">// This simplifies to the carry from (low_sig + rmask + p_odd)</span></div>
<div class="line"><span class="comment">// Rounding will generate a carry into p_rnd.</span></div>
<div class="line"><span class="comment">// if and only if GRX > 0b100 or (GRX == 0b100) && (bit-127 == 1)</span></div>
<div class="line">p_odd = (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vec_and ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) high_sig, onemask);</div>
<div class="line">p_rnd = <a class="code" href="vec__int128__ppc_8h.html#af18b98d2d73f1afbc439e1407c78f305">vec_addecuq</a> (low_sig, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) rmask, p_odd);</div>
<div class="line">q_sig = <a class="code" href="vec__int128__ppc_8h.html#a539de2a4426a84102471306acc571ce8">vec_adduqm</a> (high_sig, p_rnd);</div>
</div><!-- fragment --><p> Here we take advantage of <em>uncollected x-bits</em> in low_sig. Until we add the rmask and generate the carry, we can OR/ADD p_odd to any bit in low_sig except the Guard or Round bits. In this case we use the extend/carry form of add quadword to effect a 3 way add and generate the carry/round bit.</p>
<dl class="section note"><dt>Note</dt><dd>In the specific examples above the <b>and</b> with the <em>onemask</em> is not required before use as the VRC operand of <a class="el" href="vec__int128__ppc_8h.html#af18b98d2d73f1afbc439e1407c78f305" title="Vector Add Extended & write Carry Unsigned Quadword.">vec_addecuq()</a>. The instruction internally uses only bit[127] for the carry-in on the extended quadword add.</dd></dl>
<h4><a class="anchor" id="f128_softfloat_IRRN_0_2_2"></a>
Examples for Round toward Zero</h4>
<p>Example for Convert Quadword to Quad-precision: </p><div class="fragment"><div class="line"><span class="comment">// Simplest case, shift right 15 bits</span></div>
<div class="line">q_sig = <a class="code" href="vec__int128__ppc_8h.html#ac05c640c6a42770cb95466ff4a2d903c">vec_srqi</a> ((<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) q_sig, 15);</div>
</div><!-- fragment --><p> This code runs about 3 instructions.</p>
<h4><a class="anchor" id="f128_softfloat_IRRN_0_2_6"></a>
Examples for Round to Odd</h4>
<p>Example for Convert to Quad-precision. </p><div class="fragment"><div class="line"><span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> RXmask = <a class="code" href="vec__common__ppc_8h.html#ae4520a89b9b5a292a3e647a6d5b712ad">CONST_VINT128_W</a> ( 0, 0, 0, 0x7fff);</div>
<div class="line"><a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> q_odd;</div>
<div class="line"><span class="comment">// For "Round to Odd".</span></div>
<div class="line"><span class="comment">// If if G=1, or R=1, or X=1, Set least significant bit to 1.</span></div>
<div class="line"><span class="comment">// Isolate GRX bit then add the mask.</span></div>
<div class="line">q_odd = vec_and ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) q_siq, RXmask);</div>
<div class="line"><span class="comment">// The add will generate a carry into bit 112, for non-zero GRX</span></div>
<div class="line">q_odd = vec_add (q_odd, RXmask);</div>
<div class="line"><span class="comment">// Or this into bit 112 of the q_sig.</span></div>
<div class="line">q_sig = (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vec_or ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) q_sig, q_odd);</div>
<div class="line">q_sig = <a class="code" href="vec__int128__ppc_8h.html#ac05c640c6a42770cb95466ff4a2d903c">vec_srqi</a> ((<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) q_sig, 15);</div>
</div><!-- fragment --><p> This code runs about 6 instructions to load the mask and round=odd.</p>
<p>Example for Add/Subtract Quad-precision: </p><div class="fragment"><div class="line"><span class="comment">// Round to odd from low order GRX-bits</span></div>
<div class="line">p_tmp = <a class="code" href="vec__int128__ppc_8h.html#a070fe972995f3954362835f5b72e5ff6">vec_slqi</a> (s_sig, 125);</div>
<div class="line">p_odd = <a class="code" href="vec__int128__ppc_8h.html#ad7aaadba249ce46c4c94f78df1020da3">vec_addcuq</a> (p_tmp, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) q_ones);</div>
<div class="line">q_sig = <a class="code" href="vec__int128__ppc_8h.html#ac05c640c6a42770cb95466ff4a2d903c">vec_srqi</a> (s_sig, 3);</div>
<div class="line">q_sig = (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vec_or ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) q_sig, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) p_odd);</div>
</div><!-- fragment --><p>Examples for Multiply Quad-precision. For this case we can manipulate low_sig to generate a carry for rounding up/down/odd and then add/subtract/or this carry to high_sig to produce the rounded product significand. For example round-to-odd: </p><div class="fragment"><div class="line"><span class="comment">// Round to odd from low_sig bits</span></div>
<div class="line">p_odd = <a class="code" href="vec__int128__ppc_8h.html#ad7aaadba249ce46c4c94f78df1020da3">vec_addcuq</a> (low_sig, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) q_ones);</div>
<div class="line">q_sig = (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vec_or ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) high_sig, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) p_odd);</div>
</div><!-- fragment --><h2><a class="anchor" id="f128_softfloat_0_0_1"></a>
Quad-Precision compares for POWER8</h2>
<p>IEEE floating-point compare is a bit more complicated than binary integer compare operations. The two main complications are; Not-a-Number (NaN) which IEEE insists are <em>unordered</em>, and signed 0.0 where IEEE insists that -0.0 is equal to +0.0. If you ignore the NaN and signed 0.0 cases you can treat floating-point values as signed magnitude binary integers, and use integer compares and boolean logic. Which looks like this:</p>
<ul>
<li>a =<sup>f</sup> b == (a =<sup>s</sup> b)</li>
<li>a <<sup>f</sup> b == (a >=<sup>s</sup> 0 & a <<sup>s</sup> b) | (a <<sup>s</sup> 0 & a ><sup>u</sup> b)</li>
<li>a <=<sup>f</sup> b == (a >=<sup>s</sup> 0 & a <=<sup>s</sup> b) | (a <<sup>s</sup> 0 & a >=<sup>u</sup> b)</li>
</ul>
<p>Where; =<sup>f</sup>, <<sup>f</sup>, and <=<sup>f</sup> are the desired floating-point compares, =<sup>s</sup>, <<sup>s</sup>, <=<sup>s</sup>, ><sup>s</sup> and >=<sup>s</sup>, are signed integer compares, and =<sup>u</sup>, ><sup>u</sup>, and >=<sup>u</sup> are unsigned integer compares.</p>
<dl class="section see"><dt>See also</dt><dd>"Hacker's Delight, 2nd Edition," Henry S. Warren, Jr, Addison Wesley, 2013. Chapter 17, Floating-point, Section 17-3 Comparing Floating-Point Numbers Using Integer Operations.</dd></dl>
<p>One key implication of this is that we will need signed and unsigned 128-bit compare operations. Instructions for 128-bit integer compares was added for PowerISA 3.1 (POWER10) but we also need to support POWER8/9. The good news is that PowerISA 2.07B (POWER8) includes Vector Add/Subtract Modulo/Carry/Extend Quadword instructions. Specifically Vector Subtract & write Carry Unsigned Quadword can implement all the unsigned ordered (<. <=, >, >=) compares by manipulating the comparand order and evaluating the carry for 0 or 1.</p>
<p>POWER8 also includes vector doubleword integer compare instructions. And the Vector Compare Equal To Unsigned Doubleword instruction can be used with a few additional logical operations to implement 128-bit equal and not equal operations. These operations are already provided by <a class="el" href="vec__int128__ppc_8h.html" title="Header package containing a collection of 128-bit computation functions implemented with PowerISA VMX...">vec_int128_ppc.h</a>.</p>
<p>Some additional observations:</p><ul>
<li>The unsigned compare equal can be used for unsigned or signed integers.</li>
<li>(a >=<sup>s</sup> 0) == ~(a <<sup>s</sup> 0).<ul>
<li>So we only need one compare boolean and the binary NOT.</li>
<li>((a >=<sup>s</sup> 0) & a <<sup>s</sup> b) | (~(a >=<sup>s</sup> 0) & a ><sup>u</sup> b).</li>
<li>Now this starts to look like a vector select operation.</li>
<li>(src1 & ~mask) | (src2 & mask)</li>
</ul>
</li>
<li>(a >=<sup>s</sup> 0) is a special case that only depends on the sign-bit.<ul>
<li>A unsigned compare can be used with a slight change,</li>
<li>Propagating the sign-bit across the (quad)word generates the same boolean. This is the <a class="el" href="vec__int128__ppc_8h.html#af21d01bb19f0ea8605d8c37035837802" title="Vector Set Bool from Signed Quadword.">vec_setb_sq()</a> operation. The __float128 variant is <a class="el" href="vec__f128__ppc_8h.html#a4d5b388cfc9af26418bdd4ec8e4e6f73" title="Vector Set Bool from Quadword Floating-point.">vec_setb_qp()</a></li>
</ul>
</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>The examples that follow, use vector __int128 parameters instead of __binary128 to avoid the hassles of cast incompatibility between scalar __binary128's and vector types. The actual implementations use the xfer functions.</dd></dl>
<div class="fragment"><div class="line"><a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a></div>
<div class="line">test_cmpltf128_v1c (<a class="code" href="vec__common__ppc_8h.html#a3b2bbf9f23490ccca3bdc08bc1dc7831">vi128_t</a> vfa128, <a class="code" href="vec__common__ppc_8h.html#a3b2bbf9f23490ccca3bdc08bc1dc7831">vi128_t</a> vfb128)</div>
<div class="line">{</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> altb, agtb;</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> signbool;</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> result;</div>
<div class="line"> </div>
<div class="line"> <span class="comment">// Replace (vfa >= 0) with (vfa < 0) == vec_setb_qp (vfa)</span></div>
<div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> shift = vec_splat_u8 (7);</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> splat = vec_splat ((<a class="code" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a>) vfa128, <a class="code" href="vec__common__ppc_8h.html#a3975205947785b1745a791ef12256e9a">VEC_BYTE_H</a>);</div>
<div class="line"> signbool = (<a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a>) vec_sra (splat, shift);</div>
<div class="line"> </div>
<div class="line"> altb = <a class="code" href="vec__int128__ppc_8h.html#a82d83d78ff2330205a8d74741b34a1be">vec_cmpltsq</a> (vfa128, vfb128);</div>
<div class="line"> agtb = <a class="code" href="vec__int128__ppc_8h.html#ad4ce43dcbc14fb34623d5ece8073b86e">vec_cmpgtuq</a> ((<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vfa128, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vfb128);</div>
<div class="line"> result = (<a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a>) vec_sel ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>)altb, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>)agtb, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>)signbool);</div>
<div class="line"> <span class="keywordflow">return</span> result;</div>
<div class="line">}</div>
</div><!-- fragment --><p>Now we can tackle the pesky signed 0.0 case. The simplest method is to add another term that test for either a or b is -0.0. This simplifies to just logical a OR b and unsigned compare to -0.0. Which looks like this:</p>
<ul>
<li>a =<sup>f</sup> b == (a =<sup>s</sup> b) | ((a | b) == 0x80000000...0)</li>
<li>a <<sup>f</sup> b == (a >=<sup>s</sup> 0 & a <<sup>s</sup> b) | ((a <<sup>s</sup> 0 & a ><sup>u</sup> b) & ((a | b) != 0x80000000...0))</li>
<li>a <=<sup>f</sup> b == (a >=<sup>s</sup> 0 & a <=<sup>s</sup> b) | ((a <<sup>s</sup> 0 & a >=<sup>u</sup> b) | ((a | b) == 0x80000000...0))</li>
</ul>
<p>Again we can replace signed compares (a >= 0) and (a < 0) with a single <a class="el" href="vec__f128__ppc_8h.html#a4d5b388cfc9af26418bdd4ec8e4e6f73" title="Vector Set Bool from Quadword Floating-point.">vec_setb_qp()</a> and simplify the boolean logic by using vec_sel(). For the ((a | b) != 0x80000000...0) term we can save an instruction by replacing <a class="el" href="vec__int128__ppc_8h.html#a186d0b94bbc652e700ab4e1733b9524c" title="Vector Compare Not Equal Unsigned Quadword.">vec_cmpneuq()</a> with <a class="el" href="vec__int128__ppc_8h.html#a7197cd5c6e946211f2718b5e8464cdc0" title="Vector Compare Equal Unsigned Quadword.">vec_cmpequq()</a> and replacing the AND operation with AND compliment. </p><div class="fragment"><div class="line"><a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a></div>
<div class="line">test_cmpltf128_v2c (<a class="code" href="vec__common__ppc_8h.html#a3b2bbf9f23490ccca3bdc08bc1dc7831">vi128_t</a> vfa128, <a class="code" href="vec__common__ppc_8h.html#a3b2bbf9f23490ccca3bdc08bc1dc7831">vi128_t</a> vfb128)</div>
<div class="line">{</div>
<div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> signmask = <a class="code" href="vec__common__ppc_8h.html#ae4520a89b9b5a292a3e647a6d5b712ad">CONST_VINT128_W</a> (0x80000000, 0, 0, 0);</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> altb, agtb, nesm;</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> or_ab;</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> signbool;</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> result;</div>
<div class="line"> </div>
<div class="line"> <span class="comment">// Replace (vfa >= 0) with (vfa < 0) == vec_setb_qp (vfa)</span></div>
<div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> shift = vec_splat_u8 (7);</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> splat = vec_splat ((<a class="code" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a>) vfa128, <a class="code" href="vec__common__ppc_8h.html#a3975205947785b1745a791ef12256e9a">VEC_BYTE_H</a>);</div>
<div class="line"> signbool = (<a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a>) vec_sra (splat, shift);</div>
<div class="line"> </div>
<div class="line"> altb = <a class="code" href="vec__int128__ppc_8h.html#a82d83d78ff2330205a8d74741b34a1be">vec_cmpltsq</a> (vfa128, vfb128);</div>
<div class="line"> agtb = <a class="code" href="vec__int128__ppc_8h.html#ad4ce43dcbc14fb34623d5ece8073b86e">vec_cmpgtuq</a> ((<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vfa128, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) vfb128);</div>
<div class="line"> </div>
<div class="line"> or_ab = vec_or ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) vfa128, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) vfb128 );</div>
<div class="line"> <span class="comment">// For ne compare eq and and compliment</span></div>
<div class="line"> nesm = <a class="code" href="vec__int128__ppc_8h.html#a7197cd5c6e946211f2718b5e8464cdc0">vec_cmpequq</a> ((<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) or_ab, (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a>) signmask);</div>
<div class="line"> agtb = (<a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a>) vec_andc ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) agtb, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>) nesm);</div>
<div class="line"> <span class="comment">// select altb for 0's and agtb for 1's</span></div>
<div class="line"> <span class="keywordflow">return</span> (<a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a>) vec_sel ((<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>)altb, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>)agtb, (<a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a>)signbool);</div>
<div class="line">}</div>
</div><!-- fragment --><p> This sequence runs 27 instructions when you include the constant loads.</p>
<p>An alternative compare method converts both floating-point values in a way that a single (unsigned) integer compare can be used.</p>
<div class="fragment"><div class="line"><span class="comment">// for each comparand</span></div>
<div class="line"> <span class="keywordflow">if</span> (n >= 0)</div>
<div class="line"> n = n + 0x80000000;</div>
<div class="line"> <span class="keywordflow">else</span></div>
<div class="line"> n = -n;</div>
<div class="line"><span class="comment">// Use unsigned integer comparison</span></div>
</div><!-- fragment --><p> An interesting feature of this method is that +0.0 becomes (0x00000000 + 0x80000000 = 0x80000000) and -0.0 becomes (0x80000000 - 0x80000000 = 0x80000000) which effectively converts any -0.0 into +0.0 for comparison. Signed 0.0 solved.</p>
<p>Another optimization converts (n = n + 0x80000000) to (n = n XOR 0x80000000). Gives the same result and for POWER8 a vec_xor() is 2 cycles latency vs 4 cycles for _vec_adduqm().</p>
<div class="fragment"><div class="line"><a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a></div>
<div class="line">test_cmpltf128_v3d (<a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> vfa128, <a class="code" href="vec__common__ppc_8h.html#aaf7a8e92d8ba681dac3d2ec3259c0820">vui128_t</a> vfb128)</div>
<div class="line">{</div>
<div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> zero = <a class="code" href="vec__common__ppc_8h.html#ae4520a89b9b5a292a3e647a6d5b712ad">CONST_VINT128_W</a> (0, 0, 0, 0);</div>
<div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#a2ff4a776536870e01b7c9e454586544b">vui32_t</a> signmask = <a class="code" href="vec__common__ppc_8h.html#ae4520a89b9b5a292a3e647a6d5b712ad">CONST_VINT128_W</a> (0x80000000, 0, 0, 0);</div>
<div class="line"> <span class="keyword">const</span> <a class="code" href="vec__common__ppc_8h.html#aed458e4755a6589049b936cf9f24f6f8">vui8_t</a> shift = vec_splat_u8 (7);</div>
<div class="line"> </div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> result;</div>
<div class="line"> <a class="code" href="vec__common__ppc_8h.html#a16cdf519bbbf190c311bd27d3e254208">vb128_t</a> age0, bge0;</div>