Optimisation of SRAM memory pinout for subsequent BlackIce revisions

[folknology]

I notice @lawrie has a desire for certain signals RAM_OE and WE being in different groups to enable use of inverted clock function in IO section. However the linked solution ends up using the DDR mode in order to solve the timing issues in another way which may well be more flexible. This therefore is a temporary place holder discussions about any potential optimisations of the SRAM-Ice40 current pinout choices including issues described in the link. Feel free to discuss..