{"payload":{"header_redesign_enabled":false,"results":[{"id":"604872623","archived":false,"color":"#DAE1C2","followers":0,"has_funding_file":false,"hl_name":"nbathula16/SV-Project","hl_trunc_description":"32-bit Single Precision Floating point Multiplication","language":"SystemVerilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":604872623,"name":"SV-Project","owner_id":117477359,"owner_login":"nbathula16","updated_at":"2023-03-23T19:32:57.002Z","has_issues":true}},"sponsorable":false,"topics":["coverage","randomization","constraint","floating-point","testbench","normalization","multiplier","conditional-compilation","directed-testing"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":56,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Anbathula16%252FSV-Project%2B%2Blanguage%253ASystemVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/nbathula16/SV-Project/star":{"post":"fmxO6b_Cjn-BMLDeK5iZ-THcnAHs6ggECRogQbZJqOM4_hSA_-uNbF2ViP4t65yzhgGBpWBTY0aKfXH4PcCfkA"},"/nbathula16/SV-Project/unstar":{"post":"n_qrTmEU4Ozisa5oHb191TFTnFdHPEaaK-TupdAvWTPj3YK8ArlSyfG3JoJYTy-Imb-xbn3KR_S9OWl4k7RVNA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"v6ungbBj7oiMBItIu1lBOF-M0n_XRZj_iThEnPV1UVpcDgR-LKuvAAguqObhIm0rTRKJYwD4eNQ99DlbHtQQpA"}}},"title":"Repository search results"}