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VHDL-2019: Private type resolution #1016

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bpadalino opened this issue Oct 11, 2024 · 1 comment
Open

VHDL-2019: Private type resolution #1016

bpadalino opened this issue Oct 11, 2024 · 1 comment
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@bpadalino
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I get an error about different types not matching with this:

package test_pkg is
  generic (
    type t ;
  ) ;

    type data_array is array(0 to 1, 0 to 1) of t ;

end package ;

entity test_entity is
  generic (
    type a is array(natural range <>) of type is private ;
    --type a is array(0 to 1) of type is private ; -- errors?
    function "<"(l, r : in a'element) return boolean is <> ;
    package pkg is new work.test_pkg generic map (t => a'element) -- t needs to be the same type as a'element
  ) ;
  port (
    ins     :   in  a ;
    outs    :   out a
  ) ;
end entity ;

architecture arch of test_entity is

    use pkg.all ;
    signal data : data_array ;

    -- works
    --type data_array is array(0 to 1, 0 to 1) of a'element ; -- same declaration as in the test_pkg
    --signal data : data_array ;

begin

    stage0 : for element in 0 to 1 generate
        process(ins)
        begin
            if ins(0) < ins(1) then
                data(0, 0) <= ins(1) ;
                data(0, 1) <= ins(0) ;
            else
                data(0, 0) <= ins(1) ;
                data(0, 1) <= ins(0) ;
            end if ;
        end process ;
    end generate ;

end architecture ;
** Error: type of value (an anonymous type) does not match type of target T
    > test.vhdl:38
    |
 38 |                 data(0, 0) <= ins(1) ;
    |                 ^^^^^^^^^^^^^^^^^^^^^^

There is also an error when I try to constrain the array type a bit more in the declaration. Riviera PRO is fine with it, but nvc says the 0 token is unexpected.

Am I abusing something here, or should this work?

@nickg nickg added the 2019 label Oct 13, 2024
@nickg
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nickg commented Oct 13, 2024

There is also an error when I try to constrain the array type a bit more in the declaration. Riviera PRO is fine with it, but nvc says the 0 token is unexpected.

Technically this isn't correct syntax, see https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/58

Although I think the intent of the LRM is clear, but I haven't implemented that yet.

Am I abusing something here, or should this work?

Gosh, I don't really know. I can see why you would expect that to work, but currently the generic map on the generic package is only used to check compatibility when instantiating the entity, not when analysing the architecture.

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