Implementing Reliability for Instruction Cache (L0, L1, RO) #2
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…e problems with faulty_data signal
…e, fixed tag invalidation stage from tag stage
…xed problem with reading all zeros
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Reliability for instruction cache
Changelog
Implemented parity checks using error detecting codes in the L1 (snitch_icache_lookup_serial) and L0 (snitch_icache_l0) cache.
Added fault injection scripts to test the read-only cache and the MemPool system.
Added
Changed
Fixed
(Reference to issues, labels, and related merge requests)
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