-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathdff.py
155 lines (130 loc) · 5.51 KB
/
dff.py
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
##########################################################
# #
# D-Flip Flop Layout Generator #
# Contributors: T. Shin, S. Park, Y. Oh, T. Kang #
# Last Update: 2022-05-27 #
# #
##########################################################
import numpy as np
import pprint
import laygo2
import laygo2.interface
import laygo2_tech as tech
# Parameter definitions #############
# Design Variables
cell_type = 'dff'
nf = 2
# Templates
tpmos_name = 'pmos'
tnmos_name = 'nmos'
# Grids
pg_name = 'placement_basic'
r12_name = 'routing_12_cmos'
r23_name = 'routing_23_cmos'
r34_name = 'routing_34_basic'
# Design hierarchy
libname = 'logic_generated'
# End of parameter definitions ######
# Generation start ##################
# 1. Load templates and grids.
print("Load templates")
templates = tech.load_templates()
tpmos, tnmos = templates[tpmos_name], templates[tnmos_name]
tlib = laygo2.interface.yaml.import_template(filename='logic_generated_templates.yaml')
# print(templates[tpmos_name], templates[tnmos_name], sep="\n") # Uncomment if you want to print templates information.
print("Load grids")
grids = tech.load_grids(templates=templates)
pg, r12, r23, r34 = grids[pg_name], grids[r12_name], grids[r23_name], grids[r34_name]
# print(grids[pg_name], grids[r12_name], grids[r23_name], grids[r34_name], sep="\n") # Uncomment if you want to print grids information.
cellname = cell_type+'_'+str(nf)+'x'
print('--------------------')
print('Now Creating '+cellname)
# 2. Create a design hierarchy
lib = laygo2.object.database.Library(name=libname)
dsn = laygo2.object.database.Design(name=cellname, libname=libname)
lib.append(dsn)
# 3. Create istances.
print("Create instances")
inv0 = tlib['inv_'+str(nf)+'x'].generate(name='inv0')
inv1 = tlib['inv_'+str(nf)+'x'].generate(name='inv1')
inv2 = tlib['inv_'+str(nf)+'x'].generate(name='inv2')
inv3 = tlib['inv_'+str(nf)+'x'].generate(name='inv3')
tinv0 = tlib['tinv_'+str(nf)+'x'].generate(name='tinv0')
tinv1 = tlib['tinv_'+str(nf)+'x'].generate(name='tinv1')
tinv_small0 = tlib['tinv_small_1x'].generate(name='tinv_small0')
tinv_small1 = tlib['tinv_small_1x'].generate(name='tinv_small1')
# 4. Place instances.
dsn.place(grid=pg, inst=inv0, mn=[0,0])
dsn.place(grid=pg, inst=inv1, mn=pg.mn.bottom_right(inv0))
dsn.place(grid=pg, inst=tinv0, mn=pg.mn.bottom_right(inv1))
dsn.place(grid=pg, inst=tinv_small0, mn=pg.mn.bottom_right(tinv0))
dsn.place(grid=pg, inst=inv2, mn=pg.mn.bottom_right(tinv_small0))
dsn.place(grid=pg, inst=tinv1, mn=pg.mn.bottom_right(inv2))
dsn.place(grid=pg, inst=tinv_small1, mn=pg.mn.bottom_right(tinv1))
dsn.place(grid=pg, inst=inv3, mn=pg.mn.bottom_right(tinv_small1))
# 5. Create and place wires.
print("Create wires")
# ICLK
_mn = [r34.mn(inv1.pins['O'])[0], r34.mn(tinv_small1.pins['ENB'])[0]]
_track = [None, r34.mn(inv1.pins['O'])[0,1]-2]
mn_list=[]
mn_list.append(r34.mn(inv1.pins['O'])[0])
mn_list.append(r34.mn(tinv0.pins['ENB'])[0])
mn_list.append(r34.mn(tinv1.pins['EN'])[0])
mn_list.append(r34.mn(tinv_small0.pins['EN'])[0])
mn_list.append(r34.mn(tinv_small1.pins['ENB'])[0])
dsn.route_via_track(grid=r34, mn=mn_list, track=_track)
# ICLKB
_track[1] += 1
mn_list=[]
mn_list.append(r34.mn(inv0.pins['O'])[0])
mn_list.append(r34.mn(inv1.pins['I'])[0])
mn_list.append(r34.mn(tinv0.pins['EN'])[0])
mn_list.append(r34.mn(tinv1.pins['ENB'])[0])
mn_list.append(r34.mn(tinv_small0.pins['ENB'])[0])
mn_list.append(r34.mn(tinv_small1.pins['EN'])[0])
dsn.route_via_track(grid=r34, mn=mn_list, track=_track)
# Front LATCH
_track[1] += 1
mn_list=[]
mn_list.append(r34.mn(inv2.pins['I'])[0])
mn_list.append(r34.mn(tinv0.pins['O'])[0])
mn_list.append(r34.mn(tinv_small0.pins['O'])[0])
dsn.route_via_track(grid=r34, mn=mn_list, track=_track)
# Back LATCH
mn_list=[]
mn_list.append(r34.mn(inv3.pins['I'])[0])
mn_list.append(r34.mn(tinv1.pins['O'])[0])
mn_list.append(r34.mn(tinv_small1.pins['O'])[0])
dsn.route_via_track(grid=r34, mn=mn_list, track=_track)
# LATCH
_track[1] += 1
mn_list=[]
mn_list.append(r34.mn(inv2.pins['O'])[0])
mn_list.append(r34.mn(tinv1.pins['I'])[0])
mn_list.append(r34.mn(tinv_small0.pins['I'])[0])
dsn.route_via_track(grid=r34, mn=mn_list, track=_track)
# OUT
mn_list=[]
mn_list.append(r34.mn(inv3.pins['O'])[0])
mn_list.append(r34.mn(tinv_small1.pins['I'])[0])
dsn.route_via_track(grid=r34, mn=mn_list, track=_track)
# VSS
rvss0 = dsn.route(grid=r12, mn=[r12.mn.bottom_left(inv0), r12.mn.bottom_right(inv3)])
# VDD
rvdd0 = dsn.route(grid=r12, mn=[r12.mn.top_left(inv0), r12.mn.top_right(inv3)])
# 6. Create pins.
pin0 = dsn.pin(name='I', grid=r23, mn=r23.mn.bbox(tinv0.pins['I']))
pclk0 = dsn.pin(name='CLK', grid=r23, mn=r23.mn.bbox(inv0.pins['I']))
pout0 = dsn.pin(name='O', grid=r23, mn=r23.mn.bbox(inv3.pins['O']))
pvss0 = dsn.pin(name='VSS', grid=r12, mn=r12.mn.bbox(rvss0))
pvdd0 = dsn.pin(name='VDD', grid=r12, mn=r12.mn.bbox(rvdd0))
# 7. Export to physical database.
print("Export design")
print("")
laygo2.interface.bag.export(lib, filename=libname+'_'+cellname+'.il', cellname=None, scale=1e-3, reset_library=False, tech_library=tech.name)
# Filename example: ./laygo2_generators_private/logic/skill/logic_generated_dff_2x.il
# 8. Export to a template database file.
nat_temp = dsn.export_to_template()
laygo2.interface.yaml.export_template(nat_temp, filename=libname+'_templates.yaml', mode='append')
# Filename example: ./laygo2_generators_private/logic/logic_generated_templates.yaml