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<div class="document" id="kvcordic-user-manual">
<h1 class="title">kvcordic user manual</h1>
<table border="1" class="docutils">
<colgroup>
<col width="25%" />
<col width="75%" />
</colgroup>
<tbody valign="top">
<tr><td><strong>Title</strong></td>
<td>kvcordic (Multi-function, universal, fixed-point CORDIC)</td>
</tr>
<tr><td><strong>Author</strong></td>
<td>Nikolaos Kavvadias (C) 2010-2022</td>
</tr>
<tr><td><strong>Contact</strong></td>
<td><a class="reference external" href="mailto:nikos@nkavvadias.com">nikos@nkavvadias.com</a></td>
</tr>
<tr><td><strong>Website</strong></td>
<td><a class="reference external" href="http://www.nkavvadias.com">http://www.nkavvadias.com</a></td>
</tr>
<tr><td><strong>Release Date</strong></td>
<td>20 February 2022</td>
</tr>
<tr><td><strong>Version</strong></td>
<td>1.1.0</td>
</tr>
<tr><td><strong>Rev. history</strong></td>
<td> </td>
</tr>
<tr><td><strong>v1.1.0</strong></td>
<td><p class="first">2022-02-20</p>
<p class="last">Synthesize cordic.c with Vitis HLS.</p>
</td>
</tr>
<tr><td><strong>v1.0.1</strong></td>
<td><p class="first">2014-09-26</p>
<p class="last">Updated file organization for Github; changed README to
README.rst; CORDIC-EULA.txt to LICENSE.</p>
</td>
</tr>
<tr><td><strong>v1.0.0</strong></td>
<td><p class="first">2013-02-22</p>
<p class="last">Updated architecture. A single cycle is now needed per
iteration. Documentation updated to RestructuredText.
Logic synthesis scripts updated for Xilinx ISE/XST 14.6.</p>
</td>
</tr>
<tr><td><strong>v0.0.2</strong></td>
<td><p class="first">2010-11-08</p>
<p class="last">A universal CORDIC algorithm is now specified. The new
version uses the full CORDIC interface (X,Y,Z) for input
and output. Q2.14 (16-bit) signed fixed-point arithmetic
is emulated through the use of integers.</p>
</td>
</tr>
<tr><td><strong>v0.0.1</strong></td>
<td><p class="first">2010-11-04</p>
<p class="last">The CORDIC-EULA.txt has been added.</p>
</td>
</tr>
<tr><td><strong>v0.0.0</strong></td>
<td><p class="first">2010-11-01</p>
<p class="last">Initial release.</p>
</td>
</tr>
</tbody>
</table>
<div class="section" id="introduction">
<h1>1. Introduction</h1>
<p><tt class="docutils literal">kvcordic</tt> is a collection of files comprising an implementation of a
universal CORDIC algorithm (rotation/vectoring direction, circular/linear/
hyperbolic mode) high-level synthesis benchmark by Nikolaos Kavvadias. All
design files except <tt class="docutils literal">cordic.c</tt>, <tt class="docutils literal">cordic.nac</tt>, and <tt class="docutils literal">cordic_test_data.txt</tt>
have been automatically generated. The original <tt class="docutils literal">cordic.vhd</tt> has been
optimized via (manual) operation chaining. <tt class="docutils literal">operpack.vhd</tt>,
<tt class="docutils literal">std_logic_textio.vhd</tt> are simulation/synthesis library files, copyrighted by
their respective authors.</p>
<p>IMPORTANT: Please go through the license agreement (<tt class="docutils literal">LICENSE</tt>) to ensure
proper use of the CORDIC IP CORE.</p>
</div>
<div class="section" id="file-listing">
<h1>2. File listing</h1>
<p>The CORDIC IP core distribution includes the following files:</p>
<table border="1" class="docutils">
<colgroup>
<col width="30%" />
<col width="70%" />
</colgroup>
<tbody valign="top">
<tr><td>/kvcordic</td>
<td>Top-level directory</td>
</tr>
<tr><td>AUTHORS</td>
<td>List of authors.</td>
</tr>
<tr><td>LICENSE</td>
<td>End-user license agreement for using <tt class="docutils literal">kvcordic</tt>.</td>
</tr>
<tr><td>README.rst</td>
<td>This file.</td>
</tr>
<tr><td>README.html</td>
<td>HTML version of README.</td>
</tr>
<tr><td>README.pdf</td>
<td>PDF version of README.</td>
</tr>
<tr><td>VERSION</td>
<td>Current version of the CORDIC IP cores.</td>
</tr>
<tr><td>rst2docs.sh</td>
<td>Bash script for generating the HTML and PDF versions.</td>
</tr>
<tr><td>/bench/vhdl</td>
<td>Benchmarks VHDL directory</td>
</tr>
<tr><td>cordic_tb.vhd</td>
<td>Automatically-generated VHDL testbench file.</td>
</tr>
<tr><td>/doc</td>
<td>Documentation directory</td>
</tr>
<tr><td>/rtl/vhdl</td>
<td>RTL source code directory for the IP core</td>
</tr>
<tr><td>cordic.vhd</td>
<td>Automatically-generated VHDL design file
(hand-optimized for operation chaining).</td>
</tr>
<tr><td>cordic_cdt_pkg.vhd</td>
<td>Package containing declarations.</td>
</tr>
<tr><td>/sim/rtl_sim</td>
<td>RTL simulation files directory</td>
</tr>
<tr><td>/sim/rtl_sim/bin</td>
<td>RTL simulation scripts directory</td>
</tr>
<tr><td>cordic.mk</td>
<td>Unix/Cygwin makefile for running a GHDL simulation.</td>
</tr>
<tr><td>/sim/rtl_sim/out</td>
<td>Dumps and other useful output from RTL simulation</td>
</tr>
<tr><td>cordic_alg_test_res-
ults.txt</td>
<td>Check this file for output.</td>
</tr>
<tr><td>/sim/rtl_sim/run</td>
<td>Files for running RTL simulations</td>
</tr>
<tr><td>cordic.sh</td>
<td>Unix/Cygwin bash shell script for running a GHDL
simulation.</td>
</tr>
<tr><td>cordic_test_data.txt</td>
<td>Reference vectors.</td>
</tr>
<tr><td>/sim/rtl_sim/vhdl</td>
<td>VHDL source files used for running RTL simulations</td>
</tr>
<tr><td>operpack.vhd</td>
<td>Reduced version of Nikolaos Kavvadias' operator
library.</td>
</tr>
<tr><td>std_logic_textio.vhd</td>
<td>Modified version of a testbench-related package.</td>
</tr>
<tr><td>/sw</td>
<td>Software utilities</td>
</tr>
<tr><td>cordic.c</td>
<td>Reference C implementation for test vector
generation.</td>
</tr>
<tr><td>cordic.dot</td>
<td>CDFG of the cordic procedure as a Graphviz file.</td>
</tr>
<tr><td>cordic.dot.png</td>
<td>PNG image for the above.</td>
</tr>
<tr><td>cordic.nac</td>
<td>The NAC description of the CORDIC application.</td>
</tr>
<tr><td>cordic-flp.txt</td>
<td>Comparison of fixed-point to floating-point CORDIC
(using calls to the <tt class="docutils literal">math</tt> C library) results.</td>
</tr>
<tr><td>/syn/vitis</td>
<td>Synthesis files for use with Xilinx Vitis</td>
</tr>
<tr><td>/syn/vitis/bin</td>
<td>Synthesis scripts directory</td>
</tr>
<tr><td>vhls.tcl</td>
<td>Pass Tcl directives to Vitis HLS.</td>
</tr>
<tr><td>/syn/vitis/run</td>
<td>Files for running synthesis</td>
</tr>
<tr><td>vsyn.sh</td>
<td>Bash shell script for synthesizing <tt class="docutils literal">cordic()</tt> with
Vitis HLS.</td>
</tr>
<tr><td>/syn/xise</td>
<td>Synthesis files for use with Xilinx ISE</td>
</tr>
<tr><td>/syn/xise/bin</td>
<td>Synthesis scripts directory</td>
</tr>
<tr><td>xst.mk</td>
<td>Standard Makefile for command-line usage of ISE.</td>
</tr>
<tr><td>/syn/xise/log</td>
<td>Generated log files from the synthesis process</td>
</tr>
<tr><td>cordic-xst14.6.txt</td>
<td>Synthesis report from Xilinx ISE (XST) 14.6.</td>
</tr>
<tr><td>/syn/xise/run</td>
<td>Files for running synthesis</td>
</tr>
<tr><td>syn.sh</td>
<td>Bash shell script for synthesizing <tt class="docutils literal">kvcordic</tt>
architectures with ISE.</td>
</tr>
</tbody>
</table>
</div>
<div class="section" id="usage">
<h1>3. Usage</h1>
<ol class="arabic simple">
<li>Run the shell script from a Unix/Linux/Cygwin command line.</li>
</ol>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ ./cordic.sh</tt></div>
</div>
<p>After this process, the <tt class="docutils literal">cordic_alg_test_results.txt</tt> file is generated
containing simulation results. The GHDL simulation will also generate
a VCD (waveform) file that can be opened with GTKwave:</p>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ gtkwave cordic_fsmd.vcd</tt></div>
</div>
<p>2. Create, build and run a Modelsim project with the following files (in
this order):</p>
<pre class="literal-block">
operpack.vhd
std_logic_textio.vhd
cordic_cdt_pkg.vhd
ram.vhd
cordic.vhd
cordic_tb.vhd
</pre>
</div>
<div class="section" id="synthesis">
<h1>4. Synthesis</h1>
<p>The CORDIC IP cores distribution includes scripts for logic synthesis automation
supporting Xilinx ISE. The corresponding synthesis script can be edited in order
to specify the following for adapting to the user's setup:</p>
<ul class="simple">
<li><tt class="docutils literal">XDIR</tt>: the path to the <tt class="docutils literal">/bin</tt> subdirectory of the Xilinx ISE/XST
installation where the <tt class="docutils literal">xst.exe</tt> executable is placed</li>
<li><tt class="docutils literal">arch</tt>: specific FPGA architecture (device family) to be used for synthesis</li>
<li><tt class="docutils literal">part</tt>: specific FPGA part (device) to be used for synthesis</li>
</ul>
<div class="section" id="running-the-synthesis-script">
<h2>4.1. Running the synthesis script</h2>
<p>For running the Xilinx ISE synthesis tool, change directory to the
<tt class="docutils literal">/syn/xise/run</tt> subdirectory from the top-level directory of CORDIC:</p>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ ./syn/xise/run</tt></div>
</div>
<p>and execute the corresponding script (for synthesizing <tt class="docutils literal">hwlu</tt>):</p>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ ./syn.sh</tt></div>
</div>
<p>The synthesis procedure invokes several Xilinx ISE command-line tools for logic
synthesis as described in the corresponding Makefile, found in the
the <tt class="docutils literal">/syn/xise/bin</tt> subdirectory.</p>
<p>Typically, this process includes the following:</p>
<ul class="simple">
<li>Generation of the <tt class="docutils literal">*.xst</tt> synthesis script file.</li>
<li>Generation of the <tt class="docutils literal">*.ngc</tt> gate-level netlist file in NGC format.</li>
<li>Building the corresponding <tt class="docutils literal">*.ngd</tt> file.</li>
<li>Performing mapping using <tt class="docutils literal">map</tt> which generates the corresponding <tt class="docutils literal">*.ncd</tt>
file.</li>
<li>Place-and-routing using <tt class="docutils literal">par</tt> which updates the corresponding <tt class="docutils literal">*.ncd</tt>
file.</li>
<li>Tracing critical paths using <tt class="docutils literal">trce</tt> for reoptimizing the <tt class="docutils literal">*.ncd</tt> file.</li>
<li>Bitstream generation (<tt class="docutils literal">*.bit</tt>) using <tt class="docutils literal">bitgen</tt>, however with unused pins.</li>
</ul>
<p>Finally, the <tt class="docutils literal">cordic.bit</tt> bitstream file is produced.</p>
</div>
</div>
<div class="section" id="prerequisites">
<h1>5. Prerequisites</h1>
<ul>
<li><p class="first">Standard UNIX-based tools (tested with gcc-4.6.2 on MinGW/x86) [optional if
you use Modelsim].</p>
<ul class="simple">
<li>make</li>
<li>bash (shell)</li>
</ul>
<p>For this reason, MinGW (<a class="reference external" href="http://www.mingw.org">http://www.mingw.org</a>) or Cygwin
(<a class="reference external" href="http://sources.redhat.com/cygwin">http://sources.redhat.com/cygwin</a>) are suggested, since POSIX emulation
environments of sufficient completeness.</p>
</li>
<li><p class="first">GHDL simulator (<a class="reference external" href="http://ghdl.free.fr">http://ghdl.free.fr</a>) [optional if you use Modelsim].
Provides the <tt class="docutils literal">ghdl</tt> executable (has several Windows versions, with
0.29.1 and 0.31 being the latest). It also installs GTKwave on Windows.
Note that the latest version (0.31) from
<a class="reference external" href="http://sourceforge.net/project/ghdl-updates/">http://sourceforge.net/project/ghdl-updates/</a> does not include GTKwave.</p>
</li>
<li><p class="first">Xilinx ISE (free ISE webpack is available from the Xilinx website):
<a class="reference external" href="http://www.xilinx.com">http://www.xilinx.com</a>)
The 14.6 version on Windows 7/64-bit is known to work.</p>
</li>
</ul>
</div>
</div>
</body>
</html>