diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 546bb6b3a..26d5625c6 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -84,6 +84,7 @@ jobs: with: path: ${{ env.CACHE_DIR }} key: linux-build-test-cpp-asserts-manylinux-v2-${{ github.sha }} + test_linux: runs-on: amd7940hs needs: build_test_linux diff --git a/.gitmodules b/.gitmodules index 3d0b202f2..a4b6a7412 100644 --- a/.gitmodules +++ b/.gitmodules @@ -6,10 +6,6 @@ path = third_party/mlir-air url = https://github.com/nod-ai/mlir-air.git shallow = true -[submodule "third_party/mlir-aie"] - path = third_party/mlir-aie - url = https://github.com/nod-ai/mlir-aie.git - shallow = true [submodule "third_party/aie-rt"] path = third_party/aie-rt url = https://github.com/Xilinx/aie-rt.git diff --git a/compiler/plugins/target/AMD-AIE/aie/AIE.td b/compiler/plugins/target/AMD-AIE/aie/AIE.td new file mode 100644 index 000000000..94f3c686f --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/AIE.td @@ -0,0 +1,19 @@ +// Copyright 2024 The IREE Authors +// +// Licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +#ifndef AIE_BASE +#define AIE_BASE + +include "mlir/IR/OpBase.td" + +def AIE_Dialect : Dialect { + let name = "aie"; + let cppNamespace = "::xilinx::AIE"; + let useDefaultTypePrinterParser = 1; + let useDefaultAttributePrinterParser = 1; +} + +#endif // AIE_BASE diff --git a/compiler/plugins/target/AMD-AIE/aie/AIEAttrs.td b/compiler/plugins/target/AMD-AIE/aie/AIEAttrs.td new file mode 100644 index 000000000..9d309dbdf --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/AIEAttrs.td @@ -0,0 +1,85 @@ +// Copyright 2024 The IREE Authors +// +// Licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +#ifndef AIE_ATTRS +#define AIE_ATTRS + +include "AIE.td" + +include "mlir/IR/AttrTypeBase.td" +include "mlir/IR/EnumAttr.td" + +def LockAction: I32EnumAttr<"LockAction", "lock acquire/release", + [ + I32EnumAttrCase<"Acquire", 0>, + I32EnumAttrCase<"AcquireGreaterEqual", 2>, + I32EnumAttrCase<"Release", 1>, + ]> { + + let cppNamespace = "xilinx::AIE"; +} + +def LockBlocking: I32EnumAttr<"LockBlocking", "lock operation is blocking", + [ + I32EnumAttrCase<"NonBlocking", 0>, + I32EnumAttrCase<"Blocking", 1> + ]> { + + let cppNamespace = "xilinx::AIE"; +} + +def ObjectFifoPort: I32EnumAttr<"ObjectFifoPort", + "Ports of an object FIFO", + [ + I32EnumAttrCase<"Produce", 0>, + I32EnumAttrCase<"Consume", 1> + ] + > { + let cppNamespace = "xilinx::AIE"; +} + +def BDDimLayoutAttr : AttrDef { + let mnemonic = "bd_dim_layout"; + let parameters = (ins + "uint16_t" : $size, + "uint32_t" : $stride + ); + + let assemblyFormat = "`<` struct(params) `>`"; +} + +def BDDimLayoutArrayAttr : ArrayOfAttr< + /*dialect*/AIE_Dialect, + /*attrName*/"BDDimLayoutArray", + /*attrMnemonic*/"bd_dim_layout_array", + /*eltName*/BDDimLayoutAttr.cppClassName +>; + +def BDDimLayoutArrayArrayAttr : ArrayOfAttr< + /*dialect*/AIE_Dialect, + /*attrName*/"BDDimLayoutArrayArray", + /*attrMnemonic*/"bd_dim_layout_array_array", + /*eltName*/BDDimLayoutArrayAttr.cppClassName +>; + +def BDPadLayoutAttr : AttrDef { + let mnemonic = "bd_pad_layout"; + let parameters = (ins + "uint16_t" : $const_pad_before, + "uint16_t" : $const_pad_after + ); + + let assemblyFormat = "`<` struct(params) `>`"; +} + +def BDPadLayoutArrayAttr : ArrayOfAttr< + /*dialect*/AIE_Dialect, + /*attrName*/"BDPadLayoutArray", + /*attrMnemonic*/"bd_pad_layout_array", + /*eltName*/BDPadLayoutAttr.cppClassName +>; + +#endif // AIE_ATTRS diff --git a/compiler/plugins/target/AMD-AIE/aie/AIEDialect.cpp b/compiler/plugins/target/AMD-AIE/aie/AIEDialect.cpp new file mode 100644 index 000000000..d790c074f --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/AIEDialect.cpp @@ -0,0 +1,413 @@ +// Copyright 2024 The IREE Authors +// +// Licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +#include "AIEDialect.h" + +#include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/TypeSwitch.h" +#include "mlir/IR/DialectImplementation.h" +#include "mlir/IR/OpDefinition.h" +#include "mlir/Interfaces/FoldInterfaces.h" +#include "mlir/Transforms/InliningUtils.h" + +using namespace mlir; +using namespace xilinx::AIE; + +#include "aie/AIEDialect.cpp.inc" + +namespace xilinx::AIE { +std::optional symbolizeAIEDevice( + uint32_t d) { + return mlir::iree_compiler::AMDAIE::symbolizeAMDAIEDevice(d); +} + +std::optional symbolizeAIEDevice( + llvm::StringRef d) { + return mlir::iree_compiler::AMDAIE::symbolizeAMDAIEDevice(d); +} + +namespace detail { +struct AIEObjectFifoTypeStorage : TypeStorage { + using KeyTy = MemRefType; + AIEObjectFifoTypeStorage(MemRefType elementType) : elementType(elementType) {} + bool operator==(const KeyTy &key) const { return key == KeyTy(elementType); } + static AIEObjectFifoTypeStorage *construct(TypeStorageAllocator &allocator, + const KeyTy &key) { + return new (allocator.allocate()) + AIEObjectFifoTypeStorage(key); + } + + MemRefType elementType; +}; +} // namespace detail + +AIEObjectFifoType AIEObjectFifoType::get(MemRefType elementType) { + MLIRContext *ctx = elementType.getContext(); + return Base::get(ctx, elementType); +} + +mlir::MemRefType AIEObjectFifoType::getElementType() { + return getImpl()->elementType; +} + +namespace detail { +struct AIEObjectFifoSubviewTypeStorage : TypeStorage { + using KeyTy = MemRefType; + AIEObjectFifoSubviewTypeStorage(MemRefType elementType) + : elementType(elementType) {} + bool operator==(const KeyTy &key) const { return key == elementType; } + static AIEObjectFifoSubviewTypeStorage *construct( + TypeStorageAllocator &allocator, const KeyTy &key) { + return new (allocator.allocate()) + AIEObjectFifoSubviewTypeStorage(key); + } + + MemRefType elementType; +}; +} // namespace detail + +AIEObjectFifoSubviewType AIEObjectFifoSubviewType::get(MemRefType elementType) { + MLIRContext *ctx = elementType.getContext(); + return Base::get(ctx, elementType); +} +MemRefType AIEObjectFifoSubviewType::getElementType() { + return getImpl()->elementType; +} + +static OptionalParseResult aieTypeParser(DialectAsmParser &parser, + StringRef name, Type &result) { + if (name == "objectfifo") { + MemRefType elementType; + SMLoc typeLoc = parser.getCurrentLocation(); + if (parser.parseLess() || parser.parseType(elementType) || + parser.parseGreater()) + return failure(); + + if (!llvm::isa(elementType)) { + parser.emitError(typeLoc, + "element type for an objectFifo must be " + "a MemRefType, got: ") + << elementType; + return failure(); + } + + return result = AIEObjectFifoType::get(elementType), success(); + } + + if (name == "objectfifosubview") { + if (parser.parseLess()) return failure(); + MemRefType elementType; + SMLoc typeLoc = parser.getCurrentLocation(); + if (parser.parseType(elementType)) return failure(); + if (!llvm::isa(elementType)) { + parser.emitError(typeLoc, + "element type for a subview must be " + "a MemRefType, got: ") + << elementType; + return failure(); + } + if (parser.parseGreater()) return failure(); + return result = AIEObjectFifoSubviewType::get(elementType), success(); + } + return {}; +} + +static ParseResult parse(Type &result, StringRef name, + DialectAsmParser &parser) { + if (OptionalParseResult parseResult = aieTypeParser(parser, name, result); + parseResult.has_value()) + return parseResult.value(); + parser.emitError(parser.getNameLoc(), "unknown AIE dialect type: \"") + << name << "\""; + return failure(); +} + +Type AIEDialect::parseType(DialectAsmParser &parser) const { + StringRef name; + Type result; + if (parser.parseKeyword(&name) || parse(result, name, parser)) return {}; + return result; +} + +void AIEDialect::printType(Type type, DialectAsmPrinter &printer) const { + if (llvm::isa(type)) { + auto objectFifoType = llvm::cast(type); + printer << "objectfifo<"; + printer << objectFifoType.getElementType(); + printer << '>'; + } else if (llvm::isa(type)) { + auto subviewType = llvm::cast(type); + printer << "objectfifosubview<"; + printer << subviewType.getElementType(); + printer << '>'; + } +} + +/// without this, canonicalize/cse/etc will lift eg constants out of core ops +/// causing eg lower-to-aie to fail to converge +struct AIEDialectFoldInterface : DialectFoldInterface { + using DialectFoldInterface::DialectFoldInterface; + + /// Registered hook to check if the given region, which is attached to an + /// operation that is *not* isolated from above, should be used when + /// materializing constants. + bool shouldMaterializeInto(Region *region) const final override { + // If this is an AIE::CoreOp region, then insert into it. + return isa(region->getParentOp()); + } +}; + +void AIEDialect::initialize() { + addTypes(); + addAttributes< +#define GET_ATTRDEF_LIST +#include "aie/AIEAttrs.cpp.inc" + >(); + addOperations< +#define GET_OP_LIST +#include "aie/AIEOps.cpp.inc" + >(); + addInterfaces(); +} +} // namespace xilinx::AIE + +#include "aie/AIEEnums.cpp.inc" + +#define GET_OP_CLASSES +#include "aie/AIEOps.cpp.inc" + +// Include implementations for custom attributes +#define GET_ATTRDEF_CLASSES +#include "aie/AIEAttrs.cpp.inc" + +namespace xilinx::AIE { + +mlir::ParseResult parseObjectFifoProducerTile( + mlir::OpAsmParser &parser, mlir::OpAsmParser::UnresolvedOperand &operand, + BDDimLayoutArrayAttr &dimensions) { + std::vector emptyDims = {}; + if (parser.parseOperand(operand)) return mlir::failure(); + if (succeeded(parser.parseOptionalKeyword("toStream"))) { + if (parser.parseCustomAttributeWithFallback( + dimensions)) { + return mlir::failure(); + } + } else { + dimensions = BDDimLayoutArrayAttr::get(parser.getContext(), + llvm::ArrayRef(emptyDims)); + } + return mlir::success(); +} + +void printObjectFifoProducerTile(mlir::OpAsmPrinter &printer, + mlir::Operation *op, mlir::Value operand, + BDDimLayoutArrayAttr dimensions) { + printer << operand; + if (!dimensions.empty()) { + printer << " toStream "; + printer.printStrippedAttrOrType(dimensions); + } +} + +mlir::ParseResult parseObjectFifoConsumerTiles( + mlir::OpAsmParser &parser, + llvm::SmallVectorImpl &tiles, + BDDimLayoutArrayArrayAttr &dimensions) { + std::vector tileDims = {}; + auto parseOneOperand = [&]() -> llvm::ParseResult { + if (parser.parseOperand(tiles.emplace_back(), true)) { + return mlir::failure(); + } + BDDimLayoutArrayAttr dimAttr = + BDDimLayoutArrayAttr::get(parser.getContext(), {}); + if (succeeded(parser.parseOptionalKeyword("fromStream"))) { + if (parser.parseCustomAttributeWithFallback( + dimAttr)) { + return mlir::failure(); + } + } + tileDims.emplace_back(dimAttr); + return mlir::success(); + }; + + if (parser.parseCommaSeparatedList(mlir::AsmParser::Delimiter::None, + parseOneOperand, " in operand list")) + return mlir::failure(); + + dimensions = BDDimLayoutArrayArrayAttr::get(parser.getContext(), tileDims); + return mlir::success(); +} + +void printObjectFifoConsumerTiles(mlir::OpAsmPrinter &printer, + mlir::Operation *op, mlir::OperandRange tiles, + BDDimLayoutArrayArrayAttr dimsPerTileAttr) { + size_t tileIdx = 0; + for (auto tile : tiles) { + printer << tile; + if (dimsPerTileAttr && tileIdx < dimsPerTileAttr.size() && + dimsPerTileAttr[tileIdx] && !dimsPerTileAttr[tileIdx].empty()) { + printer << " fromStream "; + printer.printStrippedAttrOrType(dimsPerTileAttr[tileIdx]); + } + if (tileIdx < tiles.size() - 1) { + printer << ", "; + } + tileIdx++; + } +} + +TileOp getTileOp(mlir::Operation &op) { + mlir::Value t = *op.getOperands().begin(); + return llvm::cast(t.getDefiningOp()); +} + +TileOp CoreOp::getTileOp() { return xilinx::AIE::getTileOp(*getOperation()); } + +TileOp BufferOp::getTileOp() { return xilinx::AIE::getTileOp(*getOperation()); } + +TileOp ShimDMAOp::getTileOp() { + return xilinx::AIE::getTileOp(*getOperation()); +} + +int32_t getBufferElementTypeWidthInBytes(DMABDOp &op) { + return op.getBuffer().getType().getElementTypeBitWidth() / 8; +} + +int32_t getLenInBytes(DMABDOp &op) { + if (std::optional len = op.getLen(); len.has_value()) + return len.value() * getBufferElementTypeWidthInBytes(op); + else + return op.getBuffer().getType().getNumElements() * + getBufferElementTypeWidthInBytes(op); +} + +int32_t getOffsetInBytes(DMABDOp &op) { + return op.getOffset() * getBufferElementTypeWidthInBytes(op); +} + +MemOp getMemOp(TileOp &op) { + auto users = op.getResult().getUsers(); + for (auto user : users) + if (auto memOp = llvm::dyn_cast(*user)) return memOp; + return nullptr; +} + +CoreOp getCoreOp(TileOp &op) { + auto users = op.getResult().getUsers(); + for (auto user : users) + if (auto coreOp = llvm::dyn_cast(*user)) return coreOp; + return nullptr; +} + +MemOp TileOp::getMemOp() { return xilinx::AIE::getMemOp(*this); } + +CoreOp TileOp::getCoreOp() { return xilinx::AIE::getCoreOp(*this); } + +void collectBuffers(DeviceOp &device, + llvm::DenseMap> &buffers) { + for (BufferOp buffer : device.getOps()) { + mlir::Operation *tileOp = buffer.getTile().getDefiningOp(); + buffers[tileOp].push_back(buffer); + } +} + +void collectTiles(xilinx::AIE::DeviceOp &device, + llvm::DenseMap &tiles) { + for (auto tile : device.getOps()) { + int getCol = tile.getCol(); + int getRow = tile.getRow(); + tiles[{getCol, getRow}] = tile; + } +} + +int64_t getAllocationSize(BufferOp &op) { + auto type = llvm::cast(op.getType()); + return type.getNumElements() * type.getElementTypeBitWidth() / 8; +} + +mlir::iree_compiler::AMDAIE::AMDAIEDeviceModel getDeviceModel( + mlir::Operation *op) { + if (auto t = llvm::dyn_cast(op)) { + return mlir::iree_compiler::AMDAIE::getDeviceModel( + static_cast(t.getDevice())); + } + if (auto t = op->getParentOfType()) { + return mlir::iree_compiler::AMDAIE::getDeviceModel( + static_cast(t.getDevice())); + } + llvm::report_fatal_error("couldn't find device model for op"); +} + +size_t TileOp::getNumDestConnections( + mlir::iree_compiler::AMDAIE::StrmSwPortType s) { + auto deviceModel = getDeviceModel(this->getOperation()); + return deviceModel.getNumDestSwitchBoxConnections(this->getCol(), + this->getRow(), s); +} + +size_t TileOp::getNumSourceConnections( + mlir::iree_compiler::AMDAIE::StrmSwPortType s) { + auto deviceModel = getDeviceModel(this->getOperation()); + return deviceModel.getNumSourceSwitchBoxConnections(this->getCol(), + this->getRow(), s); +} + +bool TileOp::isMemTile() { + auto deviceModel = getDeviceModel(this->getOperation()); + return deviceModel.isMemTile(this->getCol(), this->getRow()); +} + +void SwitchboxOp::getAsmResultNames( + llvm::function_ref setNameFn) { + return xilinx::AIE::getAsmResultNames(this, setNameFn); +} + +void ShimMuxOp::getAsmResultNames( + llvm::function_ref setNameFn) { + return xilinx::AIE::getAsmResultNames(this, setNameFn); +} + +void MemOp::getAsmResultNames( + llvm::function_ref setNameFn) { + return xilinx::AIE::getAsmResultNames(this, setNameFn); +} + +void CoreOp::getAsmResultNames( + llvm::function_ref setNameFn) { + return xilinx::AIE::getAsmResultNames(this, setNameFn); +} + +void MemTileDMAOp::getAsmResultNames( + llvm::function_ref setNameFn) { + return xilinx::AIE::getAsmResultNames(this, setNameFn); +} + +void BufferOp::getAsmResultNames( + llvm::function_ref setNameFn) { + return xilinx::AIE::getAsmResultNames(this, setNameFn); +} + +void LockOp::getAsmResultNames( + llvm::function_ref setNameFn) { + return xilinx::AIE::getAsmResultNames(this, setNameFn); +} + +void TileOp::getAsmResultNames( + llvm::function_ref setNameFn) { + std::string nameWithoutDialect = + getOperationName().str().substr(getOperationName().find('.') + 1); + setNameFn(getResult(), nameWithoutDialect + "_" + std::to_string(getCol()) + + "_" + std::to_string(getRow())); +} + +mlir::iree_compiler::AMDAIE::AMDAIEDeviceModel DeviceOp::getTargetModel() { + return getDeviceModel(this->getOperation()); +} + +uint32_t getAddressGenGranularity() { return 32; }; +} // namespace xilinx::AIE diff --git a/compiler/plugins/target/AMD-AIE/aie/AIEDialect.h b/compiler/plugins/target/AMD-AIE/aie/AIEDialect.h new file mode 100644 index 000000000..cf76fea4a --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/AIEDialect.h @@ -0,0 +1,150 @@ +// Copyright 2024 The IREE Authors +// +// Licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +#ifndef MLIR_AIE_DIALECT_H +#define MLIR_AIE_DIALECT_H + +#include "AIEEnums.h" +#include "iree-amd-aie/aie_runtime/iree_aie_router.h" +#include "iree-amd-aie/aie_runtime/iree_aie_runtime.h" +#include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/ControlFlow/IR/ControlFlow.h" +#include "mlir/Dialect/Func/IR/FuncOps.h" +#include "mlir/Dialect/LLVMIR/LLVMDialect.h" +#include "mlir/Dialect/MemRef/IR/MemRef.h" +#include "mlir/Dialect/SCF/IR/SCF.h" +#include "mlir/IR/BuiltinAttributes.h" +#include "mlir/IR/Dialect.h" +#include "mlir/IR/OpDefinition.h" +#include "mlir/IR/OpImplementation.h" +#include "mlir/IR/Types.h" + +namespace xilinx::AIE { +template +bool hasName(T &op) { + return bool(op.getOperation()->template getAttrOfType( + mlir::SymbolTable::getSymbolAttrName())); +} + +template +mlir::StringAttr name(T &op) { + if (auto attr = op.getOperation()->template getAttrOfType( + mlir::SymbolTable::getSymbolAttrName())) + return attr; + op.emitOpError("does not have '") + << mlir::SymbolTable::getSymbolAttrName() << "' attribute specified"; + llvm::report_fatal_error("couldn't get name"); +} + +namespace detail { +struct AIEObjectFifoTypeStorage; +} + +class AIEObjectFifoType + : public mlir::Type::TypeBase { + public: + using Base::Base; + static AIEObjectFifoType get(mlir::MemRefType elementType); + static constexpr llvm::StringLiteral name = "objectfifo"; + mlir::MemRefType getElementType(); +}; + +namespace detail { +struct AIEObjectFifoSubviewTypeStorage; +} + +class AIEObjectFifoSubviewType + : public mlir::Type::TypeBase { + public: + using Base::Base; + static AIEObjectFifoSubviewType get(mlir::MemRefType elementType); + static constexpr llvm::StringLiteral name = "objectfifosubview"; + mlir::MemRefType getElementType(); +}; + +using DMAChannelDir = mlir::iree_compiler::AMDAIE::DMAChannelDir; +using Port = mlir::iree_compiler::AMDAIE::Port; +using WireBundle = mlir::iree_compiler::AMDAIE::StrmSwPortType; +using DMAChannelDirAttr = mlir::iree_compiler::AMDAIE::DMAChannelDirAttr; +using AIEArch = mlir::iree_compiler::AMDAIE::AIEArch; +using AIEDevice = mlir::iree_compiler::AMDAIE::AMDAIEDevice; +using AIEDeviceAttr = mlir::iree_compiler::AMDAIE::AMDAIEDeviceAttr; + +std::optional symbolizeAIEDevice( + uint32_t d); +std::optional symbolizeAIEDevice( + llvm::StringRef d); +} // namespace xilinx::AIE + +#include "aie/AIEDialect.h.inc" + +#define GET_ATTRDEF_CLASSES +#include "aie/AIEAttrs.h.inc" + +#define GET_OP_CLASSES +#include "aie/AIEOps.h.inc" + +namespace xilinx::AIE { +mlir::ParseResult parseObjectFifoProducerTile( + mlir::OpAsmParser &parser, mlir::OpAsmParser::UnresolvedOperand &operand, + BDDimLayoutArrayAttr &dimensions); + +void printObjectFifoProducerTile(mlir::OpAsmPrinter &printer, + mlir::Operation *op, mlir::Value operand, + BDDimLayoutArrayAttr dimensions); + +mlir::ParseResult parseObjectFifoConsumerTiles( + mlir::OpAsmParser &parser, + llvm::SmallVectorImpl &tiles, + BDDimLayoutArrayArrayAttr &dimensions); + +void printObjectFifoConsumerTiles(mlir::OpAsmPrinter &printer, + mlir::Operation *op, mlir::OperandRange tiles, + BDDimLayoutArrayArrayAttr dimsPerTileAttr); + +TileOp getTileOp(mlir::Operation &op); +int32_t getBufferElementTypeWidthInBytes(DMABDOp &op); +int32_t getLenInBytes(DMABDOp &op); +int32_t getOffsetInBytes(DMABDOp &op); +MemOp getMemOp(TileOp &op); +CoreOp getCoreOp(TileOp &op); +void collectBuffers( + DeviceOp &device, + llvm::DenseMap> &buffers); +void collectTiles(xilinx::AIE::DeviceOp &device, + llvm::DenseMap &tiles); +int64_t getAllocationSize(BufferOp &op); +mlir::iree_compiler::AMDAIE::AMDAIEDeviceModel getDeviceModel( + mlir::Operation *op); + +template +void getAsmResultNames( + T op, llvm::function_ref setNameFn) { + std::string nameWithoutDialect = + op->getOperationName().str().substr(op->getOperationName().find('.') + 1); + auto t = llvm::cast(op->getTile().getDefiningOp()); + setNameFn(op->getResult(), nameWithoutDialect + "_" + + std::to_string(t.getCol()) + "_" + + std::to_string(t.getRow())); +} + +uint32_t getAddressGenGranularity(); + +struct DMAChannel { + DMAChannelDir direction; + int channel; + + bool operator==(const DMAChannel &rhs) const { + return std::tie(direction, channel) == std::tie(rhs.direction, rhs.channel); + } +}; + +} // namespace xilinx::AIE + +#endif diff --git a/compiler/plugins/target/AMD-AIE/aie/AIEEnums.h b/compiler/plugins/target/AMD-AIE/aie/AIEEnums.h new file mode 100644 index 000000000..b1628d732 --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/AIEEnums.h @@ -0,0 +1,15 @@ +// Copyright 2024 The IREE Authors +// +// Licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +#ifndef MLIR_AIE_ENUMS_H +#define MLIR_AIE_ENUMS_H + +#include "mlir/IR/BuiltinTypes.h" +#include "mlir/IR/Dialect.h" + +#include "aie/AIEEnums.h.inc" + +#endif diff --git a/compiler/plugins/target/AMD-AIE/aie/AIENormalizeAddressSpaces.td b/compiler/plugins/target/AMD-AIE/aie/AIENormalizeAddressSpaces.td new file mode 100644 index 000000000..8c1ece08d --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/AIENormalizeAddressSpaces.td @@ -0,0 +1,26 @@ +// Copyright 2024 The IREE Authors +// +// Licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +#ifndef AIE_NORMALIZE_ADDRESS_SPACES +#define AIE_NORMALIZE_ADDRESS_SPACES + +include "AIE.td" + +include "mlir/Dialect/MemRef/IR/MemRefOps.td" +include "mlir/IR/PatternBase.td" + +def toDefaultAddressSpace : NativeCodeCall<"TypeAttr::get(memRefToDefaultAddressSpace($0.getValue()))">; +def hasNonDefaultAddressSpace : Constraint< + CPred<"llvm::cast($0.getValue()).getMemorySpace() != 0">, + "has non-default address space">; +def : Pat< + /*pattern*/ (MemRef_GlobalOp $sym_name, $sym_visibility, $type, $initial_value, $constant, $attrs), + /*result*/ (MemRef_GlobalOp $sym_name, $sym_visibility, (toDefaultAddressSpace $type), $initial_value, $constant, $attrs), + /*preds*/ [(hasNonDefaultAddressSpace $type)], + /*supplemental_results*/ [], + /*benefitAdded*/ (addBenefit 20)>; + +#endif // AIE_NORMALIZE_ADDRESS_SPACES diff --git a/compiler/plugins/target/AMD-AIE/aie/AIEOps.td b/compiler/plugins/target/AMD-AIE/aie/AIEOps.td new file mode 100644 index 000000000..c8b3399df --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/AIEOps.td @@ -0,0 +1,661 @@ +// Copyright 2024 The IREE Authors +// +// Licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +#ifndef AIE_OPS +#define AIE_OPS + +include "AIE.td" +include "AIEAttrs.td" +include "AIETypes.td" +include "iree-amd-aie/aie_runtime/AMDAIEEnums.td" + +include "mlir/IR/CommonAttrConstraints.td" +include "mlir/IR/SymbolInterfaces.td" +include "mlir/Interfaces/CallInterfaces.td" +include "mlir/Interfaces/InferTypeOpInterface.td" +include "mlir/Interfaces/SideEffectInterfaces.td" +include "mlir/IR/OpAsmInterface.td" + +class AIE_Op traits = []> : + Op; + +def AIE_DeviceOp: AIE_Op<"device", [ + HasParent<"mlir::ModuleOp">, + SymbolTable, SingleBlock, NoTerminator, IsolatedFromAbove + ]> { + let summary = "Define an AIE design targetting a complete device"; + let arguments = (ins AMDAIEDeviceAttr:$device); + let regions = (region AnyRegion:$body_region); + let assemblyFormat = [{ + `(` $device `)` regions attr-dict + }]; + + // mlir-air legacy + let extraClassDeclaration = [{ + mlir::iree_compiler::AMDAIE::AMDAIEDeviceModel getTargetModel(); + }]; +} + +def AIE_TileOp: AIE_Op<"tile", [ + Pure, + DeclareOpInterfaceMethods, + DeclareOpInterfaceMethods + ]>, Results<(outs Index:$result)> { + let arguments = ( + ins ConfinedAttr]>:$col, + ConfinedAttr]>:$row + ); + + let summary = "Declare an AIE tile"; + let assemblyFormat = [{ + `(` $col `,` $row `)` attr-dict + }]; + + // mlir-air legacy + let extraClassDeclaration = [{ + int colIndex() { return getCol(); } + int rowIndex() { return getRow(); } + bool isShimTile() { return getRow() == 0; } + CoreOp getCoreOp(); + bool isMemTile(); + MemOp getMemOp(); + size_t getNumSourceConnections(mlir::iree_compiler::AMDAIE::StrmSwPortType w); + size_t getNumDestConnections(mlir::iree_compiler::AMDAIE::StrmSwPortType w); + void getAsmResultNames( + llvm::function_ref setNameFn); + }]; +} + +def AIE_EndOp: AIE_Op<"end", [Terminator]> { + let summary = "end op"; + let assemblyFormat = [{ attr-dict }]; +} + +def AIE_SwitchboxOp: AIE_Op<"switchbox", [ + DeclareOpInterfaceMethods, + SingleBlockImplicitTerminator<"EndOp">, + DeclareOpInterfaceMethods + ]>, Results<(outs Index:$result)> { + let arguments = (ins Index:$tile); + + let summary = "Declare a switch"; + let regions = (region AnyRegion:$connections); + let assemblyFormat = [{ `(` $tile `)` regions attr-dict }]; + // mlir-air legacy + let extraClassDeclaration = [{ + void getAsmResultNames( + llvm::function_ref setNameFn); + }]; +} + +def AIE_ShimSwitchboxOp: AIE_Op<"shim_switchbox", [ + SingleBlockImplicitTerminator<"EndOp">, + DeclareOpInterfaceMethods + ]>, Results<(outs Index)> { + let arguments = (ins I8Attr:$col); + let summary = "Declare a switch in the PL shim"; + let regions = (region AnyRegion:$connections); + let assemblyFormat = [{ `(` $col `)` regions attr-dict }]; +} + +def AIE_ShimMuxOp: AIE_Op<"shim_mux", [ + DeclareOpInterfaceMethods, + SingleBlockImplicitTerminator<"EndOp">, + DeclareOpInterfaceMethods + ]>, Results<(outs Index)> { + let arguments = ( + ins Index:$tile + ); + let summary = "Declare a switch in the PL shim"; + let regions = (region AnyRegion:$connections); + let assemblyFormat = [{ `(` $tile `)` regions attr-dict }]; + let extraClassDeclaration = [{ + void getAsmResultNames( + llvm::function_ref setNameFn); + }]; +} + +def AIE_CoreOp: AIE_Op<"core", [ + DeclareOpInterfaceMethods, + DeclareOpInterfaceMethods + ]>, Results<(outs Index)> { + let arguments = ( + ins Index:$tile, + DefaultValuedAttr:$stack_size, + OptionalAttr:$link_with, + OptionalAttr:$elf_file + ); + let summary = "Declare a core module"; + let regions = (region AnyRegion:$body); + let assemblyFormat = [{ `(` $tile `)` regions attr-dict }]; + + let builders = [ + OpBuilder<(ins "mlir::Value":$tile), [{ + build($_builder, $_state, $_builder.getIndexType(), tile); + }]> + ]; + // mlir-air legacy + let extraClassDeclaration = [{ + TileOp getTileOp(); + void getAsmResultNames( + llvm::function_ref setNameFn); + }]; +} + +def AIE_ConnectOp: AIE_Op<"connect"> { + let arguments = ( + ins StrmSwPortTypeAttr:$source_bundle, + ConfinedAttr]>:$source_channel, + StrmSwPortTypeAttr:$dest_bundle, + ConfinedAttr]>:$dest_channel + ); + let summary = "A circuit-switched connection inside a switchbox"; + let assemblyFormat = [{ + `<` $source_bundle `:` $source_channel `,` $dest_bundle `:` $dest_channel `>` attr-dict + }]; +} + +def AIE_FlowOp: AIE_Op<"flow"> { + let arguments = ( + ins Index:$source, + StrmSwPortTypeAttr:$source_bundle, + ConfinedAttr]>:$source_channel, + Index:$dest, + StrmSwPortTypeAttr:$dest_bundle, + ConfinedAttr]>:$dest_channel + ); + let summary = "A logical circuit-switched connection between cores"; + let assemblyFormat = [{ + `(` $source `,` $source_bundle `:` $source_channel `,` $dest `,` $dest_bundle `:` $dest_channel `)` attr-dict + }]; +} + +def AIE_AMSelOp: AIE_Op<"amsel", [ + HasParent<"SwitchboxOp">, + DeclareOpInterfaceMethods + ]>, Results<(outs Index)> { + let arguments = ( + ins ConfinedAttr, IntMaxValue<5>]>:$arbiterID, + ConfinedAttr, IntMaxValue<3>]>:$msel + ); + let summary = "Declare an arbiter of a switchbox with a master select value (arbiter + msel)"; + let assemblyFormat = [{ + `<` $arbiterID `>` `(` $msel `)` attr-dict + }]; + + let builders = [ + OpBuilder<(ins "int":$arbiterID, "int":$msel), + [{ + build($_builder, $_state, $_builder.getIndexType(), + $_builder.getI8IntegerAttr(arbiterID), + $_builder.getI8IntegerAttr(msel)); + }]> + ]; +} + +def AIE_MasterSetOp: AIE_Op<"masterset", [ + HasParent<"SwitchboxOp">, + DeclareOpInterfaceMethods + ]>, Results<(outs Index)> { + let arguments = ( + ins StrmSwPortTypeAttr:$dest_bundle, + ConfinedAttr]>:$dest_channel, + Variadic:$amsels + ); + let summary = "Packet switched input connection"; + let assemblyFormat = [{ + `(` $dest_bundle `:` $dest_channel `,` $amsels `)` attr-dict + }]; +} + +def AIE_PacketRulesOp: AIE_Op<"packet_rules", [SingleBlockImplicitTerminator<"EndOp">]> { + let arguments = ( + ins StrmSwPortTypeAttr:$source_bundle, + ConfinedAttr]>:$source_channel + ); + let regions = (region AnyRegion:$rules); + let summary = "Packet switched routing rules"; + let assemblyFormat = [{ `(` $source_bundle `:` $source_channel `)` regions attr-dict }]; +} + +def AIE_PacketRuleOp: AIE_Op<"rule"> { + let arguments = ( + ins I8Attr:$mask, + I8Attr:$value, + Index:$amsel + ); + let summary = "Packet switched routing rule"; + let assemblyFormat = [{ + `(` $mask `,` $value `,` $amsel `)` attr-dict + }]; +} + +def AIE_PacketFlowOp: AIE_Op<"packet_flow", [SingleBlockImplicitTerminator<"EndOp">]> { + let summary = "Packet switched flow"; + let arguments = ( + ins I8Attr:$ID, + OptionalAttr:$keep_pkt_header + ); + let regions = (region AnyRegion:$ports); + + let assemblyFormat = [{ `(` $ID `)` regions attr-dict }]; + // mlir-air legacy + let extraClassDeclaration = [{ + int IDInt() { return getID(); } + }]; +} + +def AIE_PacketSourceOp: AIE_Op<"packet_source"> { + let arguments = ( + ins Index:$tile, + StrmSwPortTypeAttr:$bundle, + ConfinedAttr]>:$channel + ); + let summary = "A sourceport"; + let assemblyFormat = [{ + `<` $tile `,` $bundle `:` $channel `>` attr-dict + }]; + + // mlir-air legacy + let extraClassDeclaration = [{ + Port port() { return {getBundle(), getChannel()}; } + }]; +} + +def AIE_PacketDestOp: AIE_Op<"packet_dest"> { + let arguments = ( + ins Index:$tile, + StrmSwPortTypeAttr:$bundle, + ConfinedAttr]>:$channel + ); + let summary = "A destination port"; + let assemblyFormat = [{ + `<` $tile `,` $bundle `:` $channel `>` attr-dict + }]; + + // mlir-air legacy + let extraClassDeclaration = [{ + Port port() { return {getBundle(), getChannel()}; } + }]; +} + +def AIE_DMABDPACKETOp: AIE_Op<"dma_bd_packet"> { + let summary = "Enable packet headers for a dma block descriptor"; + let arguments = ( + ins I32Attr:$packet_type, + I32Attr:$packet_id + ); + + let assemblyFormat = [{ + `(` $packet_type `,` $packet_id `)` attr-dict + }]; +} + +def AIE_DMABDOp: AIE_Op<"dma_bd", [ + DeclareOpInterfaceMethods, + ]> { + let summary = "Declare a dma buffer descriptor op"; + let arguments = ( + ins AnyMemRef:$buffer, + // in multiples of element width (not bytes) + DefaultValuedOptionalAttr:$offset, + // in multiples of element width (not bytes) + OptionalAttr:$len, + OptionalAttr:$dimensions, + OptionalAttr:$pad_dimensions, + DefaultValuedOptionalAttr:$pad_value, + OptionalAttr:$bd_id, + // should never be assigned by user... + OptionalAttr:$next_bd_id + ); + + + let assemblyFormat = [{ + `(` $buffer `:` type($buffer) (`,` $offset^)? (`,` $len^)? (`,` $dimensions^)? (`,` $pad_dimensions^)? (`,` `pad_value` `=` $pad_value^)? `)` attr-dict + }]; + + let builders = [ + OpBuilder<(ins "mlir::Value":$buffer, "int":$offset, "int":$len), [{ + $_state.addOperands(buffer); + $_state.addAttribute("offset", $_builder.getI32IntegerAttr(offset)); + $_state.addAttribute("len", $_builder.getI32IntegerAttr(len)); + }]>, + OpBuilder<(ins "mlir::Value":$buffer, "int":$offset, "int":$len, "BDDimLayoutArrayAttr":$dims), [{ + $_state.addOperands(buffer); + $_state.addAttribute("offset", $_builder.getI32IntegerAttr(offset)); + $_state.addAttribute("len", $_builder.getI32IntegerAttr(len)); + $_state.addAttribute("dimensions", dims); + }]>, + OpBuilder<(ins "mlir::Value":$buffer, "int":$offset, "int":$len, "BDPadLayoutArrayAttr":$paddims), [{ + $_state.addOperands(buffer); + $_state.addAttribute("offset", $_builder.getI32IntegerAttr(offset)); + $_state.addAttribute("len", $_builder.getI32IntegerAttr(len)); + $_state.addAttribute("pad_dimensions", paddims); + }]>, + OpBuilder<(ins "mlir::Value":$buffer, "int":$offset, "int":$len, "BDDimLayoutArrayAttr":$dims, "BDPadLayoutArrayAttr":$paddims), [{ + $_state.addOperands(buffer); + $_state.addAttribute("offset", $_builder.getI32IntegerAttr(offset)); + $_state.addAttribute("len", $_builder.getI32IntegerAttr(len)); + $_state.addAttribute("dimensions", dims); + $_state.addAttribute("pad_dimensions", paddims); + }]> + ]; +} + +def AIE_DMAStartOp: AIE_Op<"dma_start", [ + Terminator, + DeclareOpInterfaceMethods + ]>, Results<(outs I1:$valid)> { + + let summary = "An op to start DMA"; + let arguments = ( + ins DMAChannelDir:$channel_dir, + ConfinedAttr]>:$channel_index, + // repeat_count==0 means "do it once" and don't repeat + DefaultValuedAttr:$repeat_count + ); + let successors = (successor AnySuccessor:$dest, AnySuccessor:$chain); + let assemblyFormat = [{ + `(` $channel_dir `,` $channel_index `,` $dest `,` $chain (`,` `repeat_count` `=` $repeat_count^)? `)` attr-dict + }]; +} + +// MemOps are not actually Callable, but we want to inline code into them, so we have to +// implement CallableOpInterface +def AIE_MemOp: AIE_Op<"mem", [ + DeclareOpInterfaceMethods, + DeclareOpInterfaceMethods + ]>, Results<(outs Index)> { + let summary = "Declare a memory op"; + let arguments = (ins Index:$tile); + let regions = (region AnyRegion:$body); + let assemblyFormat = [{ `(` $tile `)` regions attr-dict }]; + // mlir-air legacy + let extraClassDeclaration = [{ + void getAsmResultNames( + llvm::function_ref setNameFn); + }]; +} + +def AIE_MemTileDMAOp: AIE_Op<"memtile_dma", [ + DeclareOpInterfaceMethods, + DeclareOpInterfaceMethods + ]>, Results<(outs Index)> { + let summary = "Declare a memtile_dma op"; + let arguments = (ins Index:$tile); + let regions = (region AnyRegion:$body); + let assemblyFormat = [{ `(` $tile `)` regions attr-dict }]; + // mlir-air legacy + let extraClassDeclaration = [{ + void getAsmResultNames( + llvm::function_ref setNameFn); + }]; +} + +def AIE_NextBDOp: AIE_Op<"next_bd", [Terminator]> { + let summary = "The next buffer descriptor"; + let successors = (successor AnySuccessor:$dest); + + let assemblyFormat = [{ + $dest attr-dict + }]; +} + +def AIE_LockOp: AIE_Op<"lock", [ + DeclareOpInterfaceMethods, + Pure, DeclareOpInterfaceMethods + ]>, Results<(outs Index)> { + let summary = "Declare a physical lock"; + let arguments = ( + ins Index:$tile, + OptionalAttr]>>:$lockID, + OptionalAttr:$init, + OptionalAttr:$sym_name + ); + + let assemblyFormat = [{ `(` $tile (`,` $lockID^ )? `)` attr-dict }]; + + let builders = [ + OpBuilder<(ins "mlir::Value":$tile, "int":$lockID, "int":$init), [{ + build($_builder, $_state, + $_builder.getIndexType(), + tile, + $_builder.getI8IntegerAttr(lockID), + $_builder.getI8IntegerAttr(init), + nullptr + ); + }]> + ]; + // mlir-air legacy + let extraClassDeclaration = [{ + int getLockIDValue() { + assert(getLockID().has_value() && "Lock has no ID value"); + return getLockID().value(); + } + void getAsmResultNames( + llvm::function_ref setNameFn); + }]; +} + +def AIE_UseLockOp: AIE_Op<"use_lock"> { + let summary = "acquire/release lock op"; + let arguments = ( + ins Index:$lock, + LockAction:$action, + OptionalAttr:$value, + OptionalAttr:$blocking, + DefaultValuedOptionalAttr:$acq_en + ); + + let assemblyFormat = [{ + `(` $lock `,` $action (`,` $value^)? (`,` $blocking^)? `)` attr-dict + }]; + + let builders = [ + OpBuilder<(ins "mlir::Value":$lock, + "xilinx::AIE::LockAction":$action, + "int32_t":$value), [{ + build($_builder, $_state, lock, action, $_builder.getI8IntegerAttr(value), nullptr); + }]> + ]; +} + +def AIE_BufferOp: AIE_Op<"buffer", [ + DeclareOpInterfaceMethods, +]>, Results<(outs AnyMemRef)> { + let summary = "Declare a buffer"; + let arguments = ( + ins Index:$tile, + OptionalAttr:$sym_name, + OptionalAttr:$address, + OptionalAttr:$mem_bank + ); + + let results = (outs AnyMemRef:$buffer); + let assemblyFormat = [{ + `(` $tile `)` attr-dict `:` type($buffer) + }]; + // mlir-air legacy + let extraClassDeclaration = [{ + TileOp getTileOp(); + void getAsmResultNames( + llvm::function_ref setNameFn); + }]; +} + +def AIE_ShimDMAAllocationOp : AIE_Op<"shim_dma_allocation"> { + let summary = "Runtime allocation information for a single shim DMA"; + let arguments = ( + ins FlatSymbolRefAttr:$sym_name, + DMAChannelDir:$channel_dir, + I64Attr:$channel_index, + I64Attr:$col, + // If this is set we are using the PLIO in this ShimTile + DefaultValuedAttr:$plio + ); + + let results = (outs); + + let assemblyFormat = [{ + $sym_name `(` $channel_dir `,` $channel_index `,` $col `)` attr-dict + }]; +} + +def AIE_ObjectFifoCreateOp: AIE_Op<"objectfifo", [Symbol]> { + let summary = "Create a circular buffer or channel between two tiles"; + let arguments = ( + ins SymbolNameAttr:$sym_name, + Index:$producerTile, + Variadic:$consumerTiles, + AnyAttrOf<[ConfinedAttr]>, ArrayAttr]>:$elemNumber, + TypeAttrOf:$elemType, + BDDimLayoutArrayAttr:$dimensionsToStream, + BDDimLayoutArrayArrayAttr:$dimensionsFromStreamPerConsumer, + DefaultValuedAttr:$via_DMA, + DefaultValuedAttr:$plio + ); + + let assemblyFormat = [{ + $sym_name + `(` + custom($producerTile, $dimensionsToStream) `,` + `{` + custom($consumerTiles, $dimensionsFromStreamPerConsumer) + `}` + `,` + $elemNumber + `)` attr-dict `:` $elemType + }]; + + let builders = [ + OpBuilder<(ins "mlir::StringAttr":$sym_name, "mlir::Value":$producerTile, + "mlir::ValueRange":$consumerTiles, "mlir::Attribute":$elemNumber, "mlir::Type":$elem_type, + CArg<"llvm::ArrayRef", "{}">:$dimensionsToStream, + CArg<"llvm::ArrayRef", "{}">:$dimensionsFromStreamPerConsumer), [{ + odsState.addOperands(producerTile); + odsState.addOperands(consumerTiles); + odsState.addAttribute(getSymNameAttrName(odsState.name), sym_name); + odsState.addAttribute(getElemNumberAttrName(odsState.name), elemNumber); + odsState.addAttribute(getElemTypeAttrName(odsState.name), mlir::TypeAttr::get(elem_type)); + odsState.addAttribute(getDimensionsToStreamAttrName(odsState.name), + odsBuilder.getAttr(dimensionsToStream)); + odsState.addAttribute(getDimensionsFromStreamPerConsumerAttrName(odsState.name), + odsBuilder.getAttr(dimensionsFromStreamPerConsumer)); + }]> + ]; + + let extraClassDeclaration = [{ + mlir::StringAttr name() { + return ::xilinx::AIE::name(*this); + } + }]; +} + +def AIE_ObjectFifoLinkOp: AIE_Op<"objectfifo.link"> { + let summary = "Links two objectFifos through an intermediary tile's DMA"; + let arguments = ( + ins SymbolRefArrayAttr:$fifoIns, + SymbolRefArrayAttr:$fifoOuts + ); + + let hasCustomAssemblyFormat = 1; + + let assemblyFormat = [{ + $fifoIns `->` $fifoOuts `(` `)` attr-dict + }]; +} + +def AIE_ObjectFifoAcquireOp: AIE_Op<"objectfifo.acquire"> { + let summary = "Acquire operation to lock and return objects of an ObjectFifo"; + let arguments = ( + ins ObjectFifoPort:$port, + FlatSymbolRefAttr:$objFifo_name, + ConfinedAttr]>:$size + ); + + let results = (outs AIE_ObjectFifoSubviewType:$subview); + + let assemblyFormat = [{ + attr-dict $objFifo_name `(` $port `,` $size `)` `:` type($subview) + }]; + +} + +def AIE_ObjectFifoReleaseOp: AIE_Op<"objectfifo.release"> { + let summary = "Release operation for object locks in an ObjectFifo"; + let arguments = ( + ins ObjectFifoPort:$port, + FlatSymbolRefAttr:$objFifo_name, + ConfinedAttr]>:$size + ); + + let assemblyFormat = [{ + attr-dict $objFifo_name `(` $port `,` $size `)` + }]; + +} + +def AIE_ObjectFifoSubviewAccessOp : AIE_Op<"objectfifo.subview.access"> { + let summary = "ObjectFifoSubview type accessor method"; + let arguments = ( + ins AIE_ObjectFifoSubviewType:$subview, + ConfinedAttr]>:$index + ); + + + let results = (outs AnyMemRef:$output); + + let assemblyFormat = [{ + $subview `[` $index `]` attr-dict `:` type($subview) `->` type($output) + }]; + + let builders = [ + OpBuilder<(ins "mlir::Value":$subview, "size_t":$index)> + ]; +} + +// mlir-air legacy + +def AIE_ExternalBufferOp: AIE_Op<"external_buffer">, Results<(outs AnyMemRef)> { + let summary = "Declare a buffer in external memory"; + let arguments = (ins OptionalAttr:$sym_name); + + let results = (outs AnyMemRef:$buffer); + let assemblyFormat = [{ attr-dict `:` type($buffer) }]; +} + +def AIE_ShimDMAOp: AIE_Op<"shim_dma", [ + DeclareOpInterfaceMethods + ]>, Results<(outs Index)> { + let arguments = ( + ins Index:$tile + ); + let summary = "Declare a DMA in the PL shim"; + let regions = (region AnyRegion:$body); + let assemblyFormat = [{ `(` $tile `)` regions attr-dict }]; + let extraClassDeclaration = [{ + int colIndex(); + int rowIndex(); + TileOp getTileOp(); + }]; +} + +// legacy to support tests + +def AIE_ObjectFifoRegisterExternalBuffersOp: AIE_Op<"objectfifo.register_external_buffers"> { + let summary = "Registers external buffers to given object fifo shim tile(s) to use in the associated shim DMA(s)"; + let arguments = ( + ins FlatSymbolRefAttr:$objFifo_name, + Index:$tile, + Variadic:$externalBuffers + ); + + let assemblyFormat = [{ + attr-dict $objFifo_name `(` $tile `,` `{` $externalBuffers `}` `)` `:` `(` type($externalBuffers) `)` + }]; +} + +#endif // AIE_OPS diff --git a/compiler/plugins/target/AMD-AIE/aie/AIETypes.td b/compiler/plugins/target/AMD-AIE/aie/AIETypes.td new file mode 100644 index 000000000..41a81d510 --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/AIETypes.td @@ -0,0 +1,23 @@ +// Copyright 2024 The IREE Authors +// +// Licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +#ifndef AIE_TYPES +#define AIE_TYPES + +include "AIE.td" +include "AIEAttrs.td" + +include "mlir/IR/AttrTypeBase.td" + +def AIE_ObjectFifoType : + DialectType($_self)">, + "AIE objectFifo type">; + +def AIE_ObjectFifoSubviewType : + DialectType($_self)">, + "AIE ObjectFifoSubview type">; + +#endif // AIE_TYPES diff --git a/compiler/plugins/target/AMD-AIE/aie/AIEX.td b/compiler/plugins/target/AMD-AIE/aie/AIEX.td new file mode 100644 index 000000000..69fd6bc59 --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/AIEX.td @@ -0,0 +1,205 @@ +// Copyright 2024 The IREE Authors +// +// Licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +#ifndef AIEX_OPS +#define AIEX_OPS + +include "AIEAttrs.td" +include "iree-amd-aie/aie_runtime/AMDAIEEnums.td" + +include "mlir/IR/OpBase.td" +include "mlir/IR/AttrTypeBase.td" +include "mlir/IR/EnumAttr.td" +include "mlir/IR/SymbolInterfaces.td" +include "mlir/Interfaces/CallInterfaces.td" +include "mlir/Interfaces/SideEffectInterfaces.td" +include "mlir/IR/CommonAttrConstraints.td" + +def AIEX_Dialect : Dialect { + let name = "aiex"; + let cppNamespace = "::xilinx::AIEX"; +} + +class AIEX_Op traits = []> : + Op; + +def AIE_RuntimeSequenceOp : AIEX_Op<"runtime_sequence", [NoTerminator]> { + let summary = "Program the configuration co-processor of the AI Engine array"; + let arguments = ( + ins OptionalAttr:$sym_name + ); + let regions = (region + AnyRegion:$body + ); + let hasCustomAssemblyFormat = 1; +} + +def MyOffsetSizeAndStrideOpInterface: OpInterfaceTrait<"::xilinx::AIE::MyOffsetSizeAndStrideOpInterface"> {} +def AIE_NpuDmaMemcpyNdOp: AIEX_Op<"npu.dma_memcpy_nd", [ + AttrSizedOperandSegments, + MyOffsetSizeAndStrideOpInterface + ]> { + let summary = "half DMA operator"; + let arguments = ( + ins I64Attr:$x, + I64Attr:$y, + AnyMemRef:$memref, + // NOTE: these are in reverse order: offset3, offset2, ... + Variadic:$offsets, + Variadic:$sizes, + Variadic:$strides, + ConfinedAttr]>:$static_offsets, + ConfinedAttr]>:$static_sizes, + ConfinedAttr]>:$static_strides, + FlatSymbolRefAttr:$metadata, + I64Attr:$id, + DefaultValuedOptionalAttr:$issue_token + ); + + let assemblyFormat = [{ + `(` $x `,` $y `,` $memref `` + custom($offsets, $static_offsets) `` + custom($sizes, $static_sizes) `` + custom($strides, $static_strides) `)` + attr-dict `:` type($memref) + }]; + + let extraClassDeclaration = [{ + static unsigned getOffsetSizeAndStrideStartOperandIndex(); + static std::array getArrayAttrMaxRanks(); + llvm::SmallVector getStridesInAddressGranularity(); + llvm::SmallVector getSizesInAddressGranularity(); + int64_t getOffsetInBytes(); + }]; + + let extraClassDefinition = [{ + unsigned $cppClass::getOffsetSizeAndStrideStartOperandIndex() { return 1; } + std::array $cppClass::getArrayAttrMaxRanks() { return {4, 4, 4}; } + }]; +} + +def AIE_NpuDmaWaitOp: AIEX_Op<"npu.dma_wait"> { + let summary = "Blocking operation to wait for a DMA to complete execution."; + let arguments = ( + ins FlatSymbolRefAttr:$symbol + ); + let assemblyFormat = [{ + attr-dict + }]; +} + +def AIE_NpuPushQueueOp: AIEX_Op<"npu.push_queue"> { + let summary = "bd queue push operator"; + let arguments = ( + ins I32Attr:$column, + I32Attr:$row, + DMAChannelDir:$direction, + I32Attr:$channel, + BoolAttr:$issue_token, + I32Attr:$repeat_count, + I32Attr:$bd_id + ); + let results = (outs ); + let assemblyFormat = [{ + `(` $column `,` $row `,` $direction `:` $channel `)` attr-dict + }]; +} + +def AIE_NpuWrite32Op: AIEX_Op<"npu.write32"> { + let summary = "write32 operator"; + let arguments = ( + ins UI32Attr:$address, + UI32Attr:$value, + OptionalAttr:$buffer, + OptionalAttr:$column, + OptionalAttr:$row + ); + let results = (outs ); + let assemblyFormat = [{ + attr-dict + }]; +} + +def AIE_NpuBlockWriteOp: AIEX_Op<"npu.blockwrite"> { + let summary = "blockwrite operator"; + let arguments = ( + ins UI32Attr:$address, + AnyMemRef:$data, + OptionalAttr:$buffer, + OptionalAttr:$column, + OptionalAttr:$row + ); + let results = (outs ); + let assemblyFormat = [{ + `(` $data `)` attr-dict `:` type($data) + }]; +} + +// OP_SYNC +def AIE_NpuSyncOp: AIEX_Op<"npu.sync"> { + let summary = "sync operator"; + let arguments = ( + ins I32Attr:$column, + I32Attr:$row, + I32Attr:$direction, + I32Attr:$channel, + I32Attr:$column_num, + I32Attr:$row_num + ); + let results = (outs ); + let assemblyFormat = [{ + attr-dict + }]; +} + +def AIE_NpuAddressPatchOp: AIEX_Op<"npu.address_patch"> { + let summary = "address patch operator"; + let arguments = ( + ins UI32Attr:$addr, + I32Attr:$arg_idx, + I32Attr:$arg_plus + ); + let results = (outs ); + let assemblyFormat = [{ + attr-dict + }]; +} + +// NPU Bd Write operation +def AIE_NpuWriteBdOp: AIEX_Op<"npu.writebd"> { + let summary = "dma operator"; + let arguments = ( + ins I32Attr:$column, + I32Attr:$bd_id, + I32Attr:$buffer_length, + I32Attr:$buffer_offset, + I32Attr:$enable_packet, + I32Attr:$out_of_order_id, + I32Attr:$packet_id, + I32Attr:$packet_type, + I32Attr:$d0_size, + I32Attr:$d0_stride, + I32Attr:$d1_size, + I32Attr:$d1_stride, + I32Attr:$d2_stride, + I32Attr:$iteration_current, + I32Attr:$iteration_size, + I32Attr:$iteration_stride, + I32Attr:$next_bd, + I32Attr:$row, + I32Attr:$use_next_bd, + I32Attr:$valid_bd, + I32Attr:$lock_rel_val, + I32Attr:$lock_rel_id, + I32Attr:$lock_acq_enable, + I32Attr:$lock_acq_val, + I32Attr:$lock_acq_id + ); + let results = (outs ); + let assemblyFormat = [{ attr-dict }]; +} + +#endif // AIEX_OPS diff --git a/compiler/plugins/target/AMD-AIE/aie/AIEXDialect.cpp b/compiler/plugins/target/AMD-AIE/aie/AIEXDialect.cpp new file mode 100644 index 000000000..001f2ace0 --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/AIEXDialect.cpp @@ -0,0 +1,169 @@ +// Copyright 2024 The IREE Authors +// +// Licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +#include "AIEXDialect.h" + +#include "mlir/Dialect/Func/IR/FuncOps.h" +#include "mlir/Interfaces/FoldInterfaces.h" +#include "mlir/Transforms/InliningUtils.h" + +using namespace mlir; +using namespace xilinx; +using namespace xilinx::AIE; + +#include "aie/AIEXDialect.cpp.inc" + +namespace xilinx::AIEX { + +void AIEXDialect::initialize() { + addOperations< +#define GET_OP_LIST +#include "aie/AIEX.cpp.inc" + >(); +} + +} // namespace xilinx::AIEX + +#define GET_OP_CLASSES +#include "aie/AIEX.cpp.inc" + +llvm::SmallVector +AIEX::NpuDmaMemcpyNdOp::getStridesInAddressGranularity() { + MemRefType buffer = getMemref().getType(); + auto elemWidth = buffer.getElementTypeBitWidth(); + auto addressGranularity = getAddressGenGranularity(); + llvm::SmallVector strides = llvm::map_to_vector( + llvm::reverse(getMixedStrides()), + [](OpFoldResult s) { return getConstantIntValue(s).value(); }); + if (!strides.empty()) { + for (int i = 0; i < 4; i++) { + strides[i] = (strides[i] * elemWidth) / addressGranularity; + } + } + return strides; +} + +llvm::SmallVector +AIEX::NpuDmaMemcpyNdOp::getSizesInAddressGranularity() { + MemRefType buffer = getMemref().getType(); + auto elemWidth = buffer.getElementTypeBitWidth(); + auto addressGranularity = getAddressGenGranularity(); + llvm::SmallVector sizes = llvm::map_to_vector( + llvm::reverse(getMixedSizes()), + [](OpFoldResult s) { return getConstantIntValue(s).value(); }); + if (!sizes.empty()) { + sizes[0] = (sizes[0] * elemWidth) / addressGranularity; + } + return sizes; +} + +int64_t AIEX::NpuDmaMemcpyNdOp::getOffsetInBytes() { + llvm::SmallVector offsets = llvm::map_to_vector( + llvm::reverse(getMixedOffsets()), + [](OpFoldResult s) { return getConstantIntValue(s).value(); }); + size_t stride = 1; + size_t offset = 0; + MemRefType my_memref = getMemref().getType(); + auto shape = my_memref.getShape(); + size_t R = shape.size(); + size_t el_bit_width = my_memref.getElementTypeBitWidth(); + assert(el_bit_width % 8 == 0 && + "Expected Memref element bitwidth to be multiple of 8."); + size_t S = el_bit_width / 8; + for (size_t i = 0; i < R; i++) { + offset += offsets[i] * stride * S; + stride *= shape[R - i - 1]; + } + return offset; +} + +//===----------------------------------------------------------------------===// +// RuntimeSequenceOp +//===----------------------------------------------------------------------===// + +ParseResult AIEX::RuntimeSequenceOp::parse(OpAsmParser &parser, + OperationState &result) { + StringAttr nameAttr; + (void)parser.parseOptionalSymbolName( + nameAttr, mlir::SymbolTable::getSymbolAttrName(), result.attributes); + + SmallVector entryArgs; + + // Entry arguments, e.g. (%addr: memref<1xi32>) + ParseResult argParseResult = parser.parseCommaSeparatedList( + OpAsmParser::Delimiter::Paren, [&]() -> ParseResult { + OpAsmParser::Argument argument; + if (parser.parseArgument(argument, true, true)) { + return failure(); + } + entryArgs.push_back(argument); + return success(); + }); + if (argParseResult) { + return argParseResult; + } + + auto *body = result.addRegion(); + ParseResult bodyParseResult = parser.parseRegion(*body, entryArgs, false); + if (bodyParseResult) { + return bodyParseResult; + } + + return success(); +} + +void AIEX::RuntimeSequenceOp::print(OpAsmPrinter &printer) { + Region &body = getRegion(); + + auto nameAttr = (*this)->getAttrOfType( + mlir::SymbolTable::getSymbolAttrName()); + if (nameAttr) { + printer << ' '; + printer.printSymbolName(nameAttr); + } + + printer << '('; + for (unsigned i = 0, n = body.getNumArguments(); i < n; i++) { + if (i > 0) { + printer << ", "; + } + printer.printRegionArgument(body.getArgument(i)); + } + printer << ')'; + + printer << ' '; + printer.printRegion(body, false, true); +} + +LogicalResult xilinx::AIE::myVerifyOffsetSizeAndStrideOp( + OffsetSizeAndStrideOpInterface op) { + std::array maxRanks = op.getArrayAttrMaxRanks(); + if (!(op.getMixedOffsets().size() == 1 && maxRanks[0] == 1) && // NOLINT + op.getMixedOffsets().size() != op.getMixedSizes().size()) + return op->emitError( + "expected mixed offsets rank to match mixed sizes rank (") + << op.getMixedOffsets().size() << " vs " << op.getMixedSizes().size() + << ") so the rank of the result type is well-formed."; + if (failed(verifyListOfOperandsOrIntegers( + op, "offset", maxRanks[0], op.getStaticOffsets(), op.getOffsets()))) + return failure(); + if (failed(verifyListOfOperandsOrIntegers( + op, "size", maxRanks[1], op.getStaticSizes(), op.getSizes()))) + return failure(); + if (failed(verifyListOfOperandsOrIntegers( + op, "stride", maxRanks[2], op.getStaticStrides(), op.getStrides()))) + return failure(); + for (int64_t offset : op.getStaticOffsets()) + if (offset < 0 && !ShapedType::isDynamic(offset)) + return op->emitError("expected offsets to be non-negative, but got ") + << offset; + for (int64_t size : op.getStaticSizes()) + if (size < 0 && !ShapedType::isDynamic(size)) + return op->emitError("expected sizes to be non-negative, but got ") + << size; + + return success(); +} diff --git a/compiler/plugins/target/AMD-AIE/aie/AIEXDialect.h b/compiler/plugins/target/AMD-AIE/aie/AIEXDialect.h new file mode 100644 index 000000000..445f42eec --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/AIEXDialect.h @@ -0,0 +1,36 @@ +// Copyright 2024 The IREE Authors +// +// Licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +#ifndef MLIR_AIEX_DIALECT_H +#define MLIR_AIEX_DIALECT_H + +#include "AIEDialect.h" + +namespace xilinx::AIE { +mlir::LogicalResult myVerifyOffsetSizeAndStrideOp( + mlir::OffsetSizeAndStrideOpInterface op); +template +struct MyOffsetSizeAndStrideOpInterfaceTrait + : public ::mlir::detail::OffsetSizeAndStrideOpInterfaceTrait { + static ::mlir::LogicalResult verifyTrait(::mlir::Operation *op) { + return myVerifyOffsetSizeAndStrideOp( + ::mlir::cast<::mlir::OffsetSizeAndStrideOpInterface>(op)); + } +}; + +struct MyOffsetSizeAndStrideOpInterface + : ::mlir::OffsetSizeAndStrideOpInterface { + template + struct Trait : public MyOffsetSizeAndStrideOpInterfaceTrait {}; +}; +} // namespace xilinx::AIE + +#include "aie/AIEXDialect.h.inc" + +#define GET_OP_CLASSES +#include "aie/AIEX.h.inc" + +#endif diff --git a/compiler/plugins/target/AMD-AIE/aie/AMDAIEAssignBufferAddressesBasic.cpp b/compiler/plugins/target/AMD-AIE/aie/AMDAIEAssignBufferAddressesBasic.cpp index 4e11ba9e9..7e3ea3bc3 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AMDAIEAssignBufferAddressesBasic.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AMDAIEAssignBufferAddressesBasic.cpp @@ -4,8 +4,8 @@ // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +#include "AIEDialect.h" #include "Passes.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" #include "iree-amd-aie/aie_runtime/iree_aie_runtime.h" #include "llvm/ADT/Twine.h" #include "mlir/IR/Attributes.h" @@ -41,13 +41,13 @@ struct AMDAIEAssignBufferAddressesPassBasic : mlir::OperationPass { DeviceOp device = getOperation(); int counter = 0; device.walk([&](BufferOp buffer) { - if (!buffer.hasName()) + if (!hasName(buffer)) buffer.setSymName("_anonymous" + std::to_string(counter++)); }); DenseMap> tileToBuffers; device.walk([&](BufferOp buffer) { - tileToBuffers[buffer.getTileOp()].insert(buffer); + tileToBuffers[getTileOp(*buffer)].insert(buffer); }); AMDAIEDeviceModel deviceModel = mlir::iree_compiler::AMDAIE::getDeviceModel( @@ -55,11 +55,11 @@ struct AMDAIEAssignBufferAddressesPassBasic : mlir::OperationPass { for (auto [tile, buffers] : tileToBuffers) { // Leave room at the bottom of the address range for stack int64_t address = 0; - if (auto core = tile.getCoreOp()) address += core.getStackSize(); + if (auto core = getCoreOp(tile)) address += core.getStackSize(); for (auto buffer : buffers) { buffer.setAddress(address); - address += buffer.getAllocationSize(); + address += getAllocationSize(buffer); } int maxDataMemorySize; diff --git a/compiler/plugins/target/AMD-AIE/aie/AMDAIEAssignBufferDescriptorIDs.cpp b/compiler/plugins/target/AMD-AIE/aie/AMDAIEAssignBufferDescriptorIDs.cpp index 343fe9999..890e61e01 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AMDAIEAssignBufferDescriptorIDs.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AMDAIEAssignBufferDescriptorIDs.cpp @@ -7,8 +7,8 @@ #include #include +#include "AIEDialect.h" #include "Passes.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" #include "iree-amd-aie/aie_runtime/Utils/ChannelBdIdGenerator.h" #include "iree-amd-aie/aie_runtime/iree_aie_runtime.h" #include "mlir/Pass/Pass.h" @@ -34,15 +34,12 @@ LogicalResult assignBdIds(DeviceOp deviceOp) { ChannelBdIdGenerator memTileChannelBdIdGenerator( deviceModel.getChannelToValidBdIds(AMDAIETileType::MEMTILE)); - auto memOps = llvm::to_vector_of(deviceOp.getOps()); + auto memOps = llvm::to_vector_of(deviceOp.getOps()); llvm::append_range(memOps, deviceOp.getOps()); - llvm::append_range(memOps, deviceOp.getOps()); - for (TileElement memOp : memOps) { - int col = memOp.getTileID().col; - int row = memOp.getTileID().row; - + for (Operation *memOp : memOps) { + TileOp t = getTileOp(*memOp); // BdIdGenerator gen(col, row, deviceModel); - ChannelBdIdGenerator gen = deviceModel.isMemTile(col, row) + ChannelBdIdGenerator gen = deviceModel.isMemTile(t.getCol(), t.getRow()) ? memTileChannelBdIdGenerator : shimChannelBdIdGenerator; @@ -53,7 +50,7 @@ LogicalResult assignBdIds(DeviceOp deviceOp) { DenseMap blockChannelMap; // Associate with each block the channel index specified by the // dma_start - for (Block &block : memOp.getOperation()->getRegion(0)) + for (Block &block : memOp->getRegion(0)) for (auto op : block.getOps()) { int chNum = op.getChannelIndex(); blockChannelMap[&block] = chNum; @@ -66,7 +63,7 @@ LogicalResult assignBdIds(DeviceOp deviceOp) { } } - for (Block &block : memOp.getOperation()->getRegion(0)) { + for (Block &block : memOp->getRegion(0)) { if (block.getOps().empty()) continue; assert(blockChannelMap.count(&block)); DMABDOp bd = (*block.getOps().begin()); @@ -77,15 +74,16 @@ LogicalResult assignBdIds(DeviceOp deviceOp) { std::optional bdId = gen.getAndAssignBdId(blockChannelMap[&block]); if (!bdId) - return memOp.emitOpError() + return memOp->emitOpError() << "could not find and assign a valid BD id"; bd.setBdId(bdId.value()); } } } - for (TileElement memOp : memOps) { + + for (Operation *memOp : memOps) { DenseMap blockBdIdMap; - for (Block &block : memOp.getOperation()->getRegion(0)) { + for (Block &block : memOp->getRegion(0)) { if (block.getOps().empty()) continue; DMABDOp bd = *block.getOps().begin(); assert(bd.getBdId().has_value() && @@ -93,7 +91,7 @@ LogicalResult assignBdIds(DeviceOp deviceOp) { blockBdIdMap[&block] = bd.getBdId().value(); } - for (Block &block : memOp.getOperation()->getRegion(0)) { + for (Block &block : memOp->getRegion(0)) { if (block.getOps().empty()) continue; DMABDOp bd = *block.getOps().begin(); std::optional nextBdId; diff --git a/compiler/plugins/target/AMD-AIE/aie/AMDAIEAssignLockIDs.cpp b/compiler/plugins/target/AMD-AIE/aie/AMDAIEAssignLockIDs.cpp index 162660358..3d6efe6fc 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AMDAIEAssignLockIDs.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AMDAIEAssignLockIDs.cpp @@ -11,8 +11,8 @@ // independently. If there are existing lock IDs, this pass is idempotent // and only assigns lock IDs to locks without an ID. +#include "AIEDialect.h" #include "Passes.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" #include "iree-amd-aie/aie_runtime/iree_aie_runtime.h" #include "llvm/ADT/DenseMap.h" #include "mlir/Pass/Pass.h" @@ -55,7 +55,7 @@ struct AMDAIEAssignLockIDsPass : mlir::OperationPass { // Construct data structure storing locks by tile. device.walk([&](LockOp lockOp) { - TileOp tileOp = lockOp.getTileOp(); + TileOp tileOp = xilinx::AIE::getTileOp(*lockOp); if (lockOp.getLockID().has_value()) { auto lockID = lockOp.getLockID().value(); auto iter = tileToLocks.find(tileOp); @@ -100,7 +100,7 @@ struct AMDAIEAssignLockIDsPass : mlir::OperationPass { << " locks available in this tile."; return signalPassFailure(); } - lockOp.setLockIDAttr(rewriter.getI32IntegerAttr(nextID)); + lockOp.setLockIDAttr(rewriter.getI8IntegerAttr(nextID)); ++nextID; } } diff --git a/compiler/plugins/target/AMD-AIE/aie/AMDAIECoreToStandard.cpp b/compiler/plugins/target/AMD-AIE/aie/AMDAIECoreToStandard.cpp index 55a58225c..46ee4aedb 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AMDAIECoreToStandard.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AMDAIECoreToStandard.cpp @@ -4,8 +4,8 @@ // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +#include "AIEDialect.h" #include "Passes.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" #include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVM.h" #include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVMPass.h" #include "mlir/Dialect/Arith/IR/Arith.h" @@ -35,9 +35,10 @@ struct AMDAIEUseLockToStdLowering : OpConversionPattern { if (!isa(useLock->getParentOp())) { // Generate the intrinsic name std::string funcName = "llvm.aie2."; - if (useLock.acquire() || useLock.acquireGE()) + if (useLock.getAction() == LockAction::Acquire || + useLock.getAction() == LockAction::AcquireGreaterEqual) funcName += "acquire"; - else if (useLock.release()) + else if (useLock.getAction() == LockAction::Release) funcName += "release"; // TODO(max): this can be simplified with // SymbolTable::lookupNearestSymbolFrom if DeviceOp ceases to be a @@ -47,10 +48,11 @@ struct AMDAIEUseLockToStdLowering : OpConversionPattern { funcName); SmallVector args; - int lockValue = useLock.getLockValue(); + int lockValue = useLock.getValue().value_or(1); // AIE2 acquire greater equal is encoded as a negative value. - if (useLock.acquireGE()) lockValue = -lockValue; + if (useLock.getAction() == LockAction::AcquireGreaterEqual) + lockValue = -lockValue; args.push_back(rewriter.create( useLock.getLoc(), IntegerType::get(rewriter.getContext(), 32), useLock.getLock())); @@ -84,17 +86,12 @@ struct AMDAIEBufferToStandard : OpConversionPattern { ConversionPatternRewriter &rewriter) const override { rewriter.setInsertionPointToStart(module.getBody()); auto t = llvm::cast(buffer.getType()); - int col = llvm::cast(buffer.getTile().getDefiningOp()).getCol(); - int row = llvm::cast(buffer.getTile().getDefiningOp()).getRow(); - StringRef symName = buffer.name().getValue(); - mlir::ElementsAttr initValue = buffer.getInitialValueAttr(); + StringRef symName = name(buffer).getValue(); // Don't emit initialization for cores that don't "own" the buffer (to // prevent duplication in the data section of the elf/object file) - if ((tileRow != row && tileRow != -1) || (tileCol != col && tileCol != -1)) - initValue = nullptr; rewriter.create( rewriter.getUnknownLoc(), symName, rewriter.getStringAttr("public"), - buffer.getType(), initValue, /*constant*/ false, + buffer.getType(), nullptr, /*constant*/ false, /*alignment*/ nullptr); for (OpOperand &use : make_early_inc_range(buffer.getResult().getUses())) { @@ -131,8 +128,9 @@ struct AMDAIECoreToStandardFunc : OpConversionPattern { LogicalResult matchAndRewrite( CoreOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { - int col = op.colIndex(); - int row = op.rowIndex(); + TileOp t = getTileOp(*op); + int col = t.getCol(); + int row = t.getRow(); // Only pull code for the indicated function if ((tileRow != row && tileRow != -1) || diff --git a/compiler/plugins/target/AMD-AIE/aie/AMDAIECreatePathFindFlows.cpp b/compiler/plugins/target/AMD-AIE/aie/AMDAIECreatePathFindFlows.cpp index ce2e1df1a..d531ec619 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AMDAIECreatePathFindFlows.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AMDAIECreatePathFindFlows.cpp @@ -9,12 +9,11 @@ #include #include +#include "AIEDialect.h" #include "Passes.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" #include "iree-amd-aie/aie_runtime/iree_aie_router.h" #include "iree-amd-aie/aie_runtime/iree_aie_runtime.h" #include "llvm/ADT/DenseMapInfo.h" -#include "llvm/Support/Debug.h" #include "llvm/Support/raw_os_ostream.h" #include "mlir/Pass/Pass.h" #include "mlir/Transforms/DialectConversion.h" @@ -28,7 +27,6 @@ using xilinx::AIE::DeviceOp; using xilinx::AIE::DMAChannelDir; using xilinx::AIE::EndOp; using xilinx::AIE::FlowOp; -using xilinx::AIE::Interconnect; using xilinx::AIE::MasterSetOp; using xilinx::AIE::PacketDestOp; using xilinx::AIE::PacketFlowOp; @@ -38,7 +36,6 @@ using xilinx::AIE::PacketSourceOp; using xilinx::AIE::ShimMuxOp; using xilinx::AIE::SwitchboxOp; using xilinx::AIE::TileOp; -using xilinx::AIE::WireOp; #define DEBUG_TYPE "amdaie-create-pathfinder-flows" #define OVER_CAPACITY_COEFF 0.02 @@ -47,60 +44,6 @@ using xilinx::AIE::WireOp; namespace mlir::iree_compiler::AMDAIE { -StrmSwPortType toStrmT(xilinx::AIE::WireBundle w) { - switch (w) { - case xilinx::AIE::WireBundle::Core: - return StrmSwPortType::CORE; - case xilinx::AIE::WireBundle::DMA: - return StrmSwPortType::DMA; - case xilinx::AIE::WireBundle::FIFO: - return StrmSwPortType::FIFO; - case xilinx::AIE::WireBundle::South: - return StrmSwPortType::SOUTH; - case xilinx::AIE::WireBundle::West: - return StrmSwPortType::WEST; - case xilinx::AIE::WireBundle::North: - return StrmSwPortType::NORTH; - case xilinx::AIE::WireBundle::East: - return StrmSwPortType::EAST; - case xilinx::AIE::WireBundle::NOC: - return StrmSwPortType::NOC; - case xilinx::AIE::WireBundle::Trace: - return StrmSwPortType::TRACE; - case xilinx::AIE::WireBundle::Ctrl: - return StrmSwPortType::CTRL; - default: - llvm::report_fatal_error("unhandled xilinx::AIE::WireBundle"); - } -} - -xilinx::AIE::WireBundle toWireB(StrmSwPortType w) { - switch (w) { - case StrmSwPortType::CORE: - return xilinx::AIE::WireBundle::Core; - case StrmSwPortType::DMA: - return xilinx::AIE::WireBundle::DMA; - case StrmSwPortType::FIFO: - return xilinx::AIE::WireBundle::FIFO; - case StrmSwPortType::SOUTH: - return xilinx::AIE::WireBundle::South; - case StrmSwPortType::WEST: - return xilinx::AIE::WireBundle::West; - case StrmSwPortType::NORTH: - return xilinx::AIE::WireBundle::North; - case StrmSwPortType::EAST: - return xilinx::AIE::WireBundle::East; - case StrmSwPortType::TRACE: - return xilinx::AIE::WireBundle::Trace; - case StrmSwPortType::NOC: - return xilinx::AIE::WireBundle::NOC; - case StrmSwPortType::CTRL: - return xilinx::AIE::WireBundle::Ctrl; - default: - llvm::report_fatal_error("unhandled xilinx::AIE::WireBundle"); - } -} - TileOp getOrCreateTile(OpBuilder &builder, DeviceOp &device, int col, int row) { for (auto tile : device.getOps()) { if (tile.getCol() == col && tile.getRow() == row) return tile; @@ -151,8 +94,9 @@ struct ConvertFlowsToInterconnect : OpConversionPattern { FlowOp flowOp, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { auto srcTile = llvm::cast(flowOp.getSource().getDefiningOp()); - TileLoc srcCoords = {srcTile.colIndex(), srcTile.rowIndex()}; - StrmSwPortType srcBundle = toStrmT(flowOp.getSourceBundle()); + TileLoc srcCoords = {static_cast(srcTile.getCol()), + static_cast(srcTile.getRow())}; + StrmSwPortType srcBundle = (flowOp.getSourceBundle()); int srcChannel = flowOp.getSourceChannel(); Port srcPort = {srcBundle, srcChannel}; PathEndPoint srcPe{srcCoords.col, srcCoords.row, srcPort}; @@ -185,9 +129,9 @@ struct ConvertFlowsToInterconnect : OpConversionPattern { Block &b = op->getRegion(0).front(); OpBuilder::InsertionGuard g(rewriter); rewriter.setInsertionPoint(b.getTerminator()); - rewriter.create(rewriter.getUnknownLoc(), - toWireB(conn.src.bundle), conn.src.channel, - toWireB(conn.dst.bundle), conn.dst.channel); + rewriter.create(rewriter.getUnknownLoc(), (conn.src.bundle), + conn.src.channel, (conn.dst.bundle), + conn.dst.channel); } } @@ -229,15 +173,15 @@ LogicalResult runOnPacketFlow( const std::map &flowSolutions) { mlir::DenseMap tiles; for (auto tileOp : device.getOps()) { - int col = tileOp.colIndex(); - int row = tileOp.rowIndex(); + int col = tileOp.getCol(); + int row = tileOp.getRow(); tiles[{col, row}] = tileOp; } DenseMap keepPktHeaderAttr; SwitchBoxToConnectionFlowIDT switchboxes; for (PacketFlowOp pktFlowOp : device.getOps()) { - int flowID = pktFlowOp.IDInt(); + int flowID = pktFlowOp.getID(); Port srcPort{StrmSwPortType::SS_PORT_TYPE_MAX, -1}; TileOp srcTile; TileLoc srcCoords{-1, -1}; @@ -246,13 +190,13 @@ LogicalResult runOnPacketFlow( for (Operation &Op : b.getOperations()) { if (auto pktSource = llvm::dyn_cast(Op)) { srcTile = llvm::cast(pktSource.getTile().getDefiningOp()); - srcPort = {toStrmT(pktSource.port().bundle), pktSource.port().channel}; - srcCoords = {srcTile.colIndex(), srcTile.rowIndex()}; + srcPort = {(pktSource.getBundle()), + static_cast(pktSource.getChannel())}; + srcCoords = {srcTile.getCol(), srcTile.getRow()}; } else if (auto pktDest = llvm::dyn_cast(Op)) { TileOp destTile = llvm::cast(pktDest.getTile().getDefiningOp()); - Port destPort = {toStrmT(pktDest.port().bundle), - pktDest.port().channel}; - TileLoc destCoord = {destTile.colIndex(), destTile.rowIndex()}; + Port destPort = {(pktDest.getBundle()), pktDest.getChannel()}; + TileLoc destCoord = {destTile.getCol(), destTile.getRow()}; if (pktFlowOp->hasAttr("keep_pkt_header")) keepPktHeaderAttr[PhysPort{destCoord, destPort}] = StringAttr::get(Op.getContext(), "true"); @@ -344,8 +288,8 @@ LogicalResult runOnPacketFlow( amsels.push_back(amselOps[msel]); } auto msOp = builder.create( - builder.getUnknownLoc(), builder.getIndexType(), - toWireB(tileMaster.bundle), tileMaster.channel, amsels); + builder.getUnknownLoc(), builder.getIndexType(), (tileMaster.bundle), + tileMaster.channel, amsels); if (auto pktFlowAttrs = keepPktHeaderAttr[{tileLoc, tileMaster}]) msOp->setAttr("keep_pkt_header", pktFlowAttrs); } @@ -370,7 +314,7 @@ LogicalResult runOnPacketFlow( PacketRulesOp packetrules; if (slaveRules.count(slave) == 0) { packetrules = builder.create( - builder.getUnknownLoc(), toWireB(slave.bundle), slave.channel); + builder.getUnknownLoc(), (slave.bundle), slave.channel); PacketRulesOp::ensureTerminator(packetrules.getRules(), builder, builder.getUnknownLoc()); slaveRules[slave] = packetrules; @@ -414,44 +358,43 @@ LogicalResult runOnPacketFlow( for (Operation &op : switchbox.getConnections().getOps()) { // check if there is MM2S DMA in the switchbox of the 0th row if (auto pktrules = llvm::dyn_cast(op); - pktrules && - toStrmT(pktrules.getSourceBundle()) == StrmSwPortType::DMA) { + pktrules && (pktrules.getSourceBundle()) == StrmSwPortType::DMA) { // If there is, then it should be put into the corresponding shimmux OpBuilder::InsertionGuard g(builder); Block &b0 = shimMuxOp.getConnections().front(); builder.setInsertionPointToStart(&b0); - pktrules.setSourceBundle(toWireB(StrmSwPortType::SOUTH)); + pktrules.setSourceBundle((StrmSwPortType::SOUTH)); if (pktrules.getSourceChannel() == 0) { pktrules.setSourceChannel(3); builder.create(builder.getUnknownLoc(), - toWireB(StrmSwPortType::DMA), 0, - toWireB(StrmSwPortType::NORTH), 3); + (StrmSwPortType::DMA), 0, + (StrmSwPortType::NORTH), 3); } else if (pktrules.getSourceChannel() == 1) { pktrules.setSourceChannel(7); builder.create(builder.getUnknownLoc(), - toWireB(StrmSwPortType::DMA), 1, - toWireB(StrmSwPortType::NORTH), 7); + (StrmSwPortType::DMA), 1, + (StrmSwPortType::NORTH), 7); } } // check if there is S2MM DMA in the switchbox of the 0th row if (auto mtset = llvm::dyn_cast(op); - mtset && toStrmT(mtset.getDestBundle()) == StrmSwPortType::DMA) { + mtset && (mtset.getDestBundle()) == StrmSwPortType::DMA) { // If there is, then it should be put into the corresponding shimmux OpBuilder::InsertionGuard g(builder); Block &b0 = shimMuxOp.getConnections().front(); builder.setInsertionPointToStart(&b0); - mtset.setDestBundle(toWireB(StrmSwPortType::SOUTH)); + mtset.setDestBundle((StrmSwPortType::SOUTH)); if (mtset.getDestChannel() == 0) { mtset.setDestChannel(2); builder.create(builder.getUnknownLoc(), - toWireB(StrmSwPortType::NORTH), 2, - toWireB(StrmSwPortType::DMA), 0); + (StrmSwPortType::NORTH), 2, + (StrmSwPortType::DMA), 0); } else if (mtset.getDestChannel() == 1) { mtset.setDestChannel(3); builder.create(builder.getUnknownLoc(), - toWireB(StrmSwPortType::NORTH), 3, - toWireB(StrmSwPortType::DMA), 1); + (StrmSwPortType::NORTH), 3, + (StrmSwPortType::DMA), 1); } } } @@ -478,10 +421,10 @@ void AIEPathfinderPass::runOnOperation() { std::set processedFlows; // don't be clever and remove these initializations because // then you're doing a max against garbage data... - int maxCol = 0, maxRow = 0; + uint8_t maxCol = 0, maxRow = 0; for (TileOp tileOp : device.getOps()) { - maxCol = std::max(maxCol, tileOp.colIndex()); - maxRow = std::max(maxRow, tileOp.rowIndex()); + maxCol = std::max(maxCol, tileOp.getCol()); + maxRow = std::max(maxRow, tileOp.getRow()); } AMDAIEDeviceModel deviceModel = @@ -493,11 +436,10 @@ void AIEPathfinderPass::runOnOperation() { for (FlowOp flowOp : device.getOps()) { TileOp srcTile = llvm::cast(flowOp.getSource().getDefiningOp()); TileOp dstTile = llvm::cast(flowOp.getDest().getDefiningOp()); - TileLoc srcCoords = {srcTile.colIndex(), srcTile.rowIndex()}; - TileLoc dstCoords = {dstTile.colIndex(), dstTile.rowIndex()}; - Port srcPort = {toStrmT(flowOp.getSourceBundle()), - flowOp.getSourceChannel()}; - Port dstPort = {toStrmT(flowOp.getDestBundle()), flowOp.getDestChannel()}; + TileLoc srcCoords = {srcTile.getCol(), srcTile.getRow()}; + TileLoc dstCoords = {dstTile.getCol(), dstTile.getRow()}; + Port srcPort = {(flowOp.getSourceBundle()), flowOp.getSourceChannel()}; + Port dstPort = {(flowOp.getDestBundle()), flowOp.getDestChannel()}; pathfinder.addFlow(srcCoords, srcPort, dstCoords, dstPort, false); } @@ -510,12 +452,12 @@ void AIEPathfinderPass::runOnOperation() { for (Operation &op : b.getOperations()) { if (auto pktSource = llvm::dyn_cast(op)) { srcTile = llvm::cast(pktSource.getTile().getDefiningOp()); - srcPort = {toStrmT(pktSource.port().bundle), pktSource.port().channel}; - srcCoords = {srcTile.colIndex(), srcTile.rowIndex()}; + srcPort = {(pktSource.getBundle()), pktSource.getChannel()}; + srcCoords = {srcTile.getCol(), srcTile.getRow()}; } else if (auto pktDest = llvm::dyn_cast(op)) { TileOp dstTile = llvm::cast(pktDest.getTile().getDefiningOp()); - Port dstPort = {toStrmT(pktDest.port().bundle), pktDest.port().channel}; - TileLoc dstCoords = {dstTile.colIndex(), dstTile.rowIndex()}; + Port dstPort = {(pktDest.getBundle()), pktDest.getChannel()}; + TileLoc dstCoords = {dstTile.getCol(), dstTile.getRow()}; assert(srcPort.bundle != StrmSwPortType::SS_PORT_TYPE_MAX && srcPort.channel != -1 && "expected srcPort to have been set"); assert(srcCoords.col != -1 && srcCoords.row != -1); @@ -529,13 +471,12 @@ void AIEPathfinderPass::runOnOperation() { for (SwitchboxOp switchboxOp : device.getOps()) { std::vector> connects; for (ConnectOp connectOp : switchboxOp.getOps()) { - connects.emplace_back(toStrmT(connectOp.sourcePort().bundle), - connectOp.sourcePort().channel, - toStrmT(connectOp.destPort().bundle), - connectOp.destPort().channel); + connects.emplace_back( + (connectOp.getSourceBundle()), connectOp.getSourceChannel(), + (connectOp.getDestBundle()), connectOp.getDestChannel()); } - if (!pathfinder.addFixedConnection(switchboxOp.colIndex(), - switchboxOp.rowIndex(), connects)) { + TileOp t = xilinx::AIE::getTileOp(*switchboxOp.getOperation()); + if (!pathfinder.addFixedConnection(t.getCol(), t.getRow(), connects)) { switchboxOp.emitOpError() << "Unable to add fixed connections"; return signalPassFailure(); } diff --git a/compiler/plugins/target/AMD-AIE/aie/AMDAIEDmaToNpu.cpp b/compiler/plugins/target/AMD-AIE/aie/AMDAIEDmaToNpu.cpp index b17065915..f15990681 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AMDAIEDmaToNpu.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AMDAIEDmaToNpu.cpp @@ -4,9 +4,9 @@ // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +#include "AIEDialect.h" +#include "AIEXDialect.h" #include "Passes.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" -#include "aie/Dialect/AIEX/IR/AIEXDialect.h" #include "iree-amd-aie/aie_runtime/iree_aie_runtime.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" diff --git a/compiler/plugins/target/AMD-AIE/aie/AMDAIELocalizeLocks.cpp b/compiler/plugins/target/AMD-AIE/aie/AMDAIELocalizeLocks.cpp index 284799fa2..b7dcc9e23 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AMDAIELocalizeLocks.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AMDAIELocalizeLocks.cpp @@ -4,8 +4,8 @@ // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +#include "AIEDialect.h" #include "Passes.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" #include "iree-amd-aie/aie_runtime/iree_aie_runtime.h" #include "mlir/Dialect/Arith/IR/Arith.h" #include "mlir/Pass/Pass.h" @@ -46,19 +46,19 @@ struct AMDAIELocalizeLocksPass : mlir::OperationPass { for (auto coreOp : deviceOp.getOps()) { // Collect the locks used in this core. auto thisTile = dyn_cast(coreOp.getTile().getDefiningOp()); - int col = thisTile.colIndex(); - int row = thisTile.rowIndex(); + int col = thisTile.getCol(); + int row = thisTile.getRow(); // Find the neighboring tiles SmallVector accessibleTiles; for (auto tile : deviceOp.getOps()) - if (int dstRow = tile.rowIndex(); - deviceModel.hasLegalMemAffinity(col, row, tile.colIndex(), dstRow)) + if (int dstRow = tile.getRow(); + deviceModel.hasLegalMemAffinity(col, row, tile.getCol(), dstRow)) accessibleTiles.push_back(tile); for (auto tile : accessibleTiles) { - int dstCol = tile.colIndex(); - int dstRow = tile.rowIndex(); + int dstCol = tile.getCol(); + int dstRow = tile.getRow(); int cardinalMemOffset = 0; int numLocks = deviceModel.getNumLocks(dstCol, dstRow); for (auto user : tile.getResult().getUsers()) @@ -74,7 +74,7 @@ struct AMDAIELocalizeLocksPass : mlir::OperationPass { else llvm_unreachable("Found illegal lock user!"); - int localLockIndex = cardinalMemOffset + lock.getLockIDValue(); + int localLockIndex = cardinalMemOffset + lock.getLockID().value(); OpBuilder builder = OpBuilder::atBlockBegin(&coreOp.getBody().front()); diff --git a/compiler/plugins/target/AMD-AIE/aie/AMDAIENormalizeAddressSpaces.cpp b/compiler/plugins/target/AMD-AIE/aie/AMDAIENormalizeAddressSpaces.cpp index 4e26ead7b..6d9b6b030 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AMDAIENormalizeAddressSpaces.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AMDAIENormalizeAddressSpaces.cpp @@ -4,7 +4,7 @@ // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -#include "aie/Dialect/AIE/IR/AIEDialect.h" +#include "AIEDialect.h" #include "mlir/IR/Attributes.h" #include "mlir/IR/PatternMatch.h" #include "mlir/Pass/Pass.h" @@ -27,7 +27,7 @@ Type memRefToDefaultAddressSpace(Type t) { return t; } -#include "aie/Dialect/AIE/Transforms/AIENormalizeAddressSpaces.inc" +#include "aie/AIENormalizeAddressSpaces.inc" } // namespace diff --git a/compiler/plugins/target/AMD-AIE/aie/AMDAIEObjectFifoStatefulTransform.cpp b/compiler/plugins/target/AMD-AIE/aie/AMDAIEObjectFifoStatefulTransform.cpp index df8b964a4..af73621ad 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AMDAIEObjectFifoStatefulTransform.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AMDAIEObjectFifoStatefulTransform.cpp @@ -7,8 +7,8 @@ #include #include +#include "AIEDialect.h" #include "Passes.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" #include "iree-amd-aie/aie_runtime/iree_aie_runtime.h" #include "llvm/ADT/STLExtras.h" #include "mlir/Analysis/TopologicalSortUtils.h" @@ -34,10 +34,8 @@ using xilinx::AIE::BufferOp; using xilinx::AIE::CoreOp; using xilinx::AIE::DeviceOp; using xilinx::AIE::DMABDOp; -using xilinx::AIE::DMAChannelDirAttr; using xilinx::AIE::DMAStartOp; using xilinx::AIE::EndOp; -using xilinx::AIE::ExternalBufferOp; using xilinx::AIE::FlowOp; using xilinx::AIE::LockAction; using xilinx::AIE::LockOp; @@ -48,22 +46,104 @@ using xilinx::AIE::ObjectFifoAcquireOp; using xilinx::AIE::ObjectFifoCreateOp; using xilinx::AIE::ObjectFifoLinkOp; using xilinx::AIE::ObjectFifoPort; -using xilinx::AIE::ObjectFifoRegisterExternalBuffersOp; using xilinx::AIE::ObjectFifoReleaseOp; using xilinx::AIE::ObjectFifoSubviewAccessOp; using xilinx::AIE::ShimDMAAllocationOp; -using xilinx::AIE::ShimDMAOp; using xilinx::AIE::TileOp; using xilinx::AIE::UseLockOp; using xilinx::AIE::WireBundle; +namespace { +std::vector getInputObjectFifos(ObjectFifoLinkOp &op) { + std::vector inputObjFifos; + Operation *parent = op.getOperation(); + while ((parent = parent->getParentOp())) { + if (parent->hasTrait()) { + for (auto sym : op.getFifoIns()) { + auto name = dyn_cast(sym); + if (auto *st = SymbolTable::lookupSymbolIn(parent, name); + isa_and_nonnull(st)) + inputObjFifos.push_back(dyn_cast(st)); + } + } + } + return inputObjFifos; +} + +std::vector getOutputObjectFifos(ObjectFifoLinkOp &op) { + std::vector outputObjFifos; + Operation *parent = op.getOperation(); + while ((parent = parent->getParentOp())) { + if (parent->hasTrait()) { + for (auto sym : op.getFifoOuts()) { + auto name = dyn_cast(sym); + if (auto *st = SymbolTable::lookupSymbolIn(parent, name); + isa_and_nonnull(st)) + outputObjFifos.push_back(dyn_cast(st)); + } + } + } + return outputObjFifos; +} + +int objFifoSize(ObjectFifoCreateOp op, int index = 0) { + if (llvm::isa(op.getElemNumber())) + return llvm::dyn_cast( + llvm::dyn_cast(op.getElemNumber())[index]) + .getInt(); + else + return llvm::dyn_cast(op.getElemNumber()).getInt(); +} + +template +ObjectFifoCreateOp getObjectFifo(T op) { + Operation *parent = op.getOperation(); + while ((parent = parent->getParentOp())) { + if (parent->hasTrait()) { + if (auto *st = SymbolTable::lookupSymbolIn(parent, op.getObjFifoName()); + isa_and_nonnull(st)) + return dyn_cast(st); + } + } + return {}; +} + +bool isJoin(ObjectFifoLinkOp op) { return op.getFifoIns().size() > 1; } + +bool isDistribute(ObjectFifoLinkOp op) { return op.getFifoOuts().size() > 1; } + +std::optional getOptionalSharedTile(ObjectFifoLinkOp op) { + if (isJoin(op)) { + auto fifoOut = getOutputObjectFifos(op)[0]; + for (auto fifoIn : getInputObjectFifos(op)) + if (fifoOut.getProducerTile() != fifoIn.getConsumerTiles()[0]) return {}; + return {fifoOut.getProducerTile()}; + } + + if (isDistribute(op)) { + auto fifoIn = getInputObjectFifos(op)[0]; + for (auto fifoOut : getOutputObjectFifos(op)) + if (fifoIn.getConsumerTiles()[0] != fifoOut.getProducerTile()) return {}; + return {fifoIn.getConsumerTiles()[0]}; + } + + auto fifoIn = getInputObjectFifos(op); + if (auto fifoOut = getOutputObjectFifos(op); + !fifoIn.empty() && !fifoOut.empty()) + for (auto consumerIn : fifoIn[0].getConsumerTiles()) + if (consumerIn == fifoOut[0].getProducerTile()) + return {fifoOut[0].getProducerTile()}; + return {}; +} +} // namespace + class LockAnalysis { DenseMap, int> locksPerTile; public: LockAnalysis(DeviceOp &device) { for (auto lockOp : device.getOps()) - locksPerTile[{lockOp.getTile(), lockOp.getLockIDValue()}] = 1; + locksPerTile[{lockOp.getTile(), lockOp.getLockID().value()}] = 1; } /// Given a tile, returns next usable lockID for that tile. @@ -84,8 +164,8 @@ class LockAnalysis { }; class DMAChannelAnalysis { - DenseMap producerChannelsPerTile; - DenseMap consumerChannelsPerTile; + DenseMap producerChannelsPerTile; + DenseMap consumerChannelsPerTile; public: DMAChannelAnalysis(DeviceOp &device) { @@ -122,9 +202,9 @@ enum SharedMemoryDirection { LHS = -1, RHS = 1, NONE = 0 }; std::optional getOptionalLinkOp(ObjectFifoCreateOp op) { auto device = op->getParentOfType(); for (ObjectFifoLinkOp linkOp : device.getOps()) { - for (ObjectFifoCreateOp in : linkOp.getInputObjectFifos()) + for (ObjectFifoCreateOp in : getInputObjectFifos(linkOp)) if (in == op) return {linkOp}; - for (ObjectFifoCreateOp out : linkOp.getOutputObjectFifos()) + for (ObjectFifoCreateOp out : getOutputObjectFifos(linkOp)) if (out == op) return {linkOp}; } return {}; @@ -175,13 +255,14 @@ bool requiresDMAs(ObjectFifoCreateOp createOp, for (auto consumerTile : createOp.getConsumerTiles()) { auto consumerTileOp = dyn_cast(consumerTile.getDefiningOp()); if (!consumerTileOp) continue; + TileOp producerTileOp = + cast(createOp.getProducerTile().getDefiningOp()); if (std::count(splitBecauseLink.begin(), splitBecauseLink.end(), createOp)) - shareDirection = haveSharedMemory(createOp.getProducerTileOp(), - createOp.getProducerTileOp()); + // TODO(max): wut + shareDirection = haveSharedMemory(producerTileOp, producerTileOp); else - shareDirection = - haveSharedMemory(createOp.getProducerTileOp(), consumerTileOp); + shareDirection = haveSharedMemory(producerTileOp, consumerTileOp); } if (shareDirection == LHS || shareDirection == RHS) { @@ -210,31 +291,31 @@ bool requiresDMAs(ObjectFifoCreateOp createOp, /// return 0. int findObjectFifoSize(DeviceOp &device, Value tile, ObjectFifoCreateOp objFifo) { - if (objFifo.size() == 0) return 0; + if (objFifoSize(objFifo) == 0) return 0; AMDAIEDeviceModel deviceModel = getDeviceModel(static_cast(device.getDevice())); // if memTile, size is equal to objFifo size TileOp tileOp = tile.getDefiningOp(); if (deviceModel.isMemTile(tileOp.getCol(), tileOp.getRow())) - return objFifo.size(); + return objFifoSize(objFifo); int maxAcquire = 0; for (auto coreOp : make_filter_range( device.getOps(), [&tile](auto coreOp) { return coreOp.getTile() == tile; })) coreOp.walk([&](ObjectFifoAcquireOp acqOp) { - if (acqOp.getObjectFifo() == objFifo && acqOp.acqNumber() > maxAcquire) - maxAcquire = acqOp.acqNumber(); + if (getObjectFifo(acqOp) == objFifo && acqOp.getSize() > maxAcquire) + maxAcquire = acqOp.getSize(); }); - if (maxAcquire == 1 && objFifo.size() == 1) return 1; + if (maxAcquire == 1 && objFifoSize(objFifo) == 1) return 1; // +1 because objectFifo size is always 1 bigger than maxAcquire to allow // for prefetching: simplest case scenario is at least a ping-pong buffer if (maxAcquire > 0) return maxAcquire + 1; - return objFifo.size(); + return objFifoSize(objFifo); } /// Translate ObjectFifoCreateOp to corresponding DMABD, UseLocks, and NextBDs. @@ -256,7 +337,7 @@ void createDMA( } // if none exists, create one - TileOp objFifoTileOp = target.getProducerTileOp(); + TileOp objFifoTileOp = cast(target.getProducerTile().getDefiningOp()); if (!producer) { if (device->getNumRegions() != 1) llvm::report_fatal_error("expected num regions for device op"); @@ -333,7 +414,7 @@ void createAMDAIETileDMA( const DenseMap &objFifoLinks, const DenseMap> &buffersPerFifo, const DenseMap> &locksPerFifo) { - size_t numBlocks = createOp.size(); + size_t numBlocks = objFifoSize(createOp); if (numBlocks == 0) return; // search for the buffers/locks (based on if this objFifo has a link) ObjectFifoCreateOp target = createOp; @@ -359,7 +440,7 @@ void createMemTileDMA( const DenseMap &objFifoLinks, const DenseMap> &buffersPerFifo, const DenseMap> &locksPerFifo) { - size_t numBlocks = createOp.size(); + size_t numBlocks = objFifoSize(createOp); if (numBlocks == 0) return; auto fifo = llvm::cast(createOp.getElemType()); @@ -392,13 +473,13 @@ void createMemTileDMA( if (auto linkOp = getOptionalLinkOp(createOp); objFifoLinks.contains(*linkOp)) { target = objFifoLinks.at(*linkOp); - if (linkOp->isJoin()) { + if (isJoin(*linkOp)) { // find offset based on order of this op in join list - getExtraOffset(*linkOp, linkOp->getInputObjectFifos(), + getExtraOffset(*linkOp, getInputObjectFifos(*linkOp), linkOp->getFifoIns().size()); - } else if (linkOp->isDistribute()) { + } else if (isDistribute(*linkOp)) { // find offset based on order of this op in distribute list - getExtraOffset(*linkOp, linkOp->getOutputObjectFifos(), + getExtraOffset(*linkOp, getOutputObjectFifos(*linkOp), linkOp->getFifoOuts().size()); } else if (target != createOp) { @@ -408,7 +489,7 @@ void createMemTileDMA( } // check if current createOp is of smaller size in link - if (target != createOp) numBlocks = target.size(); + if (target != createOp) numBlocks = objFifoSize(target); } createDMA(device, builder, createOp, target, channelDir, @@ -420,7 +501,8 @@ void createMemTileDMA( LogicalResult unrollForLoops(DeviceOp &device, const std::set &objectFifoTiles) { for (auto coreOp : device.getOps()) { - if (!objectFifoTiles.count(coreOp.getTileOp())) continue; + if (!objectFifoTiles.count(cast(coreOp.getTile().getDefiningOp()))) + continue; WalkResult res = coreOp.walk([&](scf::ForOp forLoop) { // look for operations on objectFifos @@ -432,8 +514,8 @@ LogicalResult unrollForLoops(DeviceOp &device, for (auto acqOp : body->getOps()) { if (acqOp.getOperation()->getParentOp() == forLoop) { found = true; - ObjectFifoCreateOp op = acqOp.getObjectFifo(); - objFifoSizes.insert(op.size()); + ObjectFifoCreateOp op = getObjectFifo(acqOp); + objFifoSizes.insert(objFifoSize(op)); } } // also counts original loop body @@ -481,8 +563,8 @@ void createUseLocks( builder.create(builder.getUnknownLoc(), lock, lockAction, numLocks); std::pair opPort = {op, static_cast(port)}; - acc[opPort] = - (acc[opPort] + numLocks) % op.size(); // update to next objFifo elem + // update to next objFifo elem + acc[opPort] = (acc[opPort] + numLocks) % objFifoSize(op); } /// Replace (not really - add) ObjectFifoReleaseOp with appropriate UseLockOp. @@ -493,10 +575,10 @@ void replaceReleaseOp( const DenseMap> &locksPerFifo, DenseMap, std::vector> &releaseOps) { - ObjectFifoCreateOp op = releaseOp.getObjectFifo(); + ObjectFifoCreateOp op = getObjectFifo(releaseOp); auto core = releaseOp->getParentOfType(); if (auto linkOp = getOptionalLinkOp(op)) - if (core.getTile() == *linkOp->getOptionalSharedTile()) + if (core.getTile() == *getOptionalSharedTile(*linkOp)) llvm::report_fatal_error( "currently cannot access objectFifo used in " "ObjectFifoLinkOp"); @@ -509,7 +591,7 @@ void replaceReleaseOp( { OpBuilder::InsertionGuard gg(builder); builder.setInsertionPointAfter(releaseOp); - createUseLocks(builder, op, port, relPerFifo, releaseOp.relNumber(), + createUseLocks(builder, op, port, relPerFifo, releaseOp.getSize(), LockAction::Release, objFifoLinks, locksPerFifo); } // register release op @@ -551,7 +633,7 @@ void splitFifo( auto consumerTileOp = cast(consumerTile.getDefiningOp()); if (isa(createOp.getElemNumber())) // +1 to account for 1st depth (producer) - consumerDepth = createOp.size(consumerIndex + 1); + consumerDepth = objFifoSize(createOp, consumerIndex + 1); else consumerDepth = findObjectFifoSize(device, consumerTileOp, createOp); @@ -560,9 +642,9 @@ void splitFifo( // rename and replace split objectFifo if (createOp.getConsumerTiles().size() > 1) consumerFifoName = - createOp.name().str() + "_" + std::to_string(consumerIndex) + "_cons"; + name(createOp).str() + "_" + std::to_string(consumerIndex) + "_cons"; else - consumerFifoName = createOp.name().str() + "_cons"; + consumerFifoName = name(createOp).str() + "_cons"; BDDimLayoutArrayAttr singletonFromStreamDims = BDDimLayoutArrayAttr::get(ctx, {consumerDims[consumerIndex]}); @@ -584,9 +666,9 @@ void splitFifo( consumerIndex++; auto linkOp = getOptionalLinkOp(createOp); if (!linkOp) continue; - for (ObjectFifoCreateOp fifoIn : linkOp->getInputObjectFifos()) - if (fifoIn.name() == createOp.name() && - consumerTile == *linkOp->getOptionalSharedTile() && + for (ObjectFifoCreateOp fifoIn : getInputObjectFifos(*linkOp)) + if (name(fifoIn) == name(createOp) && + consumerTile == *getOptionalSharedTile(*linkOp) && failed(SymbolTable::replaceAllSymbolUses( createOp, StringAttr::get(ctx, consumerFifoName), linkOp->getOperation()))) @@ -610,10 +692,10 @@ void replaceObjectAcquireOp( const DenseMap> &locksPerFifo, const DenseMap> &buffersPerFifo, DenseMap> &subviews) { - ObjectFifoCreateOp op = acquireOp.getObjectFifo(); + ObjectFifoCreateOp op = getObjectFifo(acquireOp); auto core = acquireOp->getParentOfType(); auto linkOp = getOptionalLinkOp(op); - if (linkOp && core.getTile() == *linkOp->getOptionalSharedTile()) + if (linkOp && core.getTile() == *getOptionalSharedTile(*linkOp)) llvm::report_fatal_error( "currently cannot access objectFifo used in " "ObjectFifoLinkOp"); @@ -632,7 +714,7 @@ void replaceObjectAcquireOp( // and the previous one int numRel = 0; for (auto relOp : releaseOps[opPort]) { - if (relOp.getObjectFifo() != op) continue; + if (getObjectFifo(relOp) != op) continue; Block *relBlock = relOp.getOperation()->getBlock(); Operation *relBlockDefOp = relBlock->getParentOp(); Block *relParentOpBlock = relBlockDefOp->getBlock(); @@ -649,22 +731,22 @@ void replaceObjectAcquireOp( // the ReleaseOps again later, // after the subview is created releaseOps[opPort].erase(releaseOps[opPort].begin()); - numRel += relOp.relNumber(); + numRel += relOp.getSize(); } } else if (acqBlock == relParentOpBlock) { if (!acquireOp->isBeforeInBlock(relBlockDefOp)) { releaseOps[opPort].erase(releaseOps[opPort].begin()); - numRel += relOp.relNumber(); + numRel += relOp.getSize(); } } else if (relBlock == acqParentOpBlock) { if (!acqBlockDefOp->isBeforeInBlock(relOp)) { releaseOps[opPort].erase(releaseOps[opPort].begin()); - numRel += relOp.relNumber(); + numRel += relOp.getSize(); } } else if (acqParentOpBlock == relParentOpBlock) { if (!acqBlockDefOp->isBeforeInBlock(relBlockDefOp)) { releaseOps[opPort].erase(releaseOps[opPort].begin()); - numRel += relOp.relNumber(); + numRel += relOp.getSize(); } } } @@ -685,7 +767,7 @@ void replaceObjectAcquireOp( } // acquire locks - size_t numLocks = acquireOp.acqNumber(); + size_t numLocks = acquireOp.getSize(); size_t alreadyAcq = acquiredIndices.size(); size_t numCreate = numLocks > alreadyAcq ? numLocks - alreadyAcq : 0; @@ -705,7 +787,7 @@ void replaceObjectAcquireOp( // create subview: buffers that were already acquired + new acquires for (int i = 0; i < numCreate; i++) { acquiredIndices.push_back(start); - start = (start + 1) % op.size(); + start = (start + 1) % objFifoSize(op); } std::vector subviewRefs; subviewRefs.reserve(acquiredIndices.size()); @@ -728,7 +810,9 @@ void createBuffersAndLocks( DenseMap> &locksPerFifo) { // add all tiles that contain an objectFifo to objectFifoTiles for later // loop unrolling pass - objectFifoTiles.insert(createOp.getProducerTileOp()); + TileOp producerTileOp = + cast(createOp.getProducerTile().getDefiningOp()); + objectFifoTiles.insert(producerTileOp); for (auto consumerTile : createOp.getConsumerTiles()) { auto consumerTileOp = cast(consumerTile.getDefiningOp()); objectFifoTiles.insert(consumerTileOp); @@ -739,14 +823,14 @@ void createBuffersAndLocks( if (requiresDMAs(createOp, shareDirection, splitBecauseLink)) { IntegerAttr elemNumberAttr; if (isa(createOp.getElemNumber())) - elemNumberAttr = builder.getI32IntegerAttr(createOp.size()); + elemNumberAttr = builder.getI32IntegerAttr(objFifoSize(createOp)); else elemNumberAttr = builder.getI32IntegerAttr( - findObjectFifoSize(device, createOp.getProducerTileOp(), createOp)); + findObjectFifoSize(device, producerTileOp, createOp)); createOp.setElemNumberAttr(elemNumberAttr); } - if (!createOp.size()) return; + if (!objFifoSize(createOp)) return; auto fifo = llvm::cast(createOp.getElemType()); auto elemType = llvm::cast(fifo.getElementType()); @@ -756,31 +840,31 @@ void createBuffersAndLocks( // the objFifo with elements of bigger size) auto linkOp = getOptionalLinkOp(createOp); if (linkOp) { - auto fifoIn = linkOp->getInputObjectFifos()[0], - fifoOut = linkOp->getOutputObjectFifos()[0]; + auto fifoIn = getInputObjectFifos(*linkOp)[0], + fifoOut = getOutputObjectFifos(*linkOp)[0]; // elements have already been created if (objFifoLinks.contains(*linkOp)) return; // if join, fifoOut has bigger size - if (linkOp->isJoin() && createOp.name() != fifoOut.name()) return; + if (isJoin(*linkOp) && name(createOp) != name(fifoOut)) return; // if distribute, fifoIn has bigger size - if (linkOp->isDistribute() && createOp.name() != fifoIn.name()) return; + if (isDistribute(*linkOp) && name(createOp) != name(fifoIn)) return; auto fifoInType = llvm::cast( - linkOp->getInputObjectFifos()[0].getElemType()), + getInputObjectFifos(*linkOp)[0].getElemType()), fifoOutType = llvm::cast( - linkOp->getOutputObjectFifos()[0].getElemType()); + getOutputObjectFifos(*linkOp)[0].getElemType()); auto elemInType = llvm::cast(fifoInType.getElementType()), elemOutType = llvm::cast(fifoOutType.getElementType()); int64_t inSize = elemInType.getNumElements(); if (int64_t outSize = elemOutType.getNumElements(); inSize >= outSize) { if (createOp.name() != fifoIn.name()) return; - } else if (linkOp->getOutputObjectFifos()[0] != createOp) + } else if (getOutputObjectFifos(*linkOp)[0] != createOp) return; } TileOp creationTile; if (shareDirection == NONE || shareDirection == LHS) - creationTile = createOp.getProducerTileOp(); + creationTile = producerTileOp; else creationTile = cast(createOp.getConsumerTiles()[0].getDefiningOp()); @@ -792,7 +876,7 @@ void createBuffersAndLocks( OpBuilder::InsertionGuard gg(builder); builder.setInsertionPointAfter(*std::prev(tiles.end(), 1)); - size_t numElem = createOp.size(); + size_t numElem = objFifoSize(createOp); // if shimTile external buffers are collected from input code AMDAIEDeviceModel deviceModel = getDeviceModel(static_cast(device.getDevice())); @@ -802,9 +886,9 @@ void createBuffersAndLocks( for (int ofElemIndex = 0; ofElemIndex < numElem; ofElemIndex++) { auto buff = builder.create( builder.getUnknownLoc(), elemType, creationTile, - builder.getStringAttr(createOp.name().str() + "_buff_" + + builder.getStringAttr(name(createOp).str() + "_buff_" + std::to_string(ofElemIndex)), - /*address*/ nullptr, /*initial_value*/ nullptr, + /*address*/ nullptr, /*mem_bank*/ nullptr); buffers.push_back(buff); } @@ -812,9 +896,9 @@ void createBuffersAndLocks( } if (linkOp) { - if (linkOp->isDistribute()) + if (isDistribute(*linkOp)) numElem *= linkOp->getFifoOuts().size(); - else if (linkOp->isJoin()) + else if (isJoin(*linkOp)) numElem *= linkOp->getFifoIns().size(); objFifoLinks[*linkOp] = createOp; } @@ -832,7 +916,7 @@ void createBuffersAndLocks( prodLockID, numElem); prodLock.getOperation()->setAttr( SymbolTable::getSymbolAttrName(), - builder.getStringAttr(createOp.name().str() + "_prod_lock")); + builder.getStringAttr(name(createOp).str() + "_prod_lock")); std::vector locks{prodLock}; int consLockID = lockAnalysis.getLockID(creationTile); @@ -844,7 +928,7 @@ void createBuffersAndLocks( consLockID, 0); consLock.getOperation()->setAttr( SymbolTable::getSymbolAttrName(), - builder.getStringAttr(createOp.name().str() + "_cons_lock")); + builder.getStringAttr(name(createOp).str() + "_cons_lock")); locks.push_back(consLock); locksPerFifo[createOp] = locks; @@ -865,7 +949,7 @@ void createFlowsAndTileDMAs( &objFifoLinks, &buffersPerFifo]( ObjectFifoCreateOp op, DMAChannelDir channelDir, int channelIndex, BDDimLayoutArrayAttr dims) { - auto producerOp = op.getProducerTileOp(); + TileOp producerOp = cast(op.getProducerTile().getDefiningOp()); if (deviceModel.isShimTile(producerOp.getCol(), producerOp.getRow())) return; else if (deviceModel.isMemTile(producerOp.getCol(), producerOp.getRow())) @@ -876,6 +960,9 @@ void createFlowsAndTileDMAs( objFifoLinks, buffersPerFifo, locksPerFifo); }; // create producer tile DMA + + TileOp producerProducerTileOp = + cast(producer.getProducerTile().getDefiningOp()); SwitchDMAConnection producerChan = dmaAnalysis.getProducerDMAChannel(producer.getProducerTile()); createDMA(producer, static_cast(producerChan.direction), @@ -883,12 +970,12 @@ void createFlowsAndTileDMAs( // generate objectFifo allocation info OpBuilder::InsertionGuard g(builder); builder.setInsertionPoint(&device.getBody()->back()); - if (deviceModel.isShimTile(producer.getProducerTileOp().getCol(), - producer.getProducerTileOp().getRow())) + if (deviceModel.isShimTile(producerProducerTileOp.getCol(), + producerProducerTileOp.getRow())) builder.create( builder.getUnknownLoc(), producer.getName(), static_cast(producerChan.direction), - producerChan.channel, producer.getProducerTileOp().getCol()); + producerChan.channel, producerProducerTileOp.getCol()); for (auto consumer : consumers) { // create consumer tile DMA @@ -901,12 +988,15 @@ void createFlowsAndTileDMAs( // generate objectFifo allocation info OpBuilder::InsertionGuard gg(builder); builder.setInsertionPoint(&device.getBody()->back()); - if (deviceModel.isShimTile(consumer.getProducerTileOp().getCol(), - consumer.getProducerTileOp().getRow())) + + TileOp consumerProducerTileOp = + cast(consumer.getProducerTile().getDefiningOp()); + if (deviceModel.isShimTile(consumerProducerTileOp.getCol(), + consumerProducerTileOp.getRow())) builder.create( builder.getUnknownLoc(), producer.getName(), static_cast(consumerChan.direction), - consumerChan.channel, consumer.getProducerTileOp().getCol()); + consumerChan.channel, consumerProducerTileOp.getCol()); // create flow { @@ -1029,8 +1119,7 @@ struct AMDAIEObjectFifoStatefulTransformPass : mlir::OperationPass { // Replace subview.access ops coreOp.walk([&](ObjectFifoSubviewAccessOp accessOp) { auto acqOp = accessOp.getSubview().getDefiningOp(); - if (ObjectFifoCreateOp op = acqOp.getObjectFifo(); - getOptionalLinkOp(op)) + if (ObjectFifoCreateOp op = getObjectFifo(acqOp); getOptionalLinkOp(op)) llvm::report_fatal_error( "currently cannot access objectFifo used in " "ObjectFifoLinkOp"); @@ -1056,8 +1145,7 @@ struct AMDAIEObjectFifoStatefulTransformPass : mlir::OperationPass { // Remove old ops SetVector opsToErase; device.walk([&](Operation *op) { - if (isa(op)) opsToErase.insert(op); }); diff --git a/compiler/plugins/target/AMD-AIE/aie/AMDAIEXToStandard.cpp b/compiler/plugins/target/AMD-AIE/aie/AMDAIEXToStandard.cpp index bca74d507..4e0de9c09 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AMDAIEXToStandard.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AMDAIEXToStandard.cpp @@ -4,8 +4,8 @@ // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +#include "AIEXDialect.h" #include "Passes.h" -#include "aie/Dialect/AIEX/IR/AIEXDialect.h" #include "mlir/Pass/Pass.h" #include "mlir/Transforms/DialectConversion.h" @@ -22,7 +22,8 @@ struct AMDAIEXOpRemoval : OpConversionPattern { using OpAdaptor = typename MyAIEXOp::Adaptor; ModuleOp &module; - AMDAIEXOpRemoval(MLIRContext *context, ModuleOp &m, PatternBenefit benefit = 1) + AMDAIEXOpRemoval(MLIRContext *context, ModuleOp &m, + PatternBenefit benefit = 1) : OpConversionPattern(context, benefit), module(m) {} LogicalResult matchAndRewrite( @@ -66,7 +67,6 @@ struct AMDAIEXToStandardPass : mlir::OperationPass { removepatterns.add>(m.getContext(), m); removepatterns.add>(m.getContext(), m); removepatterns.add>(m.getContext(), m); - removepatterns.add>(m.getContext(), m); removepatterns.add>(m.getContext(), m); removepatterns.add>(m.getContext(), m); removepatterns.add>(m.getContext(), m); diff --git a/compiler/plugins/target/AMD-AIE/aie/CMakeLists.txt b/compiler/plugins/target/AMD-AIE/aie/CMakeLists.txt index 101042830..db5c1e449 100644 --- a/compiler/plugins/target/AMD-AIE/aie/CMakeLists.txt +++ b/compiler/plugins/target/AMD-AIE/aie/CMakeLists.txt @@ -7,16 +7,6 @@ set(IREE_PACKAGE_ROOT_DIR "${CMAKE_CURRENT_LIST_DIR}") set(IREE_PACKAGE_ROOT_PREFIX "iree::target::amd-aie::aie") -list(APPEND IREE_COMPILER_TABLEGEN_INCLUDE_DIRS - "${IREE_MLIR_AIE_SOURCE_DIR}/include") - -iree_cc_library( - NAME - defs - INCLUDES - "${IREE_MLIR_AIE_SOURCE_DIR}/include" -) - ############################################################################### # AIE Dialect ############################################################################### @@ -25,74 +15,64 @@ iree_tablegen_library( NAME AIEAttrsGen TD_FILE - "${IREE_MLIR_AIE_SOURCE_DIR}/include/aie/Dialect/AIE/IR/AIEAttrs.td" + AIEAttrs.td OUTS - -gen-attrdef-decls Dialect/AIE/IR/AIEAttrs.h.inc - -gen-attrdef-defs Dialect/AIE/IR/AIEAttrs.cpp.inc - -gen-enum-decls Dialect/AIE/IR/AIEEnums.h.inc - -gen-enum-defs Dialect/AIE/IR/AIEEnums.cpp.inc + -gen-attrdef-decls AIEAttrs.h.inc + -gen-attrdef-defs AIEAttrs.cpp.inc + -gen-enum-decls AIEEnums.h.inc + -gen-enum-defs AIEEnums.cpp.inc ) iree_tablegen_library( NAME - AIEDialectGen + AIETypesGen TD_FILE - "${IREE_MLIR_AIE_SOURCE_DIR}/include/aie/Dialect/AIE/IR/AIE.td" + AIETypes.td OUTS - -gen-dialect-decls Dialect/AIE/IR/AIEDialect.h.inc - -gen-dialect-defs Dialect/AIE/IR/AIEDialect.cpp.inc + -gen-typedef-decls AIETypes.h.inc + -gen-typedef-defs AIETypes.cpp.inc ) iree_tablegen_library( NAME - AIEInterfacesGen + AIEDialectGen TD_FILE - "${IREE_MLIR_AIE_SOURCE_DIR}/include/aie/Dialect/AIE/IR/AIEInterfaces.td" + AIE.td OUTS - -gen-op-interface-decls Dialect/AIE/IR/AIEInterfaces.h.inc - -gen-op-interface-defs Dialect/AIE/IR/AIEInterfaces.cpp.inc + -gen-dialect-decls AIEDialect.h.inc + -gen-dialect-defs AIEDialect.cpp.inc ) +list(APPEND IREE_COMPILER_TABLEGEN_INCLUDE_DIRS + ${IREE_AMD_AIE_RUNTIME_SOURCE_DIR}) iree_tablegen_library( NAME AIEOpsGen TD_FILE - "${IREE_MLIR_AIE_SOURCE_DIR}/include/aie/Dialect/AIE/IR/AIEOps.td" + AIEOps.td OUTS - -gen-op-decls Dialect/AIE/IR/AIEOps.h.inc - -gen-op-defs Dialect/AIE/IR/AIEOps.cpp.inc -) - -iree_tablegen_library( - NAME - AIETypesGen - TD_FILE - "${IREE_MLIR_AIE_SOURCE_DIR}/include/aie/Dialect/AIE/IR/AIETypes.td" - OUTS - -gen-typedef-decls -typedefs-dialect=AIE Dialect/AIE/IR/AIETypes.h.inc - -gen-typedef-defs -typedefs-dialect=AIE Dialect/AIE/IR/AIETypes.cpp.inc + -gen-op-decls AIEOps.h.inc + -gen-op-defs AIEOps.cpp.inc ) iree_tablegen_library( NAME AIENormalizeAddressSpacesGen TD_FILE - "${IREE_MLIR_AIE_SOURCE_DIR}/include/aie/Dialect/AIE/Transforms/AIENormalizeAddressSpaces.td" + AIENormalizeAddressSpaces.td OUTS - -gen-rewriters Dialect/AIE/Transforms/AIENormalizeAddressSpaces.inc + -gen-rewriters AIENormalizeAddressSpaces.inc ) iree_cc_library( NAME AIEDialectIR SRCS - ${IREE_MLIR_AIE_SOURCE_DIR}/lib/Dialect/AIE/IR/AIEDialect.cpp - ${IREE_MLIR_AIE_SOURCE_DIR}/lib/Dialect/AIE/IR/AIETargetModel.cpp + AIEDialect.cpp DEPS - ::defs + iree-amd-aie::aie_runtime::iree_aie_runtime_static ::AIEAttrsGen ::AIEDialectGen - ::AIEInterfacesGen ::AIEOpsGen ::AIETypesGen # mlir::DataLayout::closest(mlir::Operation*) @@ -117,29 +97,28 @@ iree_tablegen_library( NAME AIEXDialectGen TD_FILE - "${IREE_MLIR_AIE_SOURCE_DIR}/include/aie/Dialect/AIEX/IR/AIEX.td" + AIEX.td OUTS - -gen-dialect-decls -dialect=aiex Dialect/AIEX/IR/AIEXDialect.h.inc - -gen-dialect-defs -dialect=aiex Dialect/AIEX/IR/AIEXDialect.cpp.inc + -gen-dialect-decls -dialect=aiex AIEXDialect.h.inc + -gen-dialect-defs -dialect=aiex AIEXDialect.cpp.inc ) iree_tablegen_library( NAME AIEXOpsGen TD_FILE - "${IREE_MLIR_AIE_SOURCE_DIR}/include/aie/Dialect/AIEX/IR/AIEX.td" + AIEX.td OUTS - -gen-op-decls Dialect/AIEX/IR/AIEX.h.inc - -gen-op-defs Dialect/AIEX/IR/AIEX.cpp.inc + -gen-op-decls AIEX.h.inc + -gen-op-defs AIEX.cpp.inc ) iree_cc_library( NAME AIEXDialectIR SRCS - ${IREE_MLIR_AIE_SOURCE_DIR}/lib/Dialect/AIEX/IR/AIEXDialect.cpp + AIEXDialect.cpp DEPS - ::defs ::AIEDialectIR ::AIEXOpsGen ::AIEXDialectGen @@ -165,7 +144,6 @@ iree_cc_library( AMDAIEObjectFifoStatefulTransform.cpp AMDAIEXToStandard.cpp DEPS - ::defs iree-amd-aie::aie_runtime::iree_aie_runtime_static ::AIEDialectIR ::AIEXDialectIR diff --git a/compiler/plugins/target/AMD-AIE/aie/Passes.h b/compiler/plugins/target/AMD-AIE/aie/Passes.h index c32580e88..347c32757 100644 --- a/compiler/plugins/target/AMD-AIE/aie/Passes.h +++ b/compiler/plugins/target/AMD-AIE/aie/Passes.h @@ -7,7 +7,7 @@ #ifndef AMDAIE_PASSES_H_ #define AMDAIE_PASSES_H_ -#include "aie/Dialect/AIE/IR/AIEDialect.h" +#include "AIEDialect.h" #include "mlir/Pass/Pass.h" namespace mlir::iree_compiler::AMDAIE { diff --git a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_dma.mlir b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_dma.mlir index 5cf17dbba..1a1fa1e51 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_dma.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_dma.mlir @@ -9,12 +9,12 @@ // CHECK: %[[FIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_0"} : memref // CHECK: %[[FIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_1"} : memref // CHECK: %[[FIFO_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_2"} : memref -// CHECK: %[[FIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 0) {init = 3 : i32, sym_name = "fifo_cons_prod_lock"} -// CHECK: %[[FIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 1) {init = 0 : i32, sym_name = "fifo_cons_cons_lock"} +// CHECK: %[[FIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 0) {init = 3 : i8, sym_name = "fifo_cons_prod_lock"} +// CHECK: %[[FIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 1) {init = 0 : i8, sym_name = "fifo_cons_cons_lock"} // CHECK: %[[FIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_0"} : memref // CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref -// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "fifo_prod_lock"} -// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} +// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "fifo_prod_lock"} +// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo_cons_lock"} // CHECK: %[[BUF83:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf83"} : memref<4xi32> // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_8_3]], DMA : 0) // CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { diff --git a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l1.mlir index 8d57fc533..6b4c7c694 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l1.mlir @@ -9,8 +9,8 @@ // CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref // CHECK: %[[FIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_2"} : memref // CHECK: %[[FIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_3"} : memref -// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i32, sym_name = "fifo_prod_lock"} -// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} +// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i8, sym_name = "fifo_prod_lock"} +// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo_cons_lock"} // CHECK: %[[BUF23:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "buf23"} : memref<4xi32> // CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { // CHECK: %[[C55_I32:.*]] = arith.constant 55 : i32 diff --git a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l2.mlir index df556aff9..da66f23e1 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l2.mlir @@ -13,18 +13,18 @@ // CHECK: %[[FIFO1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_1"} : memref<1xi32> // CHECK: %[[FIFO1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_2"} : memref<1xi32> // CHECK: %[[FIFO1_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_3"} : memref<1xi32> -// CHECK: %[[FIFO1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 0) {init = 4 : i32, sym_name = "fifo1_cons_prod_lock"} -// CHECK: %[[FIFO1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 1) {init = 0 : i32, sym_name = "fifo1_cons_cons_lock"} +// CHECK: %[[FIFO1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 0) {init = 4 : i8, sym_name = "fifo1_cons_prod_lock"} +// CHECK: %[[FIFO1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 1) {init = 0 : i8, sym_name = "fifo1_cons_cons_lock"} // CHECK: %[[FIFO0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_0"} : memref<1xi32> // CHECK: %[[FIFO0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_1"} : memref<1xi32> // CHECK: %[[FIFO0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_2"} : memref<1xi32> // CHECK: %[[FIFO0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_3"} : memref<1xi32> -// CHECK: %[[FIFO0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 4 : i32, sym_name = "fifo0_cons_prod_lock"} -// CHECK: %[[FIFO0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "fifo0_cons_cons_lock"} +// CHECK: %[[FIFO0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 4 : i8, sym_name = "fifo0_cons_prod_lock"} +// CHECK: %[[FIFO0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "fifo0_cons_cons_lock"} // CHECK: %[[FIFO0_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo0_buff_0"} : memref<1xi32> // CHECK: %[[FIFO0_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo0_buff_1"} : memref<1xi32> -// CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "fifo0_prod_lock"} -// CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "fifo0_cons_lock"} +// CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "fifo0_prod_lock"} +// CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo0_cons_lock"} // CHECK: %[[BUF83:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf83"} : memref<1xi32> // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_8_3]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_delayed_release.mlir b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_delayed_release.mlir index 394fcae06..1f1dbd3c6 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_delayed_release.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_delayed_release.mlir @@ -9,8 +9,8 @@ // CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref // CHECK: %[[FIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_2"} : memref // CHECK: %[[FIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_3"} : memref -// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i32, sym_name = "fifo_prod_lock"} -// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} +// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i8, sym_name = "fifo_prod_lock"} +// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo_cons_lock"} // CHECK: %[[BUF23:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "buf23"} : memref<4xi32> // CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { // CHECK: %[[C99_I32:.*]] = arith.constant 99 : i32 diff --git a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_static_l1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_static_l1.mlir index 138668aad..cd400e75a 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_static_l1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_static_l1.mlir @@ -14,8 +14,8 @@ // CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref // CHECK: %[[FIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_2"} : memref // CHECK: %[[FIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_3"} : memref -// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i32, sym_name = "fifo_prod_lock"} -// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} +// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i8, sym_name = "fifo_prod_lock"} +// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo_cons_lock"} // CHECK: %[[DSTBUF22:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "dstbuf22"} : memref<16xi32> // CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { // CHECK: %[[C0_I32:.*]] = arith.constant 0 : i32 diff --git a/compiler/plugins/target/AMD-AIE/aie/test/aie2_memtile_connection.mlir b/compiler/plugins/target/AMD-AIE/aie/test/aie2_memtile_connection.mlir index b333a88fe..f1e3fb759 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/aie2_memtile_connection.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/aie2_memtile_connection.mlir @@ -5,28 +5,28 @@ //CHECK: %[[T02:.*]] = aie.tile(0, 2) //CHECK: %{{.*}} = aie.switchbox(%[[T02]]) { //CHECK: %0 = aie.amsel<0> (0) -//CHECK: %1 = aie.masterset(South : 1, %0) +//CHECK: %1 = aie.masterset(SOUTH : 1, %0) //CHECK: aie.packet_rules(DMA : 0) { //CHECK: aie.rule(31, 0, %0) //CHECK: } //CHECK: } //CHECK: %{{.*}} = aie.switchbox(%[[T00]]) { -//CHECK: aie.connect +//CHECK: aie.connect //CHECK: %0 = aie.amsel<0> (0) -//CHECK: %1 = aie.masterset(South : 3, %0) -//CHECK: aie.packet_rules(North : 1) { +//CHECK: %1 = aie.masterset(SOUTH : 3, %0) +//CHECK: aie.packet_rules(NORTH : 1) { //CHECK: aie.rule(31, 0, %0) //CHECK: } //CHECK: } //CHECK: %{{.*}} = aie.shim_mux(%[[T00]]) { -//CHECK: aie.connect -//CHECK: aie.connect +//CHECK: aie.connect +//CHECK: aie.connect //CHECK: } //CHECK: %{{.*}} = aie.switchbox(%[[T01]]) { -//CHECK: aie.connect +//CHECK: aie.connect //CHECK: %0 = aie.amsel<0> (0) -//CHECK: %1 = aie.masterset(South : 1, %0) -//CHECK: aie.packet_rules(North : 1) { +//CHECK: %1 = aie.masterset(SOUTH : 1, %0) +//CHECK: aie.packet_rules(NORTH : 1) { //CHECK: aie.rule(31, 0, %0) //CHECK: } //CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/allocation_info_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/allocation_info_test.mlir index f63dc8636..749c550eb 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/allocation_info_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/allocation_info_test.mlir @@ -13,30 +13,30 @@ // CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) -// CHECK: %[[OF_OUT_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 6) {init = 0 : i32, sym_name = "of_out_1_cons_prod_lock"} -// CHECK: %[[OF_OUT_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 7) {init = 0 : i32, sym_name = "of_out_1_cons_cons_lock"} +// CHECK: %[[OF_OUT_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 6) {init = 0 : i8, sym_name = "of_out_1_cons_prod_lock"} +// CHECK: %[[OF_OUT_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 7) {init = 0 : i8, sym_name = "of_out_1_cons_cons_lock"} // CHECK: %[[OF_OUT_1_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_out_1_buff_0"} : memref<64xi16> // CHECK: %[[OF_OUT_1_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_out_1_buff_1"} : memref<64xi16> -// CHECK: %[[OF_OUT_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 2) {init = 2 : i32, sym_name = "of_out_1_prod_lock"} -// CHECK: %[[OF_OUT_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 3) {init = 0 : i32, sym_name = "of_out_1_cons_lock"} +// CHECK: %[[OF_OUT_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 2) {init = 2 : i8, sym_name = "of_out_1_prod_lock"} +// CHECK: %[[OF_OUT_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 3) {init = 0 : i8, sym_name = "of_out_1_cons_lock"} // CHECK: %[[OF_IN_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_0"} : memref<64xi16> // CHECK: %[[OF_IN_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_1"} : memref<64xi16> -// CHECK: %[[OF_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i32, sym_name = "of_in_1_cons_prod_lock"} -// CHECK: %[[OF_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i32, sym_name = "of_in_1_cons_cons_lock"} -// CHECK: %[[OF_IN_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 4) {init = 0 : i32, sym_name = "of_in_1_prod_lock"} -// CHECK: %[[OF_IN_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 5) {init = 0 : i32, sym_name = "of_in_1_cons_lock"} -// CHECK: %[[OF_OUT_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 2) {init = 0 : i32, sym_name = "of_out_0_cons_prod_lock"} -// CHECK: %[[OF_OUT_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 3) {init = 0 : i32, sym_name = "of_out_0_cons_cons_lock"} +// CHECK: %[[OF_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "of_in_1_cons_prod_lock"} +// CHECK: %[[OF_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "of_in_1_cons_cons_lock"} +// CHECK: %[[OF_IN_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 4) {init = 0 : i8, sym_name = "of_in_1_prod_lock"} +// CHECK: %[[OF_IN_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 5) {init = 0 : i8, sym_name = "of_in_1_cons_lock"} +// CHECK: %[[OF_OUT_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 2) {init = 0 : i8, sym_name = "of_out_0_cons_prod_lock"} +// CHECK: %[[OF_OUT_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 3) {init = 0 : i8, sym_name = "of_out_0_cons_cons_lock"} // CHECK: %[[OF_OUT_0_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_0_buff_0"} : memref<64xi16> // CHECK: %[[OF_OUT_0_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_0_buff_1"} : memref<64xi16> -// CHECK: %[[OF_OUT_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i32, sym_name = "of_out_0_prod_lock"} -// CHECK: %[[OF_OUT_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i32, sym_name = "of_out_0_cons_lock"} +// CHECK: %[[OF_OUT_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i8, sym_name = "of_out_0_prod_lock"} +// CHECK: %[[OF_OUT_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i8, sym_name = "of_out_0_cons_lock"} // CHECK: %[[OF_IN_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_0"} : memref<64xi16> // CHECK: %[[OF_IN_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_1"} : memref<64xi16> -// CHECK: %[[OF_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of_in_0_cons_prod_lock"} -// CHECK: %[[OF_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of_in_0_cons_cons_lock"} -// CHECK: %[[OF_IN_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i32, sym_name = "of_in_0_prod_lock"} -// CHECK: %[[OF_IN_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "of_in_0_cons_lock"} +// CHECK: %[[OF_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of_in_0_cons_prod_lock"} +// CHECK: %[[OF_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of_in_0_cons_cons_lock"} +// CHECK: %[[OF_IN_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "of_in_0_prod_lock"} +// CHECK: %[[OF_IN_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "of_in_0_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_0]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_0]], DMA : 1, %[[TILE_2_3]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/bad_npu_nd.mlir b/compiler/plugins/target/AMD-AIE/aie/test/bad_npu_nd.mlir deleted file mode 100644 index 59f3b4cd1..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/test/bad_npu_nd.mlir +++ /dev/null @@ -1,211 +0,0 @@ -// RUN: iree-opt --split-input-file --verify-diagnostics %s - -module { - aie.device(npu1_4col) { - func.func @bad_npu_nd_length(%in : memref<1920x1080xi32>, %buf : memref<32xi32>, %out : memref<1920x1080xi32>) { - %c0 = arith.constant 0 : i64 - %c1 = arith.constant 1 : i64 - %c1920 = arith.constant 1920 : i64 - %c1080 = arith.constant 1080 : i64 - // expected-error@+1 {{Size 0 exceeds the [0:1023] range}} - aiex.npu.dma_memcpy_nd (0, 0, %in[%c0,%c0,%c0,%c0][%c1,%c1,%c1080,%c1920][%c0,%c0,%c1920,%c1]) { metadata = @of_fromMem, id = 0 : i64 } : memref<1920x1080xi32> - return - } - aie.shim_dma_allocation @of_fromMem (MM2S, 0, 0) - } -} - -// ----- - -module { - aie.device(npu1_4col) { - func.func @bad_npu_nd_repeat(%in : memref<128x4x2x8xi32>, %buf : memref<32xi32>, %out : memref<8192xi32>) { - %c0 = arith.constant 0 : i64 - %c1 = arith.constant 1 : i64 - %c2 = arith.constant 2 : i64 - %c4 = arith.constant 4 : i64 - %c8 = arith.constant 8 : i64 - %c16 = arith.constant 16 : i64 - %c32 = arith.constant 32 : i64 - %c128 = arith.constant 128 : i64 - // expected-error@+1 {{Size 3 exceeds the [1:64] range}} - aiex.npu.dma_memcpy_nd (0, 0, %in[%c0,%c0,%c0,%c0][%c128,%c2,%c2,%c8][%c0,%c16,%c8,%c1]) { metadata = @of_fromMem, id = 0 : i64 } : memref<128x4x2x8xi32> - return - } - aie.shim_dma_allocation @of_fromMem (MM2S, 0, 0) - } -} - -// ----- - -module { - aie.device(npu1_4col) { - func.func @bad_npu_nd_stride(%in : memref<8388608xi32>, %buf : memref<32xi32>, %out : memref<8388608xi32>) { - %c0 = arith.constant 0 : i64 - %c1 = arith.constant 1 : i64 - %c2 = arith.constant 2 : i64 - %c2097152 = arith.constant 2097152 : i64 - // expected-error@+1 {{Stride 1 exceeds the [1:1048576] range}} - aiex.npu.dma_memcpy_nd (0, 0, %in[%c0,%c0,%c0,%c0][%c1,%c1,%c2,%c2][%c0,%c0,%c2097152,%c1]) { metadata = @of_fromMem, id = 0 : i64 } : memref<8388608xi32> - return - } - aie.shim_dma_allocation @of_fromMem (MM2S, 0, 0) - } -} - -// ----- - -// Offsets need to be 4-byte aligned. - -module { - aie.device(npu1_4col) { - func.func @bad_npu_nd_stride(%a : memref<8xi8>) { - %c0 = arith.constant 0 : i64 - %c1 = arith.constant 1 : i64 - %c2 = arith.constant 2 : i64 - %c8 = arith.constant 8 : i64 - // expected-error@+1 {{Offset must be 4-byte-aligned}} - aiex.npu.dma_memcpy_nd (0, 0, %a[%c0,%c0,%c0,%c1][%c1,%c1,%c1,%c8][%c0,%c0,%c1,%c1]) { metadata = @fifo, id = 0 : i64 } : memref<8xi8> - return - } - aie.shim_dma_allocation @fifo (MM2S, 0, 0) - } -} - -// ----- - -// Strides and sizes expressed in types other than i32 should not overflow hardware limitations when converted to 4-byte granularity. -// The following tests check this. - -module { - aie.device(npu1_4col) { - func.func @bad_npu_nd(%a : memref<8xi8>) { - %c0 = arith.constant 0 : i64 - %c1 = arith.constant 1 : i64 - %c2 = arith.constant 2 : i64 - %c4 = arith.constant 4 : i64 - %c8 = arith.constant 8 : i64 - %c2048 = arith.constant 2048 : i64 - // Although 2048 exceeds the 0:1023 limit for size 0, since the elements are i8s, - // this should be a size of 512 in address granularity (4 bytes) and hence pass the test. - aiex.npu.dma_memcpy_nd (0, 0, %a[%c0,%c0,%c0,%c0][%c1,%c1,%c2,%c2048][%c0,%c0,%c4,%c1]) { metadata = @objectfifo, id = 0 : i64 } : memref<8xi8> - return - } - aie.shim_dma_allocation @objectfifo (MM2S, 0, 0) - } -} - -// ----- - -module { - aie.device(npu1_4col) { - func.func @bad_npu_nd(%a : memref<8xi16>) { - %c0 = arith.constant 0 : i64 - %c1 = arith.constant 1 : i64 - %c2 = arith.constant 2 : i64 - %c4 = arith.constant 4 : i64 - %c8 = arith.constant 8 : i64 - %c2048 = arith.constant 2048 : i64 - // expected-error@+1 {{Size 0 exceeds the [0:1023] range}} - aiex.npu.dma_memcpy_nd (0, 0, %a[%c0,%c0,%c0,%c0][%c1,%c1,%c2,%c2048][%c0,%c0,%c4,%c1]) { metadata = @objectfifo, id = 0 : i64 } : memref<8xi16> - return - } - aie.shim_dma_allocation @objectfifo (MM2S, 0, 0) - } -} - -// ----- - -// Strides and sizes are expressed at 4-byte-granularity in hardware, but we express them at memref element type granularity. -// The following tests make sure the proper errors are generated when this is not possible. - -module { - aie.device(npu1_4col) { - func.func @bad_npu_nd(%a : memref<8xi8>) { - %c0 = arith.constant 0 : i64 - %c1 = arith.constant 1 : i64 - %c2 = arith.constant 2 : i64 // Stride of 2 i8s = 2 bytes < 4 byte granularity, should not be possible - %c8 = arith.constant 8 : i64 - // expected-error@+1 {{Stride 1 is 2 elements * 1 bytes = 2 bytes, which is not divisible by 4}} - aiex.npu.dma_memcpy_nd (0, 0, %a[%c0,%c0,%c0,%c0][%c1,%c1,%c1,%c8][%c0,%c0,%c2,%c1]) { metadata = @objectfifo, id = 0 : i64 } : memref<8xi8> - return - } - aie.shim_dma_allocation @objectfifo (MM2S, 0, 0) - } -} - -// ----- - -module { - aie.device(npu1_4col) { - func.func @bad_npu_nd(%a : memref<8xi8>) { - %c0 = arith.constant 0 : i64 - %c1 = arith.constant 1 : i64 - %c2 = arith.constant 2 : i64 - %c4 = arith.constant 4 : i64 - %c8 = arith.constant 8 : i64 - // expected-error@+1 {{2 elements at 1 bytes each equal 2 bytes, which is not divisible by 4}} - aiex.npu.dma_memcpy_nd (0, 0, %a[%c0,%c0,%c0,%c0][%c1,%c1,%c1,%c2][%c0,%c0,%c4,%c1]) { metadata = @objectfifo, id = 0 : i64 } : memref<8xi8> - return - } - aie.shim_dma_allocation @objectfifo (MM2S, 0, 0) - } -} - -// ----- - -// stride of 2 i8 is not ok - -module { - aie.device(npu1_4col) { - func.func @bad_npu_nd(%a : memref<8xi8>) { - %c0 = arith.constant 0 : i64 - %c1 = arith.constant 1 : i64 - %c2 = arith.constant 2 : i64 - %c4 = arith.constant 4 : i64 - %c8 = arith.constant 8 : i64 - // expected-error@+1 {{Stride 0 is 2 elements * 1 bytes = 2 bytes, which is not divisible by 4}} - aiex.npu.dma_memcpy_nd (0, 0, %a[%c0,%c0,%c0,%c0][%c1,%c1,%c1,%c8][%c0,%c0,%c0,%c2]) { metadata = @objectfifo, id = 0 : i64 } : memref<8xi8> - return - } - aie.shim_dma_allocation @objectfifo (MM2S, 0, 0) - } -} - -// ----- - -// stride of 1 i16 is ok, but not with size of 3xi16 - -module { - aie.device(npu1_4col) { - func.func @bad_npu_nd(%a : memref<8xi16>) { - %c0 = arith.constant 0 : i64 - %c1 = arith.constant 1 : i64 - %c3 = arith.constant 3 : i64 - %c8 = arith.constant 8 : i64 - // expected-error@+1 {{3 elements at 2 bytes each equal 6 bytes, which is not divisible by 4}} - aiex.npu.dma_memcpy_nd (0, 0, %a[%c0,%c0,%c0,%c0][%c1,%c1,%c1,%c3][%c0,%c0,%c0,%c1]) { metadata = @objectfifo, id = 0 : i64 } : memref<8xi16> - return - } - aie.shim_dma_allocation @objectfifo (MM2S, 0, 0) - } -} - -// ----- - -// bad tile - -module { - aie.device(npu1) { - func.func @bad_npu_nd(%a : memref<8xi16>) { - %c0 = arith.constant 0 : i64 - %c1 = arith.constant 1 : i64 - %c4 = arith.constant 4 : i64 - %c8 = arith.constant 8 : i64 - // expected-error@+1 {{Unsupported tile type at (0, 0) Must be ShimNOC, Mem or Core.}} - aiex.npu.dma_memcpy_nd (0, 0, %a[%c0,%c0,%c0,%c0][%c1,%c1,%c1,%c4][%c0,%c0,%c0,%c1]) { metadata = @objectfifo, id = 0 : i64 } : memref<8xi16> - return - } - aie.shim_dma_allocation @objectfifo (MM2S, 0, 0) - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE1.mlir index 57edf239e..0dcd6c415 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE1.mlir @@ -10,18 +10,18 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} // CHECK: %[[OF1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_0"} : memref<16xi32> // CHECK: %[[OF1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_1"} : memref<16xi32> -// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i32, sym_name = "of1_prod_lock"} -// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "of1_cons_lock"} +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i8, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i8, sym_name = "of1_cons_lock"} // CHECK: %[[OF0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_0"} : memref<16xi32> // CHECK: %[[OF0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_1"} : memref<16xi32> // CHECK: %[[OF0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_2"} : memref<16xi32> // CHECK: %[[OF0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_3"} : memref<16xi32> -// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "of0_prod_lock"} -// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of0_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { // CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE2.mlir index db86e19c1..90fee594c 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE2.mlir @@ -10,18 +10,18 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} // CHECK: %[[OF1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_0"} : memref<16xi32> // CHECK: %[[OF1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_1"} : memref<16xi32> -// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i32, sym_name = "of1_prod_lock"} -// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "of1_cons_lock"} +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i8, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i8, sym_name = "of1_cons_lock"} // CHECK: %[[OF0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_0"} : memref<16xi32> // CHECK: %[[OF0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_1"} : memref<16xi32> // CHECK: %[[OF0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_2"} : memref<16xi32> // CHECK: %[[OF0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_3"} : memref<16xi32> -// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "of0_prod_lock"} -// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of0_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { // CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/basic.mlir b/compiler/plugins/target/AMD-AIE/aie/test/basic.mlir index d54043534..e1c7ebf8f 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/basic.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/basic.mlir @@ -5,9 +5,9 @@ // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[IN:.*]] = aie.buffer(%[[TILE_2_1]]) {address = 8192 : i32, sym_name = "in"} : memref<16xi32> // CHECK: %[[OUT:.*]] = aie.buffer(%[[TILE_2_1]]) {address = 1824 : i32, sym_name = "out"} : memref<16xi32> -// CHECK: %[[LOCK_2_1:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 1 : i32} +// CHECK: %[[LOCK_2_1:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 1 : i8} // CHECK: %[[LOCK_2_1_0:.*]] = aie.lock(%[[TILE_2_1]], 1) -// CHECK: %[[LOCK_2_1_1:.*]] = aie.lock(%[[TILE_2_1]], 2) {init = 1 : i32} +// CHECK: %[[LOCK_2_1_1:.*]] = aie.lock(%[[TILE_2_1]], 2) {init = 1 : i8} // CHECK: %[[LOCK_2_1_2:.*]] = aie.lock(%[[TILE_2_1]], 3) // CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { // CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb4, ^bb1) @@ -47,9 +47,9 @@ module @aie_module { %t01 = aie.tile(2, 1) %buf01_0 = aie.buffer(%t01) { address = 8192 : i32, sym_name = "in" } : memref<16xi32> %buf01_1 = aie.buffer(%t01) { address = 1824 : i32, sym_name = "out" } : memref<16xi32> - %l01_0 = aie.lock(%t01, 0) { init = 1 : i32 } + %l01_0 = aie.lock(%t01, 0) { init = 1 : i8 } %l01_1 = aie.lock(%t01, 1) - %l01_2 = aie.lock(%t01, 2) { init = 1 : i32 } + %l01_2 = aie.lock(%t01, 2) { init = 1 : i8 } %l01_3 = aie.lock(%t01, 3) %m01 = aie.memtile_dma(%t01) { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^dma0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/broadcast_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/broadcast_test.mlir index e5712f29d..a3ddf59ab 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/broadcast_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/broadcast_test.mlir @@ -14,28 +14,28 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[BROADCAST_OF_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "broadcast_of_0_cons_buff_0"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "broadcast_of_0_cons_buff_1"} : memref<16xi32> -// CHECK: %[[BROADCAST_OF_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i32, sym_name = "broadcast_of_0_cons_prod_lock"} -// CHECK: %[[BROADCAST_OF_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "broadcast_of_0_cons_cons_lock"} +// CHECK: %[[BROADCAST_OF_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "broadcast_of_0_cons_prod_lock"} +// CHECK: %[[BROADCAST_OF_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "broadcast_of_0_cons_cons_lock"} // CHECK: %[[BROADCAST_OF_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_4]]) {sym_name = "broadcast_of_1_cons_buff_0"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_4]]) {sym_name = "broadcast_of_1_cons_buff_1"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_1_4]]) {sym_name = "broadcast_of_1_cons_buff_2"} : memref<16xi32> -// CHECK: %[[BROADCAST_OF_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_4]], 0) {init = 3 : i32, sym_name = "broadcast_of_1_cons_prod_lock"} -// CHECK: %[[BROADCAST_OF_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_4]], 1) {init = 0 : i32, sym_name = "broadcast_of_1_cons_cons_lock"} +// CHECK: %[[BROADCAST_OF_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_4]], 0) {init = 3 : i8, sym_name = "broadcast_of_1_cons_prod_lock"} +// CHECK: %[[BROADCAST_OF_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_4]], 1) {init = 0 : i8, sym_name = "broadcast_of_1_cons_cons_lock"} // CHECK: %[[BROADCAST_OF_2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "broadcast_of_2_cons_buff_0"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "broadcast_of_2_cons_buff_1"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_2_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "broadcast_of_2_cons_buff_2"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_2_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "broadcast_of_2_cons_buff_3"} : memref<16xi32> -// CHECK: %[[BROADCAST_OF_2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 0) {init = 4 : i32, sym_name = "broadcast_of_2_cons_prod_lock"} -// CHECK: %[[BROADCAST_OF_2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 1) {init = 0 : i32, sym_name = "broadcast_of_2_cons_cons_lock"} +// CHECK: %[[BROADCAST_OF_2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 0) {init = 4 : i8, sym_name = "broadcast_of_2_cons_prod_lock"} +// CHECK: %[[BROADCAST_OF_2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 1) {init = 0 : i8, sym_name = "broadcast_of_2_cons_cons_lock"} // CHECK: %[[BROADCAST_OF_3_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "broadcast_of_3_cons_buff_0"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_3_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "broadcast_of_3_cons_buff_1"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_3_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "broadcast_of_3_cons_buff_2"} : memref<16xi32> -// CHECK: %[[BROADCAST_OF_3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 3 : i32, sym_name = "broadcast_of_3_cons_prod_lock"} -// CHECK: %[[BROADCAST_OF_3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "broadcast_of_3_cons_cons_lock"} +// CHECK: %[[BROADCAST_OF_3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 3 : i8, sym_name = "broadcast_of_3_cons_prod_lock"} +// CHECK: %[[BROADCAST_OF_3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "broadcast_of_3_cons_cons_lock"} // CHECK: %[[BROADCAST_OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "broadcast_of_buff_0"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "broadcast_of_buff_1"} : memref<16xi32> -// CHECK: %[[BROADCAST_OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 2 : i32, sym_name = "broadcast_of_prod_lock"} -// CHECK: %[[BROADCAST_OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i32, sym_name = "broadcast_of_cons_lock"} +// CHECK: %[[BROADCAST_OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 2 : i8, sym_name = "broadcast_of_prod_lock"} +// CHECK: %[[BROADCAST_OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i8, sym_name = "broadcast_of_cons_lock"} // CHECK: aie.flow(%[[TILE_1_3]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_3]], DMA : 0, %[[TILE_3_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_3]], DMA : 0, %[[TILE_1_4]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/circuit_and_packet_routing.mlir b/compiler/plugins/target/AMD-AIE/aie/test/circuit_and_packet_routing.mlir index c310762bb..3f329ed6d 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/circuit_and_packet_routing.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/circuit_and_packet_routing.mlir @@ -5,14 +5,14 @@ // CHECK: %[[VAL_1:.*]] = aie.switchbox(%[[VAL_0:.*]]) { // CHECK: %[[VAL_2:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_3:.*]] = aie.masterset(DMA : 1, %[[VAL_2:.*]]) -// CHECK: aie.packet_rules(North : 0) { +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(31, 10, %[[VAL_2:.*]]) // CHECK: } // CHECK: } // CHECK: %[[VAL_5:.*]] = aie.tile(7, 3) // CHECK: %[[VAL_6:.*]] = aie.switchbox(%[[VAL_5:.*]]) { // CHECK: %[[VAL_7:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_8:.*]] = aie.masterset(South : 0, %[[VAL_7:.*]]) +// CHECK: %[[VAL_8:.*]] = aie.masterset(SOUTH : 0, %[[VAL_7:.*]]) // CHECK: aie.packet_rules(DMA : 0) { // CHECK: aie.rule(31, 10, %[[VAL_7:.*]]) // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/cyclostatic_AIE2_sharedMem.mlir b/compiler/plugins/target/AMD-AIE/aie/test/cyclostatic_AIE2_sharedMem.mlir index 48c48ab95..7b69a46fa 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/cyclostatic_AIE2_sharedMem.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/cyclostatic_AIE2_sharedMem.mlir @@ -9,8 +9,8 @@ // CHECK: %[[FIFO0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "fifo0_buff_1"} : memref<16xi32> // CHECK: %[[FIFO0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "fifo0_buff_2"} : memref<16xi32> // CHECK: %[[FIFO0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "fifo0_buff_3"} : memref<16xi32> -// CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "fifo0_prod_lock"} -// CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "fifo0_cons_lock"} +// CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "fifo0_prod_lock"} +// CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "fifo0_cons_lock"} // CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { // CHECK: %[[C11_I32:.*]] = arith.constant 11 : i32 // CHECK: %[[C0:.*]] = arith.constant 0 : index diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE1.mlir index 4af29d782..b59acc898 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE1.mlir @@ -11,14 +11,14 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[OF2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of2_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of2_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of2_cons_prod_lock"} -// CHECK: %[[OF2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of2_cons_cons_lock"} +// CHECK: %[[OF2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of2_cons_prod_lock"} +// CHECK: %[[OF2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of2_cons_cons_lock"} // CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} -// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i32, sym_name = "of1_prod_lock"} -// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "of1_cons_lock"} +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "of1_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_1_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: %[[EXT_BUFF_IN:.*]] = aie.external_buffer {sym_name = "ext_buff_in"} : memref<16xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE2.mlir index 64f88811f..6d2494a7c 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE2.mlir @@ -15,12 +15,12 @@ // CHECK: %[[MEM_OUT_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_3]]) {sym_name = "mem_out_cons_buff_1"} : memref<3000xi32> // CHECK: %[[MEM_OUT_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_0_3]]) {sym_name = "mem_out_cons_buff_2"} : memref<3000xi32> // CHECK: %[[MEM_OUT_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_0_3]]) {sym_name = "mem_out_cons_buff_3"} : memref<3000xi32> -// CHECK: %[[MEM_OUT_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_3]], 0) {init = 4 : i32, sym_name = "mem_out_cons_prod_lock"} -// CHECK: %[[MEM_OUT_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_3]], 1) {init = 0 : i32, sym_name = "mem_out_cons_cons_lock"} +// CHECK: %[[MEM_OUT_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_3]], 0) {init = 4 : i8, sym_name = "mem_out_cons_prod_lock"} +// CHECK: %[[MEM_OUT_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_3]], 1) {init = 0 : i8, sym_name = "mem_out_cons_cons_lock"} // CHECK: %[[MEM_IN_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "mem_in_0_cons_buff_0"} : memref<3000xi32> // CHECK: %[[MEM_IN_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "mem_in_0_cons_buff_1"} : memref<3000xi32> -// CHECK: %[[MEM_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 0) {init = 2 : i32, sym_name = "mem_in_0_cons_prod_lock"} -// CHECK: %[[MEM_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 1) {init = 0 : i32, sym_name = "mem_in_0_cons_cons_lock"} +// CHECK: %[[MEM_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 0) {init = 2 : i8, sym_name = "mem_in_0_cons_prod_lock"} +// CHECK: %[[MEM_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 1) {init = 0 : i8, sym_name = "mem_in_0_cons_cons_lock"} // CHECK: %[[MEM_IN_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_0"} : memref<3000xi32> // CHECK: %[[MEM_IN_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_1"} : memref<3000xi32> // CHECK: %[[MEM_IN_1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_2"} : memref<3000xi32> @@ -28,10 +28,10 @@ // CHECK: %[[MEM_IN_1_CONS_BUFF_4:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_4"} : memref<3000xi32> // CHECK: %[[MEM_IN_1_CONS_BUFF_5:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_5"} : memref<3000xi32> // CHECK: %[[MEM_IN_1_CONS_BUFF_6:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_6"} : memref<3000xi32> -// CHECK: %[[MEM_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 0) {init = 7 : i32, sym_name = "mem_in_1_cons_prod_lock"} -// CHECK: %[[MEM_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 1) {init = 0 : i32, sym_name = "mem_in_1_cons_cons_lock"} -// CHECK: %[[MEM_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 0) {init = 0 : i32, sym_name = "mem_in_prod_lock"} -// CHECK: %[[MEM_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 1) {init = 0 : i32, sym_name = "mem_in_cons_lock"} +// CHECK: %[[MEM_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 0) {init = 7 : i8, sym_name = "mem_in_1_cons_prod_lock"} +// CHECK: %[[MEM_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 1) {init = 0 : i8, sym_name = "mem_in_1_cons_cons_lock"} +// CHECK: %[[MEM_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 0) {init = 0 : i8, sym_name = "mem_in_prod_lock"} +// CHECK: %[[MEM_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 1) {init = 0 : i8, sym_name = "mem_in_cons_lock"} // CHECK: aie.flow(%[[TILE_0_0]], DMA : 0, %[[TILE_0_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_0_0]], DMA : 0, %[[TILE_0_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_0_1]], DMA : 0, %[[TILE_0_3]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_DDR_to_L1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_DDR_to_L1.mlir index f6e2fd751..155227d6d 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_DDR_to_L1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_DDR_to_L1.mlir @@ -11,14 +11,14 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[FROM_MEMTILE_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "from_memTile_cons_buff_0"} : memref<16xi32> // CHECK: %[[FROM_MEMTILE_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "from_memTile_cons_buff_1"} : memref<16xi32> -// CHECK: %[[FROM_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "from_memTile_cons_prod_lock"} -// CHECK: %[[FROM_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "from_memTile_cons_cons_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "from_memTile_cons_prod_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "from_memTile_cons_cons_lock"} // CHECK: %[[TO_MEMTILE_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "to_memTile_cons_buff_0"} : memref<16xi32> // CHECK: %[[TO_MEMTILE_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "to_memTile_cons_buff_1"} : memref<16xi32> -// CHECK: %[[TO_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i32, sym_name = "to_memTile_cons_prod_lock"} -// CHECK: %[[TO_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "to_memTile_cons_cons_lock"} -// CHECK: %[[TO_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i32, sym_name = "to_memTile_prod_lock"} -// CHECK: %[[TO_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "to_memTile_cons_lock"} +// CHECK: %[[TO_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i8, sym_name = "to_memTile_cons_prod_lock"} +// CHECK: %[[TO_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "to_memTile_cons_cons_lock"} +// CHECK: %[[TO_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "to_memTile_prod_lock"} +// CHECK: %[[TO_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "to_memTile_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: %[[EXT_BUFF_IN:.*]] = aie.external_buffer {sym_name = "ext_buff_in"} : memref<16xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_L1_to_DDR.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_L1_to_DDR.mlir index dc73db93b..d52d199e1 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_L1_to_DDR.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_L1_to_DDR.mlir @@ -9,16 +9,16 @@ // CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[FROM_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i32, sym_name = "from_memTile_cons_prod_lock"} -// CHECK: %[[FROM_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "from_memTile_cons_cons_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "from_memTile_cons_prod_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "from_memTile_cons_cons_lock"} // CHECK: %[[FROM_MEMTILE_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "from_memTile_buff_0"} : memref<48xi32> // CHECK: %[[FROM_MEMTILE_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "from_memTile_buff_1"} : memref<48xi32> -// CHECK: %[[FROM_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i32, sym_name = "from_memTile_prod_lock"} -// CHECK: %[[FROM_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "from_memTile_cons_lock"} +// CHECK: %[[FROM_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i8, sym_name = "from_memTile_prod_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "from_memTile_cons_lock"} // CHECK: %[[TO_MEMTILE_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "to_memTile_buff_0"} : memref<16xi32> // CHECK: %[[TO_MEMTILE_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "to_memTile_buff_1"} : memref<16xi32> -// CHECK: %[[TO_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "to_memTile_prod_lock"} -// CHECK: %[[TO_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "to_memTile_cons_lock"} +// CHECK: %[[TO_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "to_memTile_prod_lock"} +// CHECK: %[[TO_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "to_memTile_cons_lock"} // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_0]], DMA : 0) // CHECK: %[[EXT_BUFF_IN:.*]] = aie.external_buffer {sym_name = "ext_buff_in"} : memref<48xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_broadcast.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_broadcast.mlir index 6a01f7e64..b7278a5e5 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_broadcast.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_broadcast.mlir @@ -15,27 +15,27 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[SKIP_CONNECTION_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "skip_connection_cons_buff_0"} : memref<16xi32> // CHECK: %[[SKIP_CONNECTION_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "skip_connection_cons_buff_1"} : memref<16xi32> -// CHECK: %[[SKIP_CONNECTION_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 2) {init = 2 : i32, sym_name = "skip_connection_cons_prod_lock"} -// CHECK: %[[SKIP_CONNECTION_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 3) {init = 0 : i32, sym_name = "skip_connection_cons_cons_lock"} +// CHECK: %[[SKIP_CONNECTION_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 2) {init = 2 : i8, sym_name = "skip_connection_cons_prod_lock"} +// CHECK: %[[SKIP_CONNECTION_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 3) {init = 0 : i8, sym_name = "skip_connection_cons_cons_lock"} // CHECK: %[[SKIP_CONNECTION_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "skip_connection_buff_0"} : memref<16xi32> // CHECK: %[[SKIP_CONNECTION_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "skip_connection_buff_1"} : memref<16xi32> -// CHECK: %[[SKIP_CONNECTION_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i32, sym_name = "skip_connection_prod_lock"} -// CHECK: %[[SKIP_CONNECTION_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i32, sym_name = "skip_connection_cons_lock"} +// CHECK: %[[SKIP_CONNECTION_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i8, sym_name = "skip_connection_prod_lock"} +// CHECK: %[[SKIP_CONNECTION_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i8, sym_name = "skip_connection_cons_lock"} // CHECK: %[[LINK2_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_0_cons_buff_0"} : memref<16xi32> // CHECK: %[[LINK2_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_0_cons_buff_1"} : memref<16xi32> -// CHECK: %[[LINK2_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "link2_0_cons_prod_lock"} -// CHECK: %[[LINK2_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "link2_0_cons_cons_lock"} +// CHECK: %[[LINK2_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "link2_0_cons_prod_lock"} +// CHECK: %[[LINK2_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "link2_0_cons_cons_lock"} // CHECK: %[[LINK2_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link2_1_cons_buff_0"} : memref<16xi32> // CHECK: %[[LINK2_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link2_1_cons_buff_1"} : memref<16xi32> // CHECK: %[[LINK2_1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link2_1_cons_buff_2"} : memref<16xi32> -// CHECK: %[[LINK2_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 3 : i32, sym_name = "link2_1_cons_prod_lock"} -// CHECK: %[[LINK2_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "link2_1_cons_cons_lock"} +// CHECK: %[[LINK2_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 3 : i8, sym_name = "link2_1_cons_prod_lock"} +// CHECK: %[[LINK2_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "link2_1_cons_cons_lock"} // CHECK: %[[LINK1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link1_cons_buff_0"} : memref<48xi32> // CHECK: %[[LINK1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link1_cons_buff_1"} : memref<48xi32> -// CHECK: %[[LINK1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i32, sym_name = "link1_cons_prod_lock"} -// CHECK: %[[LINK1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "link1_cons_cons_lock"} -// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i32, sym_name = "link1_prod_lock"} -// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "link1_cons_lock"} +// CHECK: %[[LINK1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i8, sym_name = "link1_cons_prod_lock"} +// CHECK: %[[LINK1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "link1_cons_cons_lock"} +// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "link1_prod_lock"} +// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "link1_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_distribute.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_distribute.mlir index 9dcadcfb2..5ed3b5782 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_distribute.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_distribute.mlir @@ -17,22 +17,22 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[LINK4_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link4_cons_buff_0"} : memref<12xi32> // CHECK: %[[LINK4_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link4_cons_buff_1"} : memref<12xi32> -// CHECK: %[[LINK4_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "link4_cons_prod_lock"} -// CHECK: %[[LINK4_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "link4_cons_cons_lock"} +// CHECK: %[[LINK4_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "link4_cons_prod_lock"} +// CHECK: %[[LINK4_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "link4_cons_cons_lock"} // CHECK: %[[LINK3_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "link3_cons_buff_0"} : memref<20xi32> // CHECK: %[[LINK3_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "link3_cons_buff_1"} : memref<20xi32> -// CHECK: %[[LINK3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i32, sym_name = "link3_cons_prod_lock"} -// CHECK: %[[LINK3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i32, sym_name = "link3_cons_cons_lock"} +// CHECK: %[[LINK3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "link3_cons_prod_lock"} +// CHECK: %[[LINK3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "link3_cons_cons_lock"} // CHECK: %[[LINK2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_cons_buff_0"} : memref<4x4xi32> // CHECK: %[[LINK2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_cons_buff_1"} : memref<4x4xi32> -// CHECK: %[[LINK2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "link2_cons_prod_lock"} -// CHECK: %[[LINK2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "link2_cons_cons_lock"} +// CHECK: %[[LINK2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "link2_cons_prod_lock"} +// CHECK: %[[LINK2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "link2_cons_cons_lock"} // CHECK: %[[LINK1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link1_cons_buff_0"} : memref<48xi32> // CHECK: %[[LINK1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link1_cons_buff_1"} : memref<48xi32> -// CHECK: %[[LINK1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 6 : i32, sym_name = "link1_cons_prod_lock"} -// CHECK: %[[LINK1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "link1_cons_cons_lock"} -// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i32, sym_name = "link1_prod_lock"} -// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "link1_cons_lock"} +// CHECK: %[[LINK1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 6 : i8, sym_name = "link1_cons_prod_lock"} +// CHECK: %[[LINK1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "link1_cons_cons_lock"} +// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "link1_prod_lock"} +// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "link1_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 1, %[[TILE_2_3]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_join.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_join.mlir index f81ffcbfe..367af9e33 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_join.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_join.mlir @@ -18,28 +18,28 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[LINK5_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i32, sym_name = "link5_cons_prod_lock"} -// CHECK: %[[LINK5_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "link5_cons_cons_lock"} +// CHECK: %[[LINK5_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "link5_cons_prod_lock"} +// CHECK: %[[LINK5_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "link5_cons_cons_lock"} // CHECK: %[[LINK5_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link5_buff_0"} : memref<512xi8> // CHECK: %[[LINK5_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link5_buff_1"} : memref<512xi8> -// CHECK: %[[LINK5_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 8 : i32, sym_name = "link5_prod_lock"} -// CHECK: %[[LINK5_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "link5_cons_lock"} +// CHECK: %[[LINK5_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 8 : i8, sym_name = "link5_prod_lock"} +// CHECK: %[[LINK5_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "link5_cons_lock"} // CHECK: %[[LINK4_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link4_buff_0"} : memref<128xi8> // CHECK: %[[LINK4_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link4_buff_1"} : memref<128xi8> -// CHECK: %[[LINK4_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "link4_prod_lock"} -// CHECK: %[[LINK4_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "link4_cons_lock"} +// CHECK: %[[LINK4_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "link4_prod_lock"} +// CHECK: %[[LINK4_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "link4_cons_lock"} // CHECK: %[[LINK3_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "link3_buff_0"} : memref<128xi8> // CHECK: %[[LINK3_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "link3_buff_1"} : memref<128xi8> -// CHECK: %[[LINK3_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i32, sym_name = "link3_prod_lock"} -// CHECK: %[[LINK3_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i32, sym_name = "link3_cons_lock"} +// CHECK: %[[LINK3_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "link3_prod_lock"} +// CHECK: %[[LINK3_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "link3_cons_lock"} // CHECK: %[[LINK2_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_buff_0"} : memref<128xi8> // CHECK: %[[LINK2_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_buff_1"} : memref<128xi8> -// CHECK: %[[LINK2_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "link2_prod_lock"} -// CHECK: %[[LINK2_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "link2_cons_lock"} +// CHECK: %[[LINK2_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "link2_prod_lock"} +// CHECK: %[[LINK2_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "link2_cons_lock"} // CHECK: %[[LINK1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "link1_buff_0"} : memref<128xi8> // CHECK: %[[LINK1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "link1_buff_1"} : memref<128xi8> -// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i32, sym_name = "link1_prod_lock"} -// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "link1_cons_lock"} +// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "link1_prod_lock"} +// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "link1_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_2_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_1]], DMA : 1) // CHECK: aie.flow(%[[TILE_2_3]], DMA : 0, %[[TILE_2_1]], DMA : 2) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/loop_test.aie.mlir b/compiler/plugins/target/AMD-AIE/aie/test/loop_test.aie.mlir index 0a345376c..353951754 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/loop_test.aie.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/loop_test.aie.mlir @@ -9,8 +9,8 @@ // CHECK: %[[LOOP_OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_1"} : memref<16xi32> // CHECK: %[[LOOP_OF_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_2"} : memref<16xi32> // CHECK: %[[LOOP_OF_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_3"} : memref<16xi32> -// CHECK: %[[LOOP_OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "loop_of_prod_lock"} -// CHECK: %[[LOOP_OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "loop_of_cons_lock"} +// CHECK: %[[LOOP_OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "loop_of_prod_lock"} +// CHECK: %[[LOOP_OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "loop_of_cons_lock"} // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: index) { // CHECK: return // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/loop_test_nested.mlir b/compiler/plugins/target/AMD-AIE/aie/test/loop_test_nested.mlir index 0de536991..96bf70028 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/loop_test_nested.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/loop_test_nested.mlir @@ -7,8 +7,8 @@ // CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) // CHECK: %[[LOOP_OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_0"} : memref<16xi32> // CHECK: %[[LOOP_OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_1"} : memref<16xi32> -// CHECK: %[[LOOP_OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i32, sym_name = "loop_of_prod_lock"} -// CHECK: %[[LOOP_OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "loop_of_cons_lock"} +// CHECK: %[[LOOP_OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "loop_of_prod_lock"} +// CHECK: %[[LOOP_OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "loop_of_cons_lock"} // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<4x4xi32>, %[[ARG1:.*]]: index) { // CHECK: return // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/lower_dma.mlir b/compiler/plugins/target/AMD-AIE/aie/test/lower_dma.mlir index 6950cbd20..f661f4feb 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/lower_dma.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/lower_dma.mlir @@ -38,8 +38,8 @@ module @example0 { func.func private @llvm.aie2.put.ms(i32, i32) -> () func.func private @llvm.aie2.mcd.write.vec(vector<16xi32>, i32) -> () - // Odd AIE rows: DMem on the East - // Even AIE rows: DMem on the West + // Odd AIE rows: DMem on the EAST + // Even AIE rows: DMem on the WEST // (2, 4) (3, 4) (4, 4) (5, 4) // (2, 3) (3, 3) (4, 3) (5, 3) @@ -79,11 +79,11 @@ module @example0 { } %s33 = aie.switchbox(%t33) { - aie.connect + aie.connect } %s23 = aie.switchbox(%t23) { - aie.connect + aie.connect } %c33 = aie.core(%t33) { diff --git a/compiler/plugins/target/AMD-AIE/aie/test/matmul_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/matmul_test.mlir index 61be787f1..002aad57b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/matmul_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/matmul_test.mlir @@ -10,24 +10,24 @@ // CHECK: memref.global "public" @inA : memref<16x8xi16> // CHECK: %[[TILE_0_0:.*]] = aie.tile(2, 0) // CHECK: %[[TILE_0_2:.*]] = aie.tile(2, 2) -// CHECK: %[[OUTC_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 4) {init = 0 : i32, sym_name = "outC_cons_prod_lock"} -// CHECK: %[[OUTC_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 5) {init = 0 : i32, sym_name = "outC_cons_cons_lock"} +// CHECK: %[[OUTC_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 4) {init = 0 : i8, sym_name = "outC_cons_prod_lock"} +// CHECK: %[[OUTC_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 5) {init = 0 : i8, sym_name = "outC_cons_cons_lock"} // CHECK: %[[OUTC_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "outC_buff_0"} : memref<16x16xi16> // CHECK: %[[OUTC_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "outC_buff_1"} : memref<16x16xi16> -// CHECK: %[[OUTC_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 4) {init = 2 : i32, sym_name = "outC_prod_lock"} -// CHECK: %[[OUTC_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 5) {init = 0 : i32, sym_name = "outC_cons_lock"} +// CHECK: %[[OUTC_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 4) {init = 2 : i8, sym_name = "outC_prod_lock"} +// CHECK: %[[OUTC_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 5) {init = 0 : i8, sym_name = "outC_cons_lock"} // CHECK: %[[INB_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "inB_cons_buff_0"} : memref<8x16xi16> // CHECK: %[[INB_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "inB_cons_buff_1"} : memref<8x16xi16> -// CHECK: %[[INB_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 2) {init = 2 : i32, sym_name = "inB_cons_prod_lock"} -// CHECK: %[[INB_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 3) {init = 0 : i32, sym_name = "inB_cons_cons_lock"} -// CHECK: %[[INB_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 2) {init = 0 : i32, sym_name = "inB_prod_lock"} -// CHECK: %[[INB_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 3) {init = 0 : i32, sym_name = "inB_cons_lock"} +// CHECK: %[[INB_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 2) {init = 2 : i8, sym_name = "inB_cons_prod_lock"} +// CHECK: %[[INB_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 3) {init = 0 : i8, sym_name = "inB_cons_cons_lock"} +// CHECK: %[[INB_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 2) {init = 0 : i8, sym_name = "inB_prod_lock"} +// CHECK: %[[INB_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 3) {init = 0 : i8, sym_name = "inB_cons_lock"} // CHECK: %[[INA_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "inA_cons_buff_0"} : memref<16x8xi16> // CHECK: %[[INA_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "inA_cons_buff_1"} : memref<16x8xi16> -// CHECK: %[[INA_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 0) {init = 2 : i32, sym_name = "inA_cons_prod_lock"} -// CHECK: %[[INA_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 1) {init = 0 : i32, sym_name = "inA_cons_cons_lock"} -// CHECK: %[[INA_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 0) {init = 0 : i32, sym_name = "inA_prod_lock"} -// CHECK: %[[INA_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 1) {init = 0 : i32, sym_name = "inA_cons_lock"} +// CHECK: %[[INA_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 0) {init = 2 : i8, sym_name = "inA_cons_prod_lock"} +// CHECK: %[[INA_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 1) {init = 0 : i8, sym_name = "inA_cons_cons_lock"} +// CHECK: %[[INA_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 0) {init = 0 : i8, sym_name = "inA_prod_lock"} +// CHECK: %[[INA_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 1) {init = 0 : i8, sym_name = "inA_cons_lock"} // CHECK: aie.flow(%[[TILE_0_0]], DMA : 0, %[[TILE_0_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_0_0]], DMA : 1, %[[TILE_0_2]], DMA : 1) // CHECK: aie.flow(%[[TILE_0_2]], DMA : 0, %[[TILE_0_0]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/memTile_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/memTile_test.mlir index c97a59633..26a8a9936 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/memTile_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/memTile_test.mlir @@ -8,12 +8,12 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[OF_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of_cons_prod_lock"} -// CHECK: %[[OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of_cons_cons_lock"} +// CHECK: %[[OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of_cons_prod_lock"} +// CHECK: %[[OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of_cons_cons_lock"} // CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "of_buff_0"} : memref<16xi32> // CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "of_buff_1"} : memref<16xi32> -// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i32, sym_name = "of_prod_lock"} -// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "of_cons_lock"} +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i8, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "of_cons_lock"} // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { // CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_base_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_base_AIE2.mlir index 612b452de..5950e912e 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_base_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_base_AIE2.mlir @@ -11,24 +11,24 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<256xi32> -// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} // CHECK: %[[OF1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_0"} : memref<256xi32> // CHECK: %[[OF1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_1"} : memref<256xi32> -// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i32, sym_name = "of1_prod_lock"} -// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "of1_cons_lock"} +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i8, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i8, sym_name = "of1_cons_lock"} // CHECK: %[[OF0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_cons_buff_1"} : memref<256xi32> // CHECK: %[[OF0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_cons_buff_2"} : memref<256xi32> // CHECK: %[[OF0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_cons_buff_3"} : memref<256xi32> -// CHECK: %[[OF0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 4 : i32, sym_name = "of0_cons_prod_lock"} -// CHECK: %[[OF0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i32, sym_name = "of0_cons_cons_lock"} +// CHECK: %[[OF0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 4 : i8, sym_name = "of0_cons_prod_lock"} +// CHECK: %[[OF0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i8, sym_name = "of0_cons_cons_lock"} // CHECK: %[[OF0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_0"} : memref<256xi32> // CHECK: %[[OF0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_1"} : memref<256xi32> // CHECK: %[[OF0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_2"} : memref<256xi32> // CHECK: %[[OF0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_3"} : memref<256xi32> -// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "of0_prod_lock"} -// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of0_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_1_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_2]], DMA : 1, %[[TILE_3_3]], DMA : 0) // CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { diff --git a/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_distribute_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_distribute_AIE2.mlir index cf94a66b9..2127fac4a 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_distribute_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_distribute_AIE2.mlir @@ -14,18 +14,18 @@ // CHECK: %[[TILE_2_3:.*]] = aie.tile(3, 3) // CHECK: %[[OF2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of2_cons_buff_0"} : memref<128xi32> // CHECK: %[[OF2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of2_cons_buff_1"} : memref<128xi32> -// CHECK: %[[OF2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i32, sym_name = "of2_cons_prod_lock"} -// CHECK: %[[OF2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i32, sym_name = "of2_cons_cons_lock"} +// CHECK: %[[OF2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "of2_cons_prod_lock"} +// CHECK: %[[OF2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "of2_cons_cons_lock"} // CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of1_cons_buff_0"} : memref<128xi32> // CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of1_cons_buff_1"} : memref<128xi32> -// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} // CHECK: %[[OF0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_1]]) {sym_name = "of0_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_1]]) {sym_name = "of0_cons_buff_1"} : memref<256xi32> -// CHECK: %[[OF0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_1]], 0) {init = 4 : i32, sym_name = "of0_cons_prod_lock"} -// CHECK: %[[OF0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_1]], 1) {init = 0 : i32, sym_name = "of0_cons_cons_lock"} -// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_0]], 0) {init = 0 : i32, sym_name = "of0_prod_lock"} -// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_0]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} +// CHECK: %[[OF0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_1]], 0) {init = 4 : i8, sym_name = "of0_cons_prod_lock"} +// CHECK: %[[OF0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_1]], 1) {init = 0 : i8, sym_name = "of0_cons_cons_lock"} +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_0]], 0) {init = 0 : i8, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_0]], 1) {init = 0 : i8, sym_name = "of0_cons_lock"} // CHECK: aie.flow(%[[TILE_1_0]], DMA : 0, %[[TILE_1_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_1]], DMA : 1, %[[TILE_2_3]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_multiple_consumers_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_multiple_consumers_AIE2.mlir index d51f75ca2..1aed3daf7 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_multiple_consumers_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_multiple_consumers_AIE2.mlir @@ -16,38 +16,38 @@ // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[OF3_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of3_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF3_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of3_cons_buff_1"} : memref<256xi32> -// CHECK: %[[OF3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i32, sym_name = "of3_cons_prod_lock"} -// CHECK: %[[OF3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i32, sym_name = "of3_cons_cons_lock"} +// CHECK: %[[OF3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "of3_cons_prod_lock"} +// CHECK: %[[OF3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "of3_cons_cons_lock"} // CHECK: %[[OF3_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of3_buff_0"} : memref<256xi32> // CHECK: %[[OF3_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of3_buff_1"} : memref<256xi32> -// CHECK: %[[OF3_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of3_prod_lock"} -// CHECK: %[[OF3_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of3_cons_lock"} +// CHECK: %[[OF3_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of3_prod_lock"} +// CHECK: %[[OF3_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of3_cons_lock"} // CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<256xi32> -// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 2) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 3) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 2) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 3) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} // CHECK: %[[OF1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_0"} : memref<256xi32> // CHECK: %[[OF1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_1"} : memref<256xi32> -// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i32, sym_name = "of1_prod_lock"} -// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "of1_cons_lock"} +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i8, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i8, sym_name = "of1_cons_lock"} // CHECK: %[[OF0_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_0_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF0_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_0_cons_buff_1"} : memref<256xi32> // CHECK: %[[OF0_0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_0_cons_buff_2"} : memref<256xi32> // CHECK: %[[OF0_0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_0_cons_buff_3"} : memref<256xi32> -// CHECK: %[[OF0_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 4 : i32, sym_name = "of0_0_cons_prod_lock"} -// CHECK: %[[OF0_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i32, sym_name = "of0_0_cons_cons_lock"} +// CHECK: %[[OF0_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 4 : i8, sym_name = "of0_0_cons_prod_lock"} +// CHECK: %[[OF0_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i8, sym_name = "of0_0_cons_cons_lock"} // CHECK: %[[OF0_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of0_1_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF0_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of0_1_cons_buff_1"} : memref<256xi32> // CHECK: %[[OF0_1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of0_1_cons_buff_2"} : memref<256xi32> // CHECK: %[[OF0_1_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of0_1_cons_buff_3"} : memref<256xi32> -// CHECK: %[[OF0_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 4 : i32, sym_name = "of0_1_cons_prod_lock"} -// CHECK: %[[OF0_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "of0_1_cons_cons_lock"} +// CHECK: %[[OF0_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 4 : i8, sym_name = "of0_1_cons_prod_lock"} +// CHECK: %[[OF0_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "of0_1_cons_cons_lock"} // CHECK: %[[OF0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_0"} : memref<256xi32> // CHECK: %[[OF0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_1"} : memref<256xi32> // CHECK: %[[OF0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_2"} : memref<256xi32> // CHECK: %[[OF0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_3"} : memref<256xi32> -// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "of0_prod_lock"} -// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of0_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_1_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_2]], DMA : 1, %[[TILE_3_3]], DMA : 1) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/nested_loop_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/nested_loop_test.mlir index 06c8682f3..2d93ce41d 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/nested_loop_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/nested_loop_test.mlir @@ -16,38 +16,38 @@ // CHECK: %[[IN8_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in8_cons_buff_1"} : memref<32x32xi32, 1> // CHECK: %[[IN8_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in8_cons_buff_2"} : memref<32x32xi32, 1> // CHECK: %[[IN8_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in8_cons_buff_3"} : memref<32x32xi32, 1> -// CHECK: %[[IN8_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 4) {init = 4 : i32, sym_name = "in8_cons_prod_lock"} -// CHECK: %[[IN8_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 5) {init = 0 : i32, sym_name = "in8_cons_cons_lock"} +// CHECK: %[[IN8_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 4) {init = 4 : i8, sym_name = "in8_cons_prod_lock"} +// CHECK: %[[IN8_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 5) {init = 0 : i8, sym_name = "in8_cons_cons_lock"} // CHECK: %[[IN8_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in8_buff_0"} : memref<32x32xi32, 1> // CHECK: %[[IN8_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in8_buff_1"} : memref<32x32xi32, 1> -// CHECK: %[[IN8_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 4) {init = 2 : i32, sym_name = "in8_prod_lock"} -// CHECK: %[[IN8_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 5) {init = 0 : i32, sym_name = "in8_cons_lock"} +// CHECK: %[[IN8_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 4) {init = 2 : i8, sym_name = "in8_prod_lock"} +// CHECK: %[[IN8_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 5) {init = 0 : i8, sym_name = "in8_cons_lock"} // CHECK: %[[IN7_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in7_cons_buff_0"} : memref<64x32xi32, 1> // CHECK: %[[IN7_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in7_cons_buff_1"} : memref<64x32xi32, 1> -// CHECK: %[[IN7_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i32, sym_name = "in7_cons_prod_lock"} -// CHECK: %[[IN7_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "in7_cons_cons_lock"} +// CHECK: %[[IN7_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i8, sym_name = "in7_cons_prod_lock"} +// CHECK: %[[IN7_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i8, sym_name = "in7_cons_cons_lock"} // CHECK: %[[IN7_BUFF_0:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in7_buff_0"} : memref<64x32xi32, 1> // CHECK: %[[IN7_BUFF_1:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in7_buff_1"} : memref<64x32xi32, 1> // CHECK: %[[IN7_BUFF_2:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in7_buff_2"} : memref<64x32xi32, 1> // CHECK: %[[IN7_BUFF_3:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in7_buff_3"} : memref<64x32xi32, 1> -// CHECK: %[[IN7_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 2) {init = 4 : i32, sym_name = "in7_prod_lock"} -// CHECK: %[[IN7_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 3) {init = 0 : i32, sym_name = "in7_cons_lock"} +// CHECK: %[[IN7_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 2) {init = 4 : i8, sym_name = "in7_prod_lock"} +// CHECK: %[[IN7_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 3) {init = 0 : i8, sym_name = "in7_cons_lock"} // CHECK: %[[IN2_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "in2_0_cons_buff_0"} : memref<32x64xi32, 1> // CHECK: %[[IN2_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "in2_0_cons_buff_1"} : memref<32x64xi32, 1> // CHECK: %[[IN2_0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "in2_0_cons_buff_2"} : memref<32x64xi32, 1> // CHECK: %[[IN2_0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "in2_0_cons_buff_3"} : memref<32x64xi32, 1> -// CHECK: %[[IN2_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 0) {init = 4 : i32, sym_name = "in2_0_cons_prod_lock"} -// CHECK: %[[IN2_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 1) {init = 0 : i32, sym_name = "in2_0_cons_cons_lock"} +// CHECK: %[[IN2_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 0) {init = 4 : i8, sym_name = "in2_0_cons_prod_lock"} +// CHECK: %[[IN2_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 1) {init = 0 : i8, sym_name = "in2_0_cons_cons_lock"} // CHECK: %[[IN2_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in2_1_cons_buff_0"} : memref<32x64xi32, 1> // CHECK: %[[IN2_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in2_1_cons_buff_1"} : memref<32x64xi32, 1> -// CHECK: %[[IN2_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i32, sym_name = "in2_1_cons_prod_lock"} -// CHECK: %[[IN2_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "in2_1_cons_cons_lock"} +// CHECK: %[[IN2_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "in2_1_cons_prod_lock"} +// CHECK: %[[IN2_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "in2_1_cons_cons_lock"} // CHECK: %[[IN2_BUFF_0:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in2_buff_0"} : memref<32x64xi32, 1> // CHECK: %[[IN2_BUFF_1:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in2_buff_1"} : memref<32x64xi32, 1> // CHECK: %[[IN2_BUFF_2:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in2_buff_2"} : memref<32x64xi32, 1> // CHECK: %[[IN2_BUFF_3:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in2_buff_3"} : memref<32x64xi32, 1> -// CHECK: %[[IN2_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 0) {init = 4 : i32, sym_name = "in2_prod_lock"} -// CHECK: %[[IN2_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 1) {init = 0 : i32, sym_name = "in2_cons_lock"} +// CHECK: %[[IN2_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 0) {init = 4 : i8, sym_name = "in2_prod_lock"} +// CHECK: %[[IN2_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 1) {init = 0 : i8, sym_name = "in2_cons_lock"} // CHECK: aie.flow(%[[TILE_0_1]], DMA : 0, %[[TILE_1_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_0_1]], DMA : 0, %[[TILE_0_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_0_1]], DMA : 1, %[[TILE_1_2]], DMA : 1) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_1.mlir index a308d057f..88b3b5065 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_1.mlir @@ -8,12 +8,12 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OBJFIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> // CHECK: %[[OBJFIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "objfifo_cons_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "objfifo_cons_cons_lock"} +// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "objfifo_cons_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "objfifo_cons_cons_lock"} // CHECK: %[[OBJFIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> // CHECK: %[[OBJFIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> -// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i32, sym_name = "objfifo_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "objfifo_cons_lock"} +// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "objfifo_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "objfifo_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return diff --git a/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_2.mlir index 0ed6a3f26..620c16cb6 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_2.mlir @@ -10,12 +10,12 @@ // CHECK: %[[OBJFIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> // CHECK: %[[OBJFIFO_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_2"} : memref<16xi32> // CHECK: %[[OBJFIFO_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_3"} : memref<16xi32> -// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 4 : i32, sym_name = "objfifo_cons_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "objfifo_cons_cons_lock"} +// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 4 : i8, sym_name = "objfifo_cons_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "objfifo_cons_cons_lock"} // CHECK: %[[OBJFIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> // CHECK: %[[OBJFIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> -// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i32, sym_name = "objfifo_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "objfifo_cons_lock"} +// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "objfifo_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "objfifo_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return diff --git a/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_AIE2.mlir index 53a47fc9f..c3be314b8 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_AIE2.mlir @@ -8,12 +8,12 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OF_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "of_cons_prod_lock"} -// CHECK: %[[OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "of_cons_cons_lock"} +// CHECK: %[[OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "of_cons_prod_lock"} +// CHECK: %[[OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "of_cons_cons_lock"} // CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> // CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_1"} : memref<16xi32> -// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i32, sym_name = "of_prod_lock"} -// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of_cons_lock"} +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return diff --git a/compiler/plugins/target/AMD-AIE/aie/test/packet_routing_keep_pkt_header.mlir b/compiler/plugins/target/AMD-AIE/aie/test/packet_routing_keep_pkt_header.mlir index 7459dba82..f734d40da 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/packet_routing_keep_pkt_header.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/packet_routing_keep_pkt_header.mlir @@ -5,14 +5,14 @@ // CHECK: %[[VAL_1:.*]] = aie.switchbox(%[[VAL_0]]) { // CHECK: %[[VAL_2:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_3:.*]] = aie.masterset(DMA : 1, %[[VAL_2]]) -// CHECK: aie.packet_rules(North : 0) { +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(31, 1, %[[VAL_2]]) // CHECK: } // CHECK: } // CHECK: %[[VAL_4:.*]] = aie.tile(6, 3) // CHECK: %[[VAL_5:.*]] = aie.switchbox(%[[VAL_4]]) { // CHECK: %[[VAL_6:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_7:.*]] = aie.masterset(South : 0, %[[VAL_6]]) +// CHECK: %[[VAL_7:.*]] = aie.masterset(SOUTH : 0, %[[VAL_6]]) // CHECK: aie.packet_rules(DMA : 0) { // CHECK: aie.rule(31, 1, %[[VAL_6]]) // CHECK: } @@ -21,14 +21,14 @@ // CHECK: %[[VAL_9:.*]] = aie.switchbox(%[[VAL_8]]) { // CHECK: %[[VAL_10:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_11:.*]] = aie.masterset(DMA : 1, %[[VAL_10]]) {keep_pkt_header = "true"} -// CHECK: aie.packet_rules(North : 0) { +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(31, 2, %[[VAL_10]]) // CHECK: } // CHECK: } // CHECK: %[[VAL_12:.*]] = aie.tile(7, 3) // CHECK: %[[VAL_13:.*]] = aie.switchbox(%[[VAL_12]]) { // CHECK: %[[VAL_14:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_15:.*]] = aie.masterset(South : 0, %[[VAL_14]]) +// CHECK: %[[VAL_15:.*]] = aie.masterset(SOUTH : 0, %[[VAL_14]]) // CHECK: aie.packet_rules(DMA : 0) { // CHECK: aie.rule(31, 2, %[[VAL_14]]) // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/register_external_buffers_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/register_external_buffers_test.mlir index f94378689..5d320a955 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/register_external_buffers_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/register_external_buffers_test.mlir @@ -9,10 +9,10 @@ // CHECK: %[[EXT_OF_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "ext_of_cons_buff_0"} : memref<16xi32> // CHECK: %[[EXT_OF_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "ext_of_cons_buff_1"} : memref<16xi32> // CHECK: %[[EXT_OF_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "ext_of_cons_buff_2"} : memref<16xi32> -// CHECK: %[[EXT_OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 0) {init = 3 : i32, sym_name = "ext_of_cons_prod_lock"} -// CHECK: %[[EXT_OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 1) {init = 0 : i32, sym_name = "ext_of_cons_cons_lock"} -// CHECK: %[[EXT_OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_0]], 0) {init = 0 : i32, sym_name = "ext_of_prod_lock"} -// CHECK: %[[EXT_OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_0]], 1) {init = 0 : i32, sym_name = "ext_of_cons_lock"} +// CHECK: %[[EXT_OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 0) {init = 3 : i8, sym_name = "ext_of_cons_prod_lock"} +// CHECK: %[[EXT_OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 1) {init = 0 : i8, sym_name = "ext_of_cons_cons_lock"} +// CHECK: %[[EXT_OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_0]], 0) {init = 0 : i8, sym_name = "ext_of_prod_lock"} +// CHECK: %[[EXT_OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_0]], 1) {init = 0 : i8, sym_name = "ext_of_cons_lock"} // CHECK: aie.flow(%[[TILE_3_0]], DMA : 0, %[[TILE_3_2]], DMA : 0) // CHECK: %[[EXT_BUFFER_IN:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: memref<16xi32>) { diff --git a/compiler/plugins/target/AMD-AIE/aie/test/same_core_producer_consumer_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/same_core_producer_consumer_test.mlir index e8e9e157b..a68be25a4 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/same_core_producer_consumer_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/same_core_producer_consumer_test.mlir @@ -7,8 +7,8 @@ // CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> // CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_1"} : memref<16xi32> // CHECK: %[[OF_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_2"} : memref<16xi32> -// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 3 : i32, sym_name = "of_prod_lock"} -// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of_cons_lock"} +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 3 : i8, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of_cons_lock"} // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/shimRow_mem_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/shimRow_mem_test.mlir index 0f74f8480..57c19533b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/shimRow_mem_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/shimRow_mem_test.mlir @@ -9,10 +9,10 @@ // CHECK: %[[OBJFIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> // CHECK: %[[OBJFIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> // CHECK: %[[OBJFIFO_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "objfifo_cons_buff_2"} : memref<16xi32> -// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 0) {init = 3 : i32, sym_name = "objfifo_cons_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 1) {init = 0 : i32, sym_name = "objfifo_cons_cons_lock"} -// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_0]], 0) {init = 0 : i32, sym_name = "objfifo_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_0]], 1) {init = 0 : i32, sym_name = "objfifo_cons_lock"} +// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 0) {init = 3 : i8, sym_name = "objfifo_cons_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 1) {init = 0 : i8, sym_name = "objfifo_cons_cons_lock"} +// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_0]], 0) {init = 0 : i8, sym_name = "objfifo_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_0]], 1) {init = 0 : i8, sym_name = "objfifo_cons_lock"} // CHECK: aie.flow(%[[TILE_3_0]], DMA : 0, %[[TILE_3_2]], DMA : 0) // CHECK: %[[EXT_BUFFER_IN:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: memref<16xi32>) { diff --git a/compiler/plugins/target/AMD-AIE/aie/test/shim_AIE2_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/shim_AIE2_test.mlir index 72840fd2c..c46d46826 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/shim_AIE2_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/shim_AIE2_test.mlir @@ -8,18 +8,18 @@ // CHECK: memref.global "public" @of_in : memref<16xi32> // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[OF_OUT_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 2) {init = 0 : i32, sym_name = "of_out_cons_prod_lock"} -// CHECK: %[[OF_OUT_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 3) {init = 0 : i32, sym_name = "of_out_cons_cons_lock"} +// CHECK: %[[OF_OUT_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 2) {init = 0 : i8, sym_name = "of_out_cons_prod_lock"} +// CHECK: %[[OF_OUT_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 3) {init = 0 : i8, sym_name = "of_out_cons_cons_lock"} // CHECK: %[[OF_OUT_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_buff_0"} : memref<16xi32> // CHECK: %[[OF_OUT_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_buff_1"} : memref<16xi32> -// CHECK: %[[OF_OUT_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i32, sym_name = "of_out_prod_lock"} -// CHECK: %[[OF_OUT_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i32, sym_name = "of_out_cons_lock"} +// CHECK: %[[OF_OUT_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i8, sym_name = "of_out_prod_lock"} +// CHECK: %[[OF_OUT_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i8, sym_name = "of_out_cons_lock"} // CHECK: %[[OF_IN_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF_IN_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF_IN_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of_in_cons_prod_lock"} -// CHECK: %[[OF_IN_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of_in_cons_cons_lock"} -// CHECK: %[[OF_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i32, sym_name = "of_in_prod_lock"} -// CHECK: %[[OF_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "of_in_cons_lock"} +// CHECK: %[[OF_IN_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of_in_cons_prod_lock"} +// CHECK: %[[OF_IN_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of_in_cons_cons_lock"} +// CHECK: %[[OF_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "of_in_prod_lock"} +// CHECK: %[[OF_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "of_in_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_0]], DMA : 0) // CHECK: %[[EXT_BUFFER_IN:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/test/shim_broadcast_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/shim_broadcast_test.mlir index db50c7895..2738c8655 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/shim_broadcast_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/shim_broadcast_test.mlir @@ -12,18 +12,18 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OF_IN_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF_IN_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of_in_0_cons_prod_lock"} -// CHECK: %[[OF_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of_in_0_cons_cons_lock"} +// CHECK: %[[OF_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of_in_0_cons_prod_lock"} +// CHECK: %[[OF_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of_in_0_cons_cons_lock"} // CHECK: %[[OF_IN_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF_IN_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i32, sym_name = "of_in_1_cons_prod_lock"} -// CHECK: %[[OF_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i32, sym_name = "of_in_1_cons_cons_lock"} +// CHECK: %[[OF_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "of_in_1_cons_prod_lock"} +// CHECK: %[[OF_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "of_in_1_cons_cons_lock"} // CHECK: %[[OF_IN_2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of_in_2_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF_IN_2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of_in_2_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF_IN_2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "of_in_2_cons_prod_lock"} -// CHECK: %[[OF_IN_2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "of_in_2_cons_cons_lock"} -// CHECK: %[[OF_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i32, sym_name = "of_in_prod_lock"} -// CHECK: %[[OF_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "of_in_cons_lock"} +// CHECK: %[[OF_IN_2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "of_in_2_cons_prod_lock"} +// CHECK: %[[OF_IN_2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "of_in_2_cons_cons_lock"} +// CHECK: %[[OF_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "of_in_prod_lock"} +// CHECK: %[[OF_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "of_in_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_2]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/subview_test_1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/subview_test_1.mlir index 7e9c2a9e1..fc3db0d5b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/subview_test_1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/subview_test_1.mlir @@ -9,8 +9,8 @@ // CHECK: %[[OBJFIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> // CHECK: %[[OBJFIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_2"} : memref<16xi32> // CHECK: %[[OBJFIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_3"} : memref<16xi32> -// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "objfifo_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "objfifo_cons_lock"} +// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "objfifo_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "objfifo_cons_lock"} // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/subview_test_2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/subview_test_2.mlir index 14aa671df..8054e3ada 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/subview_test_2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/subview_test_2.mlir @@ -9,14 +9,14 @@ // CHECK: %[[OF2_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of2_buff_0"} : memref<16xi32> // CHECK: %[[OF2_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of2_buff_1"} : memref<16xi32> // CHECK: %[[OF2_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of2_buff_2"} : memref<16xi32> -// CHECK: %[[OF2_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 3 : i32, sym_name = "of2_prod_lock"} -// CHECK: %[[OF2_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "of2_cons_lock"} +// CHECK: %[[OF2_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 3 : i8, sym_name = "of2_prod_lock"} +// CHECK: %[[OF2_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i8, sym_name = "of2_cons_lock"} // CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> // CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_1"} : memref<16xi32> // CHECK: %[[OF_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_2"} : memref<16xi32> // CHECK: %[[OF_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_3"} : memref<16xi32> -// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "of_prod_lock"} -// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of_cons_lock"} +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of_cons_lock"} // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/subview_test_3.mlir b/compiler/plugins/target/AMD-AIE/aie/test/subview_test_3.mlir index 878282247..ced67e903 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/subview_test_3.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/subview_test_3.mlir @@ -9,14 +9,14 @@ // CHECK: %[[OF2_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of2_buff_0"} : memref<16xi32> // CHECK: %[[OF2_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of2_buff_1"} : memref<16xi32> // CHECK: %[[OF2_BUFF_2:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of2_buff_2"} : memref<16xi32> -// CHECK: %[[OF2_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 3 : i32, sym_name = "of2_prod_lock"} -// CHECK: %[[OF2_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i32, sym_name = "of2_cons_lock"} +// CHECK: %[[OF2_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 3 : i8, sym_name = "of2_prod_lock"} +// CHECK: %[[OF2_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i8, sym_name = "of2_cons_lock"} // CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> // CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_1"} : memref<16xi32> // CHECK: %[[OF_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_2"} : memref<16xi32> // CHECK: %[[OF_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_3"} : memref<16xi32> -// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "of_prod_lock"} -// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of_cons_lock"} +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of_cons_lock"} // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } @@ -55,7 +55,7 @@ // CHECK: } // CHECK: } -module @multiCoreMixedFifo { +module @multiCOREMixedFifo { aie.device(npu1_4col) { %tile12 = aie.tile(1, 2) %tile13 = aie.tile(1, 3) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/test_congestion0.mlir b/compiler/plugins/target/AMD-AIE/aie/test/test_congestion0.mlir index cd426e693..c59e83319 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/test_congestion0.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/test_congestion0.mlir @@ -13,7 +13,7 @@ // CHECK: %[[VAL_7:.*]] = aie.masterset(DMA : 2, %[[VAL_3]]) // CHECK: %[[VAL_8:.*]] = aie.masterset(DMA : 3, %[[VAL_4]]) // CHECK: %[[VAL_9:.*]] = aie.masterset(DMA : 4, %[[VAL_1]]) -// CHECK: aie.packet_rules(North : 0) { +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(31, 0, %[[VAL_0]]) // CHECK: aie.rule(31, 1, %[[VAL_2]]) // CHECK: aie.rule(31, 2, %[[VAL_3]]) @@ -24,43 +24,43 @@ // CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) // CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { // CHECK: %[[VAL_10:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_11:.*]] = aie.masterset(South : 0, %[[VAL_10]]) +// CHECK: %[[VAL_11:.*]] = aie.masterset(SOUTH : 0, %[[VAL_10]]) // CHECK: aie.packet_rules(DMA : 0) { // CHECK: aie.rule(31, 0, %[[VAL_10]]) // CHECK: } // CHECK: aie.packet_rules(DMA : 1) { // CHECK: aie.rule(31, 4, %[[VAL_10]]) // CHECK: } -// CHECK: aie.packet_rules(North : 0) { +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(28, 0, %[[VAL_10]]) // CHECK: } // CHECK: } // CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) // CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { // CHECK: %[[VAL_12:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_13:.*]] = aie.masterset(South : 0, %[[VAL_12]]) +// CHECK: %[[VAL_13:.*]] = aie.masterset(SOUTH : 0, %[[VAL_12]]) // CHECK: aie.packet_rules(DMA : 0) { // CHECK: aie.rule(31, 1, %[[VAL_12]]) // CHECK: } -// CHECK: aie.packet_rules(North : 0) { +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(30, 2, %[[VAL_12]]) // CHECK: } // CHECK: } // CHECK: %[[TILE_0_4:.*]] = aie.tile(0, 4) // CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { // CHECK: %[[VAL_14:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_15:.*]] = aie.masterset(South : 0, %[[VAL_14]]) +// CHECK: %[[VAL_15:.*]] = aie.masterset(SOUTH : 0, %[[VAL_14]]) // CHECK: aie.packet_rules(DMA : 0) { // CHECK: aie.rule(31, 2, %[[VAL_14]]) // CHECK: } -// CHECK: aie.packet_rules(North : 0) { +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(31, 3, %[[VAL_14]]) // CHECK: } // CHECK: } // CHECK: %[[TILE_0_5:.*]] = aie.tile(0, 5) // CHECK: %[[SWITCHBOX_0_5:.*]] = aie.switchbox(%[[TILE_0_5]]) { // CHECK: %[[VAL_16:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_17:.*]] = aie.masterset(South : 0, %[[VAL_16]]) +// CHECK: %[[VAL_17:.*]] = aie.masterset(SOUTH : 0, %[[VAL_16]]) // CHECK: aie.packet_rules(DMA : 0) { // CHECK: aie.rule(31, 3, %[[VAL_16]]) // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/test_congestion1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/test_congestion1.mlir index cd00f755c..b8673460e 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/test_congestion1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/test_congestion1.mlir @@ -7,50 +7,50 @@ // CHECK: %[[T04:.*]] = aie.tile(0, 4) // CHECK: %[[T05:.*]] = aie.tile(0, 5) // CHECK: %{{.*}} = aie.switchbox(%[[T01]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: %0 = aie.amsel<0> (0) // CHECK: %1 = aie.masterset(DMA : 4, %0) -// CHECK: aie.packet_rules(South : 0) { +// CHECK: aie.packet_rules(SOUTH : 0) { // CHECK: aie.rule(31, 0, %0) // CHECK: } // CHECK: } // CHECK: %{{.*}} = aie.switchbox(%[[T02]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %{{.*}} = aie.switchbox(%[[T03]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %{{.*}} = aie.switchbox(%[[T04]]) { -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %{{.*}} = aie.switchbox(%[[T05]]) { -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: %0 = aie.amsel<0> (0) -// CHECK: %1 = aie.masterset(East : 0, %0) +// CHECK: %1 = aie.masterset(EAST : 0, %0) // CHECK: aie.packet_rules(DMA : 1) { // CHECK: aie.rule(31, 0, %0) // CHECK: } // CHECK: } // CHECK: %{{.*}} = aie.switchbox(%[[T00]]) { -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: %0 = aie.amsel<0> (0) -// CHECK: %1 = aie.masterset(North : 0, %0) -// CHECK: aie.packet_rules(East : 0) { +// CHECK: %1 = aie.masterset(NORTH : 0, %0) +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(31, 0, %0) // CHECK: } // CHECK: } // CHECK: %{{.*}} = aie.shim_mux(%[[T00]]) { -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } module { aie.device(npu1_2col) { diff --git a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows0.mlir b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows0.mlir index bb95b4136..29a4fc09f 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows0.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows0.mlir @@ -9,9 +9,9 @@ module @test_create_packet_flows0 { // The actual indices used for the amsel arguments is unimportant. // CHECK: %[[VAL_6:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_7:.*]] = aie.amsel<0> (1) -// CHECK: %[[VAL_4:.*]] = aie.masterset(Core : 0, %[[VAL_2:.*]]) -// CHECK: %[[VAL_5:.*]] = aie.masterset(Core : 1, %[[VAL_3:.*]]) -// CHECK: aie.packet_rules(West : 0) { +// CHECK: %[[VAL_4:.*]] = aie.masterset(CORE : 0, %[[VAL_2:.*]]) +// CHECK: %[[VAL_5:.*]] = aie.masterset(CORE : 1, %[[VAL_3:.*]]) +// CHECK: aie.packet_rules(WEST : 0) { // CHECK-DAG: aie.rule(31, 0, %[[VAL_2]]) // CHECK-DAG: aie.rule(31, 1, %[[VAL_3]]) // CHECK: } @@ -20,13 +20,13 @@ module @test_create_packet_flows0 { %t11 = aie.tile(1, 1) aie.packet_flow(0x0) { - aie.packet_source<%t11, West : 0> - aie.packet_dest<%t11, Core : 0> + aie.packet_source<%t11, WEST : 0> + aie.packet_dest<%t11, CORE : 0> } aie.packet_flow(0x1) { - aie.packet_source<%t11, West : 0> - aie.packet_dest<%t11, Core : 1> + aie.packet_source<%t11, WEST : 0> + aie.packet_dest<%t11, CORE : 1> } } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows1.mlir index c21428bcb..33b9f5542 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows1.mlir @@ -4,11 +4,11 @@ // CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) // CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { // CHECK: %[[VAL_0:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_1:.*]] = aie.masterset(Core : 0, %[[VAL_0]]) -// CHECK: aie.packet_rules(West : 0) { +// CHECK: %[[VAL_1:.*]] = aie.masterset(CORE : 0, %[[VAL_0]]) +// CHECK: aie.packet_rules(WEST : 0) { // CHECK: aie.rule(31, 0, %[[VAL_0]]) // CHECK: } -// CHECK: aie.packet_rules(West : 1) { +// CHECK: aie.packet_rules(WEST : 1) { // CHECK: aie.rule(31, 1, %[[VAL_0]]) // CHECK: } // CHECK: } @@ -19,13 +19,13 @@ module @test_create_packet_flows1 { %t11 = aie.tile(1, 1) aie.packet_flow(0x0) { - aie.packet_source<%t11, West : 0> - aie.packet_dest<%t11, Core : 0> + aie.packet_source<%t11, WEST : 0> + aie.packet_dest<%t11, CORE : 0> } aie.packet_flow(0x1) { - aie.packet_source<%t11, West : 1> - aie.packet_dest<%t11, Core : 0> + aie.packet_source<%t11, WEST : 1> + aie.packet_dest<%t11, CORE : 0> } } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows2.mlir index 0cd50fe61..7029e443c 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows2.mlir @@ -5,21 +5,21 @@ // CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { // CHECK: %[[VAL_0:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_1:.*]] = aie.amsel<0> (1) -// CHECK: %[[VAL_2:.*]] = aie.masterset(Core : 0, %[[VAL_0]]) -// CHECK: %[[VAL_3:.*]] = aie.masterset(Core : 1, %[[VAL_0]], %[[VAL_1]]) -// CHECK: aie.packet_rules(West : 0) { +// CHECK: %[[VAL_2:.*]] = aie.masterset(CORE : 0, %[[VAL_0]]) +// CHECK: %[[VAL_3:.*]] = aie.masterset(CORE : 1, %[[VAL_0]], %[[VAL_1]]) +// CHECK: aie.packet_rules(WEST : 0) { // CHECK-DAG: aie.rule(31, 0, %[[VAL_0]]) // CHECK-DAG: aie.rule(31, 1, %[[VAL_1]]) // CHECK: } // CHECK: } // CHECK: aie.packet_flow(0) { -// CHECK: aie.packet_source<%[[TILE_1_1]], West : 0> -// CHECK: aie.packet_dest<%[[TILE_1_1]], Core : 0> -// CHECK: aie.packet_dest<%[[TILE_1_1]], Core : 1> +// CHECK: aie.packet_source<%[[TILE_1_1]], WEST : 0> +// CHECK: aie.packet_dest<%[[TILE_1_1]], CORE : 0> +// CHECK: aie.packet_dest<%[[TILE_1_1]], CORE : 1> // CHECK: } // CHECK: aie.packet_flow(1) { -// CHECK: aie.packet_source<%[[TILE_1_1]], West : 0> -// CHECK: aie.packet_dest<%[[TILE_1_1]], Core : 1> +// CHECK: aie.packet_source<%[[TILE_1_1]], WEST : 0> +// CHECK: aie.packet_dest<%[[TILE_1_1]], CORE : 1> // CHECK: } // CHECK: } @@ -28,14 +28,14 @@ module @test_create_packet_flows2 { %t11 = aie.tile(1, 1) aie.packet_flow(0x0) { - aie.packet_source<%t11, West : 0> - aie.packet_dest<%t11, Core : 0> - aie.packet_dest<%t11, Core : 1> + aie.packet_source<%t11, WEST : 0> + aie.packet_dest<%t11, CORE : 0> + aie.packet_dest<%t11, CORE : 1> } aie.packet_flow(0x1) { - aie.packet_source<%t11, West : 0> - aie.packet_dest<%t11, Core : 1> + aie.packet_source<%t11, WEST : 0> + aie.packet_dest<%t11, CORE : 1> } } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows3.mlir b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows3.mlir index b06dc03a1..77deb30fa 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows3.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows3.mlir @@ -5,23 +5,23 @@ // CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { // CHECK: %[[VAL_0:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_1:.*]] = aie.amsel<0> (1) -// CHECK: %[[VAL_2:.*]] = aie.masterset(Core : 0, %[[VAL_0]]) -// CHECK: %[[VAL_3:.*]] = aie.masterset(Core : 1, %[[VAL_0]], %[[VAL_1]]) -// CHECK: aie.packet_rules(West : 0) { +// CHECK: %[[VAL_2:.*]] = aie.masterset(CORE : 0, %[[VAL_0]]) +// CHECK: %[[VAL_3:.*]] = aie.masterset(CORE : 1, %[[VAL_0]], %[[VAL_1]]) +// CHECK: aie.packet_rules(WEST : 0) { // CHECK: aie.rule(31, 0, %[[VAL_0]]) // CHECK: } -// CHECK: aie.packet_rules(West : 1) { +// CHECK: aie.packet_rules(WEST : 1) { // CHECK: aie.rule(31, 1, %[[VAL_1]]) // CHECK: } // CHECK: } // CHECK: aie.packet_flow(0) { -// CHECK: aie.packet_source<%[[TILE_1_1]], West : 0> -// CHECK: aie.packet_dest<%[[TILE_1_1]], Core : 0> -// CHECK: aie.packet_dest<%[[TILE_1_1]], Core : 1> +// CHECK: aie.packet_source<%[[TILE_1_1]], WEST : 0> +// CHECK: aie.packet_dest<%[[TILE_1_1]], CORE : 0> +// CHECK: aie.packet_dest<%[[TILE_1_1]], CORE : 1> // CHECK: } // CHECK: aie.packet_flow(1) { -// CHECK: aie.packet_source<%[[TILE_1_1]], West : 1> -// CHECK: aie.packet_dest<%[[TILE_1_1]], Core : 1> +// CHECK: aie.packet_source<%[[TILE_1_1]], WEST : 1> +// CHECK: aie.packet_dest<%[[TILE_1_1]], CORE : 1> // CHECK: } // CHECK: } @@ -30,14 +30,14 @@ module @test_create_packet_flows3 { %t11 = aie.tile(1, 1) aie.packet_flow(0x0) { - aie.packet_source<%t11, West : 0> - aie.packet_dest<%t11, Core : 0> - aie.packet_dest<%t11, Core : 1> + aie.packet_source<%t11, WEST : 0> + aie.packet_dest<%t11, CORE : 0> + aie.packet_dest<%t11, CORE : 1> } aie.packet_flow(0x1) { - aie.packet_source<%t11, West : 1> - aie.packet_dest<%t11, Core : 1> + aie.packet_source<%t11, WEST : 1> + aie.packet_dest<%t11, CORE : 1> } } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows4.mlir b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows4.mlir index a63c4f2da..63551a3f3 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows4.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows4.mlir @@ -7,13 +7,13 @@ module @test_create_packet_flows4 { // CHECK: %[[VAL_1:.*]] = aie.switchbox(%[[VAL_0]]) { // CHECK: %[[VAL_6:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_7:.*]] = aie.amsel<0> (1) -// CHECK: %[[VAL_4:.*]] = aie.masterset(Core : 0, %[[VAL_3:.*]]) -// CHECK: %[[VAL_5:.*]] = aie.masterset(Core : 1, %[[VAL_2:.*]]) -// CHECK: aie.packet_rules(West : 0) { +// CHECK: %[[VAL_4:.*]] = aie.masterset(CORE : 0, %[[VAL_3:.*]]) +// CHECK: %[[VAL_5:.*]] = aie.masterset(CORE : 1, %[[VAL_2:.*]]) +// CHECK: aie.packet_rules(WEST : 0) { // CHECK-DAG: aie.rule(31, 0, %[[VAL_3]]) // CHECK-DAG: aie.rule(31, 1, %[[VAL_2]]) // CHECK: } -// CHECK: aie.packet_rules(West : 1) { +// CHECK: aie.packet_rules(WEST : 1) { // CHECK-DAG: aie.rule(31, 0, %[[VAL_2]]) // CHECK: } // CHECK: } @@ -21,18 +21,18 @@ module @test_create_packet_flows4 { %t11 = aie.tile(1, 1) aie.packet_flow(0x0) { - aie.packet_source<%t11, West : 0> - aie.packet_dest<%t11, Core : 0> + aie.packet_source<%t11, WEST : 0> + aie.packet_dest<%t11, CORE : 0> } aie.packet_flow(0x1) { - aie.packet_source<%t11, West : 0> - aie.packet_dest<%t11, Core : 1> + aie.packet_source<%t11, WEST : 0> + aie.packet_dest<%t11, CORE : 1> } aie.packet_flow(0x0) { - aie.packet_source<%t11, West : 1> - aie.packet_dest<%t11, Core : 1> + aie.packet_source<%t11, WEST : 1> + aie.packet_dest<%t11, CORE : 1> } } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows5.mlir b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows5.mlir index 537b8d5a2..28469c7bd 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows5.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows5.mlir @@ -4,11 +4,11 @@ // CHECK: %[[VAL_0:.*]] = aie.tile(1, 1) // CHECK: %[[VAL_1:.*]] = aie.switchbox(%[[VAL_0]]) { // CHECK: %[[VAL_2:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_3:.*]] = aie.masterset(Core : 0, %[[VAL_2]]) -// CHECK: aie.packet_rules(West : 0) { +// CHECK: %[[VAL_3:.*]] = aie.masterset(CORE : 0, %[[VAL_2]]) +// CHECK: aie.packet_rules(WEST : 0) { // CHECK-DAG: aie.rule(30, 0, %[[VAL_2]]) // CHECK: } -// CHECK: aie.packet_rules(West : 1) { +// CHECK: aie.packet_rules(WEST : 1) { // CHECK-DAG: aie.rule(31, 2, %[[VAL_2]]) // CHECK: } // CHECK: } @@ -20,18 +20,18 @@ module @test_create_packet_flows5 { %t11 = aie.tile(1, 1) aie.packet_flow(0x0) { - aie.packet_source<%t11, West : 0> - aie.packet_dest<%t11, Core : 0> + aie.packet_source<%t11, WEST : 0> + aie.packet_dest<%t11, CORE : 0> } aie.packet_flow(0x1) { - aie.packet_source<%t11, West : 0> - aie.packet_dest<%t11, Core : 0> + aie.packet_source<%t11, WEST : 0> + aie.packet_dest<%t11, CORE : 0> } aie.packet_flow(0x2) { - aie.packet_source<%t11, West : 1> - aie.packet_dest<%t11, Core : 0> + aie.packet_source<%t11, WEST : 1> + aie.packet_dest<%t11, CORE : 0> } } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows6.mlir b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows6.mlir index 132bc20fa..fdeb821c3 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows6.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows6.mlir @@ -4,7 +4,7 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: %[[VAL_0:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_1:.*]] = aie.masterset(East : 0, %[[VAL_0]]) +// CHECK: %[[VAL_1:.*]] = aie.masterset(EAST : 0, %[[VAL_0]]) // CHECK: aie.packet_rules(DMA : 0) { // CHECK: aie.rule(28, 0, %[[VAL_0]]) // CHECK: } @@ -14,8 +14,8 @@ // CHECK: %[[VAL_2:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_3:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_4:.*]] = aie.masterset(DMA : 0, %[[VAL_2]]) -// CHECK: %[[VAL_5:.*]] = aie.masterset(East : 0, %[[VAL_3]]) -// CHECK: aie.packet_rules(West : 0) { +// CHECK: %[[VAL_5:.*]] = aie.masterset(EAST : 0, %[[VAL_3]]) +// CHECK: aie.packet_rules(WEST : 0) { // CHECK-DAG: aie.rule(31, 0, %[[VAL_2]]) // CHECK-DAG: aie.rule(28, 0, %[[VAL_3]]) // CHECK: } @@ -25,8 +25,8 @@ // CHECK: %[[VAL_6:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_7:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_8:.*]] = aie.masterset(DMA : 0, %[[VAL_6]]) -// CHECK: %[[VAL_9:.*]] = aie.masterset(East : 0, %[[VAL_7]]) -// CHECK: aie.packet_rules(West : 0) { +// CHECK: %[[VAL_9:.*]] = aie.masterset(EAST : 0, %[[VAL_7]]) +// CHECK: aie.packet_rules(WEST : 0) { // CHECK-DAG: aie.rule(30, 2, %[[VAL_7]]) // CHECK-DAG: aie.rule(31, 1, %[[VAL_6]]) // CHECK: } @@ -36,8 +36,8 @@ // CHECK: %[[VAL_10:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_11:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_12:.*]] = aie.masterset(DMA : 0, %[[VAL_10]]) -// CHECK: %[[VAL_13:.*]] = aie.masterset(East : 0, %[[VAL_11]]) -// CHECK: aie.packet_rules(West : 0) { +// CHECK: %[[VAL_13:.*]] = aie.masterset(EAST : 0, %[[VAL_11]]) +// CHECK: aie.packet_rules(WEST : 0) { // CHECK-DAG: aie.rule(31, 2, %[[VAL_10]]) // CHECK-DAG: aie.rule(31, 3, %[[VAL_11]]) // CHECK: } @@ -46,7 +46,7 @@ // CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { // CHECK: %[[VAL_14:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_15:.*]] = aie.masterset(DMA : 0, %[[VAL_14]]) -// CHECK: aie.packet_rules(West : 0) { +// CHECK: aie.packet_rules(WEST : 0) { // CHECK: aie.rule(31, 3, %[[VAL_14]]) // CHECK: } // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows_shim0.mlir b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows_shim0.mlir index 2026ef2c3..30d0e7e91 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows_shim0.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows_shim0.mlir @@ -3,19 +3,19 @@ // CHECK-LABEL: module @aie_module { // CHECK: %[[VAL_0:.*]] = aie.tile(7, 0) // CHECK: %[[VAL_1:.*]] = aie.shim_mux(%[[VAL_0:.*]]) { -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[VAL_2:.*]] = aie.switchbox(%[[VAL_0:.*]]) { // CHECK: %[[VAL_3:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_4:.*]] = aie.masterset(South : 3, %[[VAL_3:.*]]) -// CHECK: aie.packet_rules(North : 0) { +// CHECK: %[[VAL_4:.*]] = aie.masterset(SOUTH : 3, %[[VAL_3:.*]]) +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(31, 10, %[[VAL_3:.*]]) // CHECK: } // CHECK: } // CHECK: %[[VAL_5:.*]] = aie.tile(7, 1) // CHECK: %[[VAL_6:.*]] = aie.switchbox(%[[VAL_5:.*]]) { // CHECK: %[[VAL_7:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_8:.*]] = aie.masterset(South : 0, %[[VAL_6:.*]]) +// CHECK: %[[VAL_8:.*]] = aie.masterset(SOUTH : 0, %[[VAL_6:.*]]) // CHECK: aie.packet_rules(DMA : 0) { // CHECK: aie.rule(31, 10, %[[VAL_7:.*]]) // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows_shim1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows_shim1.mlir index 2170c2b42..93b643fa4 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows_shim1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/test_create_packet_flows_shim1.mlir @@ -3,12 +3,12 @@ // CHECK-LABEL: module @aie_module { // CHECK: %[[VAL_0:.*]] = aie.tile(7, 0) // CHECK: %[[VAL_1:.*]] = aie.shim_mux(%[[VAL_0:.*]]) { -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[VAL_2:.*]] = aie.switchbox(%[[VAL_0:.*]]) { // CHECK: %[[VAL_3:.*]] = aie.amsel<0> (0) -// CHECK: %[[VAL_4:.*]] = aie.masterset(North : 0, %[[VAL_3:.*]]) -// CHECK: aie.packet_rules(South : 3) { +// CHECK: %[[VAL_4:.*]] = aie.masterset(NORTH : 0, %[[VAL_3:.*]]) +// CHECK: aie.packet_rules(SOUTH : 3) { // CHECK: aie.rule(31, 3, %[[VAL_3:.*]]) // CHECK: } // CHECK: } @@ -16,7 +16,7 @@ // CHECK: %[[VAL_6:.*]] = aie.switchbox(%[[VAL_5:.*]]) { // CHECK: %[[VAL_7:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_8:.*]] = aie.masterset(DMA : 0, %[[VAL_7:.*]]) -// CHECK: aie.packet_rules(South : 0) { +// CHECK: aie.packet_rules(SOUTH : 0) { // CHECK: aie.rule(31, 3, %[[VAL_7:.*]]) // CHECK: } // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/test_pktflow_weight_pusher.mlir b/compiler/plugins/target/AMD-AIE/aie/test/test_pktflow_weight_pusher.mlir index d321178c1..ababa7692 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/test_pktflow_weight_pusher.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/test_pktflow_weight_pusher.mlir @@ -5,7 +5,7 @@ // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: %[[VAL_0:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_1:.*]] = aie.masterset(DMA : 1, %[[VAL_0]]) -// CHECK: aie.packet_rules(East : 0) { +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(31, 0, %[[VAL_0]]) // CHECK: } // CHECK: } @@ -14,8 +14,8 @@ // CHECK: %[[VAL_2:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_3:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_4:.*]] = aie.masterset(DMA : 1, %[[VAL_3]]) -// CHECK: %[[VAL_5:.*]] = aie.masterset(West : 0, %[[VAL_2]]) -// CHECK: aie.packet_rules(East : 0) { +// CHECK: %[[VAL_5:.*]] = aie.masterset(WEST : 0, %[[VAL_2]]) +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(31, 0, %[[VAL_2]]) // CHECK: aie.rule(31, 4, %[[VAL_3]]) // CHECK: } @@ -25,8 +25,8 @@ // CHECK: %[[VAL_6:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_7:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_8:.*]] = aie.masterset(DMA : 1, %[[VAL_7]]) -// CHECK: %[[VAL_9:.*]] = aie.masterset(West : 0, %[[VAL_6]]) -// CHECK: aie.packet_rules(North : 0) { +// CHECK: %[[VAL_9:.*]] = aie.masterset(WEST : 0, %[[VAL_6]]) +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(27, 0, %[[VAL_6]]) // CHECK: aie.rule(31, 8, %[[VAL_7]]) // CHECK: } @@ -35,7 +35,7 @@ // CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { // CHECK: %[[VAL_10:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_11:.*]] = aie.masterset(DMA : 1, %[[VAL_10]]) -// CHECK: aie.packet_rules(North : 0) { +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(31, 12, %[[VAL_10]]) // CHECK: } // CHECK: } @@ -43,7 +43,7 @@ // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: %[[VAL_12:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_13:.*]] = aie.masterset(DMA : 1, %[[VAL_12]]) -// CHECK: aie.packet_rules(North : 0) { +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(31, 1, %[[VAL_12]]) // CHECK: } // CHECK: } @@ -51,7 +51,7 @@ // CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { // CHECK: %[[VAL_14:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_15:.*]] = aie.masterset(DMA : 1, %[[VAL_14]]) -// CHECK: aie.packet_rules(East : 0) { +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(31, 5, %[[VAL_14]]) // CHECK: } // CHECK: } @@ -61,13 +61,13 @@ // CHECK: %[[VAL_17:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_18:.*]] = aie.amsel<0> (2) // CHECK: %[[VAL_19:.*]] = aie.masterset(DMA : 1, %[[VAL_18]]) -// CHECK: %[[VAL_20:.*]] = aie.masterset(South : 0, %[[VAL_16]]) -// CHECK: %[[VAL_21:.*]] = aie.masterset(West : 0, %[[VAL_17]]) -// CHECK: aie.packet_rules(North : 0) { +// CHECK: %[[VAL_20:.*]] = aie.masterset(SOUTH : 0, %[[VAL_16]]) +// CHECK: %[[VAL_21:.*]] = aie.masterset(WEST : 0, %[[VAL_17]]) +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(27, 0, %[[VAL_16]]) // CHECK: aie.rule(31, 5, %[[VAL_17]]) // CHECK: } -// CHECK: aie.packet_rules(East : 0) { +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(31, 8, %[[VAL_16]]) // CHECK: aie.rule(31, 9, %[[VAL_18]]) // CHECK: } @@ -78,9 +78,9 @@ // CHECK: %[[VAL_23:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_24:.*]] = aie.amsel<0> (2) // CHECK: %[[VAL_25:.*]] = aie.masterset(DMA : 1, %[[VAL_24]]) -// CHECK: %[[VAL_26:.*]] = aie.masterset(South : 0, %[[VAL_23]]) -// CHECK: %[[VAL_27:.*]] = aie.masterset(West : 0, %[[VAL_22]]) -// CHECK: aie.packet_rules(North : 0) { +// CHECK: %[[VAL_26:.*]] = aie.masterset(SOUTH : 0, %[[VAL_23]]) +// CHECK: %[[VAL_27:.*]] = aie.masterset(WEST : 0, %[[VAL_22]]) +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(30, 8, %[[VAL_22]]) // CHECK: aie.rule(31, 12, %[[VAL_23]]) // CHECK: aie.rule(31, 13, %[[VAL_24]]) @@ -91,8 +91,8 @@ // CHECK: %[[VAL_28:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_29:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_30:.*]] = aie.masterset(DMA : 1, %[[VAL_29]]) -// CHECK: %[[VAL_31:.*]] = aie.masterset(South : 0, %[[VAL_28]]) -// CHECK: aie.packet_rules(North : 0) { +// CHECK: %[[VAL_31:.*]] = aie.masterset(SOUTH : 0, %[[VAL_28]]) +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(31, 1, %[[VAL_28]]) // CHECK: aie.rule(31, 2, %[[VAL_29]]) // CHECK: } @@ -101,7 +101,7 @@ // CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { // CHECK: %[[VAL_32:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_33:.*]] = aie.masterset(DMA : 1, %[[VAL_32]]) -// CHECK: aie.packet_rules(East : 0) { +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(31, 6, %[[VAL_32]]) // CHECK: } // CHECK: } @@ -111,12 +111,12 @@ // CHECK: %[[VAL_35:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_36:.*]] = aie.amsel<0> (2) // CHECK: %[[VAL_37:.*]] = aie.masterset(DMA : 1, %[[VAL_34]]) -// CHECK: %[[VAL_38:.*]] = aie.masterset(South : 0, %[[VAL_35]]) -// CHECK: %[[VAL_39:.*]] = aie.masterset(West : 0, %[[VAL_36]]) -// CHECK: aie.packet_rules(North : 0) { +// CHECK: %[[VAL_38:.*]] = aie.masterset(SOUTH : 0, %[[VAL_35]]) +// CHECK: %[[VAL_39:.*]] = aie.masterset(WEST : 0, %[[VAL_36]]) +// CHECK: aie.packet_rules(NORTH : 0) { // CHECK: aie.rule(31, 10, %[[VAL_34]]) // CHECK: } -// CHECK: aie.packet_rules(East : 0) { +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(26, 0, %[[VAL_35]]) // CHECK: aie.rule(31, 6, %[[VAL_36]]) // CHECK: } @@ -127,9 +127,9 @@ // CHECK: %[[VAL_41:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_42:.*]] = aie.amsel<0> (2) // CHECK: %[[VAL_43:.*]] = aie.masterset(DMA : 1, %[[VAL_42]]) -// CHECK: %[[VAL_44:.*]] = aie.masterset(South : 0, %[[VAL_41]]) -// CHECK: %[[VAL_45:.*]] = aie.masterset(West : 0, %[[VAL_40]]) -// CHECK: aie.packet_rules(East : 0) { +// CHECK: %[[VAL_44:.*]] = aie.masterset(SOUTH : 0, %[[VAL_41]]) +// CHECK: %[[VAL_45:.*]] = aie.masterset(WEST : 0, %[[VAL_40]]) +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(24, 0, %[[VAL_40]]) // CHECK: aie.rule(26, 8, %[[VAL_41]]) // CHECK: aie.rule(31, 14, %[[VAL_42]]) @@ -140,8 +140,8 @@ // CHECK: %[[VAL_46:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_47:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_48:.*]] = aie.masterset(DMA : 1, %[[VAL_47]]) -// CHECK: %[[VAL_49:.*]] = aie.masterset(South : 0, %[[VAL_46]]) -// CHECK: aie.packet_rules(East : 0) { +// CHECK: %[[VAL_49:.*]] = aie.masterset(SOUTH : 0, %[[VAL_46]]) +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(28, 0, %[[VAL_46]]) // CHECK: aie.rule(31, 3, %[[VAL_47]]) // CHECK: } @@ -151,8 +151,8 @@ // CHECK: %[[VAL_50:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_51:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_52:.*]] = aie.masterset(DMA : 1, %[[VAL_51]]) -// CHECK: %[[VAL_53:.*]] = aie.masterset(West : 0, %[[VAL_50]]) -// CHECK: aie.packet_rules(East : 0) { +// CHECK: %[[VAL_53:.*]] = aie.masterset(WEST : 0, %[[VAL_50]]) +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(28, 0, %[[VAL_50]]) // CHECK: aie.rule(31, 7, %[[VAL_51]]) // CHECK: } @@ -163,9 +163,9 @@ // CHECK: %[[VAL_55:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_56:.*]] = aie.amsel<0> (2) // CHECK: %[[VAL_57:.*]] = aie.masterset(DMA : 1, %[[VAL_56]]) -// CHECK: %[[VAL_58:.*]] = aie.masterset(South : 0, %[[VAL_55]]) -// CHECK: %[[VAL_59:.*]] = aie.masterset(West : 0, %[[VAL_54]]) -// CHECK: aie.packet_rules(East : 0) { +// CHECK: %[[VAL_58:.*]] = aie.masterset(SOUTH : 0, %[[VAL_55]]) +// CHECK: %[[VAL_59:.*]] = aie.masterset(WEST : 0, %[[VAL_54]]) +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(24, 0, %[[VAL_54]]) // CHECK: aie.rule(31, 10, %[[VAL_55]]) // CHECK: aie.rule(31, 11, %[[VAL_56]]) @@ -176,8 +176,8 @@ // CHECK: %[[VAL_60:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_61:.*]] = aie.amsel<0> (1) // CHECK: %[[VAL_62:.*]] = aie.masterset(DMA : 1, %[[VAL_61]]) -// CHECK: %[[VAL_63:.*]] = aie.masterset(West : 0, %[[VAL_60]]) -// CHECK: aie.packet_rules(East : 0) { +// CHECK: %[[VAL_63:.*]] = aie.masterset(WEST : 0, %[[VAL_60]]) +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(16, 0, %[[VAL_60]]) // CHECK: aie.rule(31, 15, %[[VAL_61]]) // CHECK: } @@ -186,13 +186,13 @@ // CHECK: %[[SWITCHBOX_6_5:.*]] = aie.switchbox(%[[TILE_6_5]]) { // CHECK: %[[VAL_64:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_65:.*]] = aie.amsel<0> (1) -// CHECK: %[[VAL_66:.*]] = aie.masterset(South : 0, %[[VAL_64]]) -// CHECK: %[[VAL_67:.*]] = aie.masterset(West : 0, %[[VAL_65]]) +// CHECK: %[[VAL_66:.*]] = aie.masterset(SOUTH : 0, %[[VAL_64]]) +// CHECK: %[[VAL_67:.*]] = aie.masterset(WEST : 0, %[[VAL_65]]) // CHECK: aie.packet_rules(DMA : 0) { // CHECK: aie.rule(24, 0, %[[VAL_64]]) // CHECK: aie.rule(24, 0, %[[VAL_65]]) // CHECK: } -// CHECK: aie.packet_rules(East : 0) { +// CHECK: aie.packet_rules(EAST : 0) { // CHECK: aie.rule(26, 10, %[[VAL_65]]) // CHECK: } // CHECK: } @@ -200,8 +200,8 @@ // CHECK: %[[SWITCHBOX_7_5:.*]] = aie.switchbox(%[[TILE_7_5]]) { // CHECK: %[[VAL_68:.*]] = aie.amsel<0> (0) // CHECK: %[[VAL_69:.*]] = aie.amsel<0> (1) -// CHECK: %[[VAL_70:.*]] = aie.masterset(South : 0, %[[VAL_68]]) -// CHECK: %[[VAL_71:.*]] = aie.masterset(West : 0, %[[VAL_69]]) +// CHECK: %[[VAL_70:.*]] = aie.masterset(SOUTH : 0, %[[VAL_68]]) +// CHECK: %[[VAL_71:.*]] = aie.masterset(WEST : 0, %[[VAL_69]]) // CHECK: aie.packet_rules(DMA : 0) { // CHECK: aie.rule(24, 8, %[[VAL_68]]) // CHECK: aie.rule(26, 10, %[[VAL_69]]) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/tileDMA_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/tileDMA_test.mlir index e6913470d..6059972da 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/tileDMA_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/tileDMA_test.mlir @@ -8,12 +8,12 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OBJFIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> // CHECK: %[[OBJFIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "objfifo_cons_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "objfifo_cons_cons_lock"} +// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "objfifo_cons_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "objfifo_cons_cons_lock"} // CHECK: %[[OBJFIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> // CHECK: %[[OBJFIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> -// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 2 : i32, sym_name = "objfifo_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 4) {init = 0 : i32, sym_name = "objfifo_cons_lock"} +// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 2 : i8, sym_name = "objfifo_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 4) {init = 0 : i8, sym_name = "objfifo_cons_lock"} // CHECK: %[[BUFFER_1_2:.*]] = aie.buffer(%[[TILE_1_2]]) : memref<16xi32> // CHECK: %[[LOCK_1_2:.*]] = aie.lock(%[[TILE_1_2]], 0) // CHECK: %[[BUFFER_1_2_0:.*]] = aie.buffer(%[[TILE_1_2]]) : memref<16xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/test/trace_packet_routing.mlir b/compiler/plugins/target/AMD-AIE/aie/test/trace_packet_routing.mlir index 39987c746..76d55e212 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/trace_packet_routing.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/trace_packet_routing.mlir @@ -10,11 +10,11 @@ module @trace_packet_routing { %tile_0_3 = aie.tile(0, 3) aie.packet_flow(0) { - aie.packet_source<%tile_0_2, Trace : 0> // core trace + aie.packet_source<%tile_0_2, TRACE : 0> // core trace aie.packet_dest<%tile_0_0, DMA : 1> } {keep_pkt_header = true} aie.packet_flow(1) { - aie.packet_source<%tile_0_3, Trace : 0> // core trace + aie.packet_source<%tile_0_3, TRACE : 0> // core trace aie.packet_dest<%tile_1_0, DMA : 1> } {keep_pkt_header = true} } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_broadcast.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_broadcast.mlir index 14a872b4e..be1d885b7 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_broadcast.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_broadcast.mlir @@ -21,113 +21,113 @@ // CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) // CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) // CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) // CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) // CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) // CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) // CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) // CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) // CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) // CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) // CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_fixed_connections.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_fixed_connections.mlir index 9241a8735..df9fb8eec 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_fixed_connections.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_fixed_connections.mlir @@ -7,20 +7,20 @@ // CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) // CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -31,20 +31,20 @@ module { %tile_6_0 = aie.tile(6, 0) %tile_7_0 = aie.tile(7, 0) %switchbox_2_0 = aie.switchbox(%tile_2_0) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_3_0 = aie.switchbox(%tile_3_0) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_6_0 = aie.switchbox(%tile_6_0) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_7_0 = aie.switchbox(%tile_7_0) { - aie.connect - aie.connect + aie.connect + aie.connect } } } @@ -63,38 +63,38 @@ module { // CHECK: %[[TILE_10_2:.*]] = aie.tile(10, 2) // CHECK: %[[TILE_11_3:.*]] = aie.tile(11, 3) // CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_9_2:.*]] = aie.switchbox(%[[TILE_9_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_2:.*]] = aie.switchbox(%[[TILE_10_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_11_3:.*]] = aie.switchbox(%[[TILE_11_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -111,38 +111,38 @@ module { %tile_10_2 = aie.tile(10, 2) %tile_11_3 = aie.tile(11, 3) %switchbox_0_3 = aie.switchbox(%tile_0_3) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_1_4 = aie.switchbox(%tile_1_4) { - aie.connect + aie.connect } %switchbox_3_3 = aie.switchbox(%tile_3_3) { - aie.connect + aie.connect } %switchbox_4_2 = aie.switchbox(%tile_4_2) { - aie.connect + aie.connect } %switchbox_5_3 = aie.switchbox(%tile_5_3) { - aie.connect + aie.connect } %switchbox_6_3 = aie.switchbox(%tile_6_3) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_7_4 = aie.switchbox(%tile_7_4) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_9_2 = aie.switchbox(%tile_9_2) { - aie.connect + aie.connect } %switchbox_10_2 = aie.switchbox(%tile_10_2) { - aie.connect + aie.connect } %switchbox_11_3 = aie.switchbox(%tile_11_3) { - aie.connect - aie.connect + aie.connect + aie.connect } } } @@ -157,28 +157,28 @@ module { // CHECK: %[[TILE_12_5:.*]] = aie.tile(12, 5) // CHECK: %[[TILE_13_3:.*]] = aie.tile(13, 3) // CHECK: %[[SWITCHBOX_2_5:.*]] = aie.switchbox(%[[TILE_2_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_6:.*]] = aie.switchbox(%[[TILE_6_6]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_12_5:.*]] = aie.switchbox(%[[TILE_12_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_13_3:.*]] = aie.switchbox(%[[TILE_13_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -191,28 +191,28 @@ module { %tile_12_5 = aie.tile(12, 5) %tile_13_3 = aie.tile(13, 3) %switchbox_2_5 = aie.switchbox(%tile_2_5) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_3_1 = aie.switchbox(%tile_3_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_6_6 = aie.switchbox(%tile_6_6) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_7_3 = aie.switchbox(%tile_7_3) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_12_5 = aie.switchbox(%tile_12_5) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_13_3 = aie.switchbox(%tile_13_3) { - aie.connect - aie.connect + aie.connect + aie.connect } } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_flow_test_1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_flow_test_1.mlir index 3f208ec6e..891b6b360 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_flow_test_1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_flow_test_1.mlir @@ -15,269 +15,269 @@ // CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) // CHECK: %[[TILE_8_4:.*]] = aie.tile(8, 4) // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) // CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) // CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) // CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) // CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) // CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) // CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) // CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) // CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_5_4:.*]] = aie.switchbox(%[[TILE_5_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_4_4:.*]] = aie.switchbox(%[[TILE_4_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_4:.*]] = aie.tile(6, 4) // CHECK: %[[SWITCHBOX_6_4:.*]] = aie.switchbox(%[[TILE_6_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) // CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) // CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) // CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) // CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) // CHECK: %[[SWITCHBOX_8_0:.*]] = aie.switchbox(%[[TILE_8_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_8_1:.*]] = aie.tile(8, 1) // CHECK: %[[SWITCHBOX_8_1:.*]] = aie.switchbox(%[[TILE_8_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) // CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -299,25 +299,25 @@ module { aie.flow(%t20, DMA : 1, %t83, DMA : 0) aie.flow(%t30, DMA : 0, %t72, DMA : 0) aie.flow(%t30, DMA : 1, %t54, DMA : 0) - aie.flow(%t34, Core : 0, %t63, Core : 1) + aie.flow(%t34, CORE : 0, %t63, CORE : 1) aie.flow(%t34, DMA : 1, %t70, DMA : 0) - aie.flow(%t43, Core : 0, %t84, Core : 1) + aie.flow(%t43, CORE : 0, %t84, CORE : 1) aie.flow(%t43, DMA : 1, %t60, DMA : 1) - aie.flow(%t44, Core : 0, %t54, Core : 1) + aie.flow(%t44, CORE : 0, %t54, CORE : 1) aie.flow(%t44, DMA : 1, %t60, DMA : 0) - aie.flow(%t54, Core : 0, %t43, Core : 1) + aie.flow(%t54, CORE : 0, %t43, CORE : 1) aie.flow(%t54, DMA : 1, %t30, DMA : 1) aie.flow(%t60, DMA : 0, %t44, DMA : 0) aie.flow(%t60, DMA : 1, %t43, DMA : 0) - aie.flow(%t63, Core : 0, %t34, Core : 1) + aie.flow(%t63, CORE : 0, %t34, CORE : 1) aie.flow(%t63, DMA : 1, %t20, DMA : 1) aie.flow(%t70, DMA : 0, %t34, DMA : 0) aie.flow(%t70, DMA : 1, %t84, DMA : 0) - aie.flow(%t72, Core : 0, %t83, Core : 1) + aie.flow(%t72, CORE : 0, %t83, CORE : 1) aie.flow(%t72, DMA : 1, %t30, DMA : 0) - aie.flow(%t83, Core : 0, %t44, Core : 1) + aie.flow(%t83, CORE : 0, %t44, CORE : 1) aie.flow(%t83, DMA : 1, %t20, DMA : 0) - aie.flow(%t84, Core : 0, %t72, Core : 1) + aie.flow(%t84, CORE : 0, %t72, CORE : 1) aie.flow(%t84, DMA : 1, %t70, DMA : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_flow_test_2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_flow_test_2.mlir index bb106fb4f..fecc0ac20 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_flow_test_2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_flow_test_2.mlir @@ -22,127 +22,127 @@ // CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) // CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) // CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -168,30 +168,30 @@ module { %t34 = aie.tile(3, 4) //TASK 1 aie.flow(%t20, DMA : 0, %t11, DMA : 0) - aie.flow(%t11, Core : 0, %t01, Core : 0) - aie.flow(%t01, Core : 0, %t12, Core : 0) - aie.flow(%t12, Core : 0, %t02, Core : 0) + aie.flow(%t11, CORE : 0, %t01, CORE : 0) + aie.flow(%t01, CORE : 0, %t12, CORE : 0) + aie.flow(%t12, CORE : 0, %t02, CORE : 0) aie.flow(%t02, DMA : 0, %t20, DMA : 0) //TASK 2 aie.flow(%t20, DMA : 1, %t14, DMA : 0) - aie.flow(%t14, Core : 0, %t04, Core : 0) - aie.flow(%t04, Core : 0, %t13, Core : 0) + aie.flow(%t14, CORE : 0, %t04, CORE : 0) + aie.flow(%t04, CORE : 0, %t13, CORE : 0) aie.flow(%t13, DMA : 0, %t20, DMA : 1) //TASK 3 aie.flow(%t30, DMA : 0, %t21, DMA : 0) - aie.flow(%t21, Core : 0, %t33, Core : 0) - aie.flow(%t33, Core : 0, %t22, Core : 0) - aie.flow(%t22, Core : 0, %t34, Core : 0) - aie.flow(%t34, Core : 0, %t24, Core : 0) - aie.flow(%t24, Core : 0, %t23, Core : 0) + aie.flow(%t21, CORE : 0, %t33, CORE : 0) + aie.flow(%t33, CORE : 0, %t22, CORE : 0) + aie.flow(%t22, CORE : 0, %t34, CORE : 0) + aie.flow(%t34, CORE : 0, %t24, CORE : 0) + aie.flow(%t24, CORE : 0, %t23, CORE : 0) aie.flow(%t23, DMA : 0, %t30, DMA : 0) //TASK 4 aie.flow(%t30, DMA : 1, %t31, DMA : 1) - aie.flow(%t31, Core : 1, %t23, Core : 1) - aie.flow(%t23, Core : 1, %t34, Core : 1) - aie.flow(%t34, Core : 1, %t24, Core : 1) - aie.flow(%t24, Core : 1, %t33, Core : 1) - aie.flow(%t33, Core : 1, %t32, Core : 1) + aie.flow(%t31, CORE : 1, %t23, CORE : 1) + aie.flow(%t23, CORE : 1, %t34, CORE : 1) + aie.flow(%t34, CORE : 1, %t24, CORE : 1) + aie.flow(%t24, CORE : 1, %t33, CORE : 1) + aie.flow(%t33, CORE : 1, %t32, CORE : 1) aie.flow(%t32, DMA : 1, %t30, DMA : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_flow_test_3.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_flow_test_3.mlir index 1472867df..d94ba7178 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_flow_test_3.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_flow_test_3.mlir @@ -25,268 +25,268 @@ // CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) // CHECK: %[[TILE_8_4:.*]] = aie.tile(8, 4) // CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) // CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) // CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) // CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) // CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) // CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) // CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_4:.*]] = aie.tile(4, 4) // CHECK: %[[SWITCHBOX_4_4:.*]] = aie.switchbox(%[[TILE_4_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_4:.*]] = aie.tile(5, 4) // CHECK: %[[SWITCHBOX_5_4:.*]] = aie.switchbox(%[[TILE_5_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_4:.*]] = aie.tile(6, 4) // CHECK: %[[SWITCHBOX_6_4:.*]] = aie.switchbox(%[[TILE_6_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) // CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) // CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) // CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) // CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) // CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -316,27 +316,27 @@ module { %t84 = aie.tile(8, 4) //TASK 1 aie.flow(%t20, DMA : 0, %t03, DMA : 0) - aie.flow(%t03, Core : 0, %t71, Core : 0) - aie.flow(%t71, Core : 0, %t84, Core : 0) - aie.flow(%t84, Core : 0, %t11, Core : 0) - aie.flow(%t11, Core : 0, %t24, Core : 0) + aie.flow(%t03, CORE : 0, %t71, CORE : 0) + aie.flow(%t71, CORE : 0, %t84, CORE : 0) + aie.flow(%t84, CORE : 0, %t11, CORE : 0) + aie.flow(%t11, CORE : 0, %t24, CORE : 0) aie.flow(%t24, DMA : 0, %t20, DMA : 0) //TASK 2 aie.flow(%t30, DMA : 0, %t14, DMA : 0) - aie.flow(%t14, Core : 0, %t01, Core : 0) - aie.flow(%t01, Core : 0, %t83, Core : 0) - aie.flow(%t83, Core : 0, %t21, Core : 0) - aie.flow(%t21, Core : 0, %t73, Core : 0) - aie.flow(%t73, Core : 0, %t82, Core : 0) + aie.flow(%t14, CORE : 0, %t01, CORE : 0) + aie.flow(%t01, CORE : 0, %t83, CORE : 0) + aie.flow(%t83, CORE : 0, %t21, CORE : 0) + aie.flow(%t21, CORE : 0, %t73, CORE : 0) + aie.flow(%t73, CORE : 0, %t82, CORE : 0) aie.flow(%t82, DMA : 0, %t30, DMA : 0) //TASK 3 aie.flow(%t20, DMA : 1, %t83, DMA : 1) - aie.flow(%t83, Core : 1, %t01, Core : 1) - aie.flow(%t01, Core : 1, %t72, Core : 1) - aie.flow(%t72, Core : 1, %t02, Core : 1) - aie.flow(%t02, Core : 1, %t24, Core : 1) - aie.flow(%t24, Core : 1, %t71, Core : 1) - aie.flow(%t71, Core : 1, %t84, Core : 1) + aie.flow(%t83, CORE : 1, %t01, CORE : 1) + aie.flow(%t01, CORE : 1, %t72, CORE : 1) + aie.flow(%t72, CORE : 1, %t02, CORE : 1) + aie.flow(%t02, CORE : 1, %t24, CORE : 1) + aie.flow(%t24, CORE : 1, %t71, CORE : 1) + aie.flow(%t71, CORE : 1, %t84, CORE : 1) aie.flow(%t84, DMA : 1, %t20, DMA : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_many_flows.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_many_flows.mlir index 2696ff627..bbaa18045 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_many_flows.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_many_flows.mlir @@ -14,182 +14,182 @@ // CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) // CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) // CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) // CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) // CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) // CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) // CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) // CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) // CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) // CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) // CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) // CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) // CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) // CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) // CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) // CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) // CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) // CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -210,15 +210,15 @@ module { aie.flow(%t13, DMA : 0, %t70, DMA : 1) aie.flow(%t02, DMA : 0, %t60, DMA : 0) aie.flow(%t22, DMA : 0, %t60, DMA : 1) - aie.flow(%t03, Core : 0, %t13, Core : 0) - aie.flow(%t03, Core : 1, %t02, Core : 0) - aie.flow(%t13, Core : 1, %t22, Core : 0) - aie.flow(%t02, Core : 1, %t22, Core : 1) + aie.flow(%t03, CORE : 0, %t13, CORE : 0) + aie.flow(%t03, CORE : 1, %t02, CORE : 0) + aie.flow(%t13, CORE : 1, %t22, CORE : 0) + aie.flow(%t02, CORE : 1, %t22, CORE : 1) aie.flow(%t73, DMA : 0, %t20, DMA : 0) aie.flow(%t73, DMA : 1, %t30, DMA : 0) aie.flow(%t31, DMA : 0, %t20, DMA : 1) aie.flow(%t31, DMA : 1, %t30, DMA : 1) - aie.flow(%t73, Core : 0, %t31, Core : 0) - aie.flow(%t73, Core : 1, %t31, Core : 1) + aie.flow(%t73, CORE : 0, %t31, CORE : 0) + aie.flow(%t73, CORE : 1, %t31, CORE : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_many_flows2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_many_flows2.mlir index 6aa08e0a9..9c004d4e7 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_many_flows2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_many_flows2.mlir @@ -14,166 +14,166 @@ // CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) // CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) // CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) // CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) // CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) // CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) // CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) // CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) // CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) // CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) // CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) // CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) // CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) // CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) // CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) // CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) // CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) // CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -194,15 +194,15 @@ module { aie.flow(%t03, DMA : 1, %t70, DMA : 1) aie.flow(%t02, DMA : 0, %t60, DMA : 0) aie.flow(%t22, DMA : 0, %t20, DMA : 0) - aie.flow(%t22, Core : 0, %t13, Core : 0) - aie.flow(%t03, Core : 1, %t02, Core : 0) - aie.flow(%t73, Core : 0, %t31, Core : 0) - aie.flow(%t73, Core : 1, %t22, Core : 1) + aie.flow(%t22, CORE : 0, %t13, CORE : 0) + aie.flow(%t03, CORE : 1, %t02, CORE : 0) + aie.flow(%t73, CORE : 0, %t31, CORE : 0) + aie.flow(%t73, CORE : 1, %t22, CORE : 1) aie.flow(%t73, DMA : 0, %t60, DMA : 1) aie.flow(%t73, DMA : 1, %t70, DMA : 0) aie.flow(%t31, DMA : 0, %t20, DMA : 1) aie.flow(%t31, DMA : 1, %t30, DMA : 1) - aie.flow(%t03, Core : 0, %t02, Core : 1) - aie.flow(%t13, Core : 1, %t31, Core : 1) + aie.flow(%t03, CORE : 0, %t02, CORE : 1) + aie.flow(%t13, CORE : 1, %t31, CORE : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_memtile.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_memtile.mlir index 5a4b0301f..b34ab15ca 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_memtile.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_memtile.mlir @@ -7,40 +7,40 @@ // CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) // CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) // CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_memtile_routing_constraints.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_memtile_routing_constraints.mlir index fb7a7a310..f78673091 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_memtile_routing_constraints.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_memtile_routing_constraints.mlir @@ -7,21 +7,21 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_mmult.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_mmult.mlir index 5e654e530..d459a67c8 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_mmult.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_mmult.mlir @@ -166,172 +166,172 @@ // CHECK: aie.end // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) // CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) // CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) // CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) // CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) // CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) // CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) // CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -501,64 +501,64 @@ module @aie.herd_0 { aie.end } %switchbox_2_0 = aie.switchbox(%tile_2_0) { - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } - aie.flow(%tile_2_1, South : 0, %tile_7_2, DMA : 0) - aie.flow(%tile_2_1, South : 1, %tile_7_2, DMA : 1) - aie.flow(%tile_7_2, DMA : 0, %tile_2_1, South : 0) + aie.flow(%tile_2_1, SOUTH : 0, %tile_7_2, DMA : 0) + aie.flow(%tile_2_1, SOUTH : 1, %tile_7_2, DMA : 1) + aie.flow(%tile_7_2, DMA : 0, %tile_2_1, SOUTH : 0) %switchbox_3_0 = aie.switchbox(%tile_3_0) { - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } - aie.flow(%tile_3_1, South : 0, %tile_8_2, DMA : 0) - aie.flow(%tile_3_1, South : 1, %tile_8_2, DMA : 1) - aie.flow(%tile_8_2, DMA : 0, %tile_2_1, South : 1) + aie.flow(%tile_3_1, SOUTH : 0, %tile_8_2, DMA : 0) + aie.flow(%tile_3_1, SOUTH : 1, %tile_8_2, DMA : 1) + aie.flow(%tile_8_2, DMA : 0, %tile_2_1, SOUTH : 1) %switchbox_6_0 = aie.switchbox(%tile_6_0) { - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } - aie.flow(%tile_6_1, South : 0, %tile_7_3, DMA : 0) - aie.flow(%tile_6_1, South : 1, %tile_7_3, DMA : 1) - aie.flow(%tile_7_3, DMA : 0, %tile_3_1, South : 0) + aie.flow(%tile_6_1, SOUTH : 0, %tile_7_3, DMA : 0) + aie.flow(%tile_6_1, SOUTH : 1, %tile_7_3, DMA : 1) + aie.flow(%tile_7_3, DMA : 0, %tile_3_1, SOUTH : 0) %switchbox_7_0 = aie.switchbox(%tile_7_0) { - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } - aie.flow(%tile_7_1, South : 0, %tile_8_3, DMA : 0) - aie.flow(%tile_7_1, South : 1, %tile_8_3, DMA : 1) - aie.flow(%tile_8_3, DMA : 0, %tile_3_1, South : 1) + aie.flow(%tile_7_1, SOUTH : 0, %tile_8_3, DMA : 0) + aie.flow(%tile_7_1, SOUTH : 1, %tile_8_3, DMA : 1) + aie.flow(%tile_8_3, DMA : 0, %tile_3_1, SOUTH : 1) %shimmux_2_0 = aie.shim_mux(%tile_2_0) { - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %shimmux_3_0 = aie.shim_mux(%tile_3_0) { - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %shimmux_6_0 = aie.shim_mux(%tile_6_0) { - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %shimmux_7_0 = aie.shim_mux(%tile_7_0) { - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_over_flows.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_over_flows.mlir index 23362e1a1..64e10669b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_over_flows.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_over_flows.mlir @@ -21,103 +21,103 @@ // CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) // CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) // CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) // CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) // CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) // CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) // CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_routed_herd_3x1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_routed_herd_3x1.mlir index a969e9aa3..7c201f0a8 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_routed_herd_3x1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_routed_herd_3x1.mlir @@ -69,102 +69,102 @@ // CHECK: %[[TILE_12_3:.*]] = aie.tile(12, 3) // CHECK: %[[TILE_12_4:.*]] = aie.tile(12, 4) // CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { // CHECK: } // CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { // CHECK: } // CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { // CHECK: } // CHECK: %[[SWITCHBOX_4_4:.*]] = aie.switchbox(%[[TILE_4_4]]) { // CHECK: } // CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_5_4:.*]] = aie.switchbox(%[[TILE_5_4]]) { // CHECK: } // CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_4:.*]] = aie.switchbox(%[[TILE_6_4]]) { // CHECK: } // CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_1:.*]] = aie.switchbox(%[[TILE_8_1]]) { // CHECK: } @@ -175,193 +175,193 @@ // CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { // CHECK: } // CHECK: %[[SWITCHBOX_9_1:.*]] = aie.switchbox(%[[TILE_9_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_9_2:.*]] = aie.switchbox(%[[TILE_9_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_9_3:.*]] = aie.switchbox(%[[TILE_9_3]]) { // CHECK: } // CHECK: %[[SWITCHBOX_9_4:.*]] = aie.switchbox(%[[TILE_9_4]]) { // CHECK: } // CHECK: %[[SWITCHBOX_10_1:.*]] = aie.switchbox(%[[TILE_10_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_2:.*]] = aie.switchbox(%[[TILE_10_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_3:.*]] = aie.switchbox(%[[TILE_10_3]]) { // CHECK: } // CHECK: %[[SWITCHBOX_10_4:.*]] = aie.switchbox(%[[TILE_10_4]]) { // CHECK: } // CHECK: %[[SWITCHBOX_11_1:.*]] = aie.switchbox(%[[TILE_11_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_11_2:.*]] = aie.switchbox(%[[TILE_11_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_11_3:.*]] = aie.switchbox(%[[TILE_11_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_11_4:.*]] = aie.switchbox(%[[TILE_11_4]]) { // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_0:.*]] = aie.switchbox(%[[TILE_0_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_0:.*]] = aie.switchbox(%[[TILE_10_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_10_0:.*]] = aie.shim_mux(%[[TILE_10_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_11_0:.*]] = aie.switchbox(%[[TILE_11_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_11_0:.*]] = aie.shim_mux(%[[TILE_11_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_0:.*]] = aie.switchbox(%[[TILE_8_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_9_0:.*]] = aie.switchbox(%[[TILE_9_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_12_0:.*]] = aie.tile(12, 0) // CHECK: %[[SWITCHBOX_12_0:.*]] = aie.switchbox(%[[TILE_12_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_13_0:.*]] = aie.tile(13, 0) // CHECK: %[[SWITCHBOX_13_0:.*]] = aie.switchbox(%[[TILE_13_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_14_0:.*]] = aie.tile(14, 0) // CHECK: %[[SWITCHBOX_14_0:.*]] = aie.switchbox(%[[TILE_14_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_15_0:.*]] = aie.tile(15, 0) // CHECK: %[[SWITCHBOX_15_0:.*]] = aie.switchbox(%[[TILE_15_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_16_0:.*]] = aie.tile(16, 0) // CHECK: %[[SWITCHBOX_16_0:.*]] = aie.switchbox(%[[TILE_16_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_17_0:.*]] = aie.tile(17, 0) // CHECK: %[[SWITCHBOX_17_0:.*]] = aie.switchbox(%[[TILE_17_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_18_0:.*]] = aie.switchbox(%[[TILE_18_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_18_0:.*]] = aie.shim_mux(%[[TILE_18_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_19_0:.*]] = aie.switchbox(%[[TILE_19_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_19_0:.*]] = aie.shim_mux(%[[TILE_19_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -434,102 +434,102 @@ module { %tile_12_3 = aie.tile(12, 3) %tile_12_4 = aie.tile(12, 4) %switchbox_0_1 = aie.switchbox(%tile_0_1) { - aie.connect + aie.connect } %switchbox_0_2 = aie.switchbox(%tile_0_2) { - aie.connect + aie.connect } %switchbox_0_3 = aie.switchbox(%tile_0_3) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_0_4 = aie.switchbox(%tile_0_4) { } %switchbox_1_1 = aie.switchbox(%tile_1_1) { - aie.connect + aie.connect } %switchbox_1_2 = aie.switchbox(%tile_1_2) { - aie.connect + aie.connect } %switchbox_1_3 = aie.switchbox(%tile_1_3) { - aie.connect + aie.connect } %switchbox_1_4 = aie.switchbox(%tile_1_4) { - aie.connect + aie.connect } %switchbox_2_1 = aie.switchbox(%tile_2_1) { - aie.connect + aie.connect } %switchbox_2_2 = aie.switchbox(%tile_2_2) { - aie.connect + aie.connect } %switchbox_2_3 = aie.switchbox(%tile_2_3) { - aie.connect + aie.connect } %switchbox_2_4 = aie.switchbox(%tile_2_4) { - aie.connect + aie.connect } %switchbox_3_1 = aie.switchbox(%tile_3_1) { - aie.connect + aie.connect } %switchbox_3_2 = aie.switchbox(%tile_3_2) { - aie.connect + aie.connect } %switchbox_3_3 = aie.switchbox(%tile_3_3) { - aie.connect + aie.connect } %switchbox_3_4 = aie.switchbox(%tile_3_4) { } %switchbox_4_1 = aie.switchbox(%tile_4_1) { - aie.connect + aie.connect } %switchbox_4_2 = aie.switchbox(%tile_4_2) { - aie.connect + aie.connect } %switchbox_4_3 = aie.switchbox(%tile_4_3) { } %switchbox_4_4 = aie.switchbox(%tile_4_4) { } %switchbox_5_1 = aie.switchbox(%tile_5_1) { - aie.connect + aie.connect } %switchbox_5_2 = aie.switchbox(%tile_5_2) { - aie.connect + aie.connect } %switchbox_5_3 = aie.switchbox(%tile_5_3) { - aie.connect + aie.connect } %switchbox_5_4 = aie.switchbox(%tile_5_4) { } %switchbox_6_1 = aie.switchbox(%tile_6_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_6_2 = aie.switchbox(%tile_6_2) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_6_3 = aie.switchbox(%tile_6_3) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_6_4 = aie.switchbox(%tile_6_4) { } %switchbox_7_1 = aie.switchbox(%tile_7_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_7_2 = aie.switchbox(%tile_7_2) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_7_3 = aie.switchbox(%tile_7_3) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_7_4 = aie.switchbox(%tile_7_4) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_8_1 = aie.switchbox(%tile_8_1) { } @@ -540,52 +540,52 @@ module { %switchbox_8_4 = aie.switchbox(%tile_8_4) { } %switchbox_9_1 = aie.switchbox(%tile_9_1) { - aie.connect + aie.connect } %switchbox_9_2 = aie.switchbox(%tile_9_2) { - aie.connect + aie.connect } %switchbox_9_3 = aie.switchbox(%tile_9_3) { } %switchbox_9_4 = aie.switchbox(%tile_9_4) { } %switchbox_10_1 = aie.switchbox(%tile_10_1) { - aie.connect + aie.connect } %switchbox_10_2 = aie.switchbox(%tile_10_2) { - aie.connect + aie.connect } %switchbox_10_3 = aie.switchbox(%tile_10_3) { } %switchbox_10_4 = aie.switchbox(%tile_10_4) { } %switchbox_11_1 = aie.switchbox(%tile_11_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_11_2 = aie.switchbox(%tile_11_2) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_11_3 = aie.switchbox(%tile_11_3) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_11_4 = aie.switchbox(%tile_11_4) { } - aie.flow(%tile_2_0, DMA : 0, %tile_2_0, North : 0) - aie.flow(%tile_2_0, DMA : 1, %tile_6_0, North : 1) - aie.flow(%tile_3_0, DMA : 0, %tile_3_0, North : 0) - aie.flow(%tile_3_0, DMA : 1, %tile_7_0, North : 1) - aie.flow(%tile_6_0, DMA : 0, %tile_0_0, North : 0) - aie.flow(%tile_6_0, DMA : 1, %tile_4_0, North : 0) - aie.flow(%tile_7_0, DMA : 0, %tile_1_0, North : 0) - aie.flow(%tile_7_0, DMA : 1, %tile_5_0, North : 0) - aie.flow(%tile_10_0, DMA : 0, %tile_10_0, North : 0) - aie.flow(%tile_11_0, DMA : 0, %tile_11_0, North : 0) - aie.flow(%tile_18_0, DMA : 0, %tile_6_0, North : 0) - aie.flow(%tile_18_0, DMA : 1, %tile_9_0, North : 0) - aie.flow(%tile_19_0, DMA : 0, %tile_7_0, North : 0) - aie.flow(%tile_19_0, DMA : 1, %tile_11_0, North : 1) + aie.flow(%tile_2_0, DMA : 0, %tile_2_0, NORTH : 0) + aie.flow(%tile_2_0, DMA : 1, %tile_6_0, NORTH : 1) + aie.flow(%tile_3_0, DMA : 0, %tile_3_0, NORTH : 0) + aie.flow(%tile_3_0, DMA : 1, %tile_7_0, NORTH : 1) + aie.flow(%tile_6_0, DMA : 0, %tile_0_0, NORTH : 0) + aie.flow(%tile_6_0, DMA : 1, %tile_4_0, NORTH : 0) + aie.flow(%tile_7_0, DMA : 0, %tile_1_0, NORTH : 0) + aie.flow(%tile_7_0, DMA : 1, %tile_5_0, NORTH : 0) + aie.flow(%tile_10_0, DMA : 0, %tile_10_0, NORTH : 0) + aie.flow(%tile_11_0, DMA : 0, %tile_11_0, NORTH : 0) + aie.flow(%tile_18_0, DMA : 0, %tile_6_0, NORTH : 0) + aie.flow(%tile_18_0, DMA : 1, %tile_9_0, NORTH : 0) + aie.flow(%tile_19_0, DMA : 0, %tile_7_0, NORTH : 0) + aie.flow(%tile_19_0, DMA : 1, %tile_11_0, NORTH : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_routed_herd_3x2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_routed_herd_3x2.mlir index bb23793dc..3bf5d867b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_routed_herd_3x2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_routed_herd_3x2.mlir @@ -154,56 +154,56 @@ // CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { // CHECK: } // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: } // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: } // CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_5:.*]] = aie.switchbox(%[[TILE_2_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_5:.*]] = aie.switchbox(%[[TILE_3_5]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { // CHECK: } // CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_4_4:.*]] = aie.switchbox(%[[TILE_4_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { // CHECK: } @@ -212,7 +212,7 @@ // CHECK: %[[SWITCHBOX_5_5:.*]] = aie.switchbox(%[[TILE_5_5]]) { // CHECK: } // CHECK: %[[SWITCHBOX_5_6:.*]] = aie.switchbox(%[[TILE_5_6]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { // CHECK: } @@ -225,32 +225,32 @@ // CHECK: %[[SWITCHBOX_6_5:.*]] = aie.switchbox(%[[TILE_6_5]]) { // CHECK: } // CHECK: %[[SWITCHBOX_6_6:.*]] = aie.switchbox(%[[TILE_6_6]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { // CHECK: } // CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { // CHECK: } // CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_5:.*]] = aie.switchbox(%[[TILE_7_5]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_6:.*]] = aie.switchbox(%[[TILE_7_6]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_1:.*]] = aie.switchbox(%[[TILE_8_1]]) { // CHECK: } // CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { // CHECK: } // CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { // CHECK: } @@ -259,18 +259,18 @@ // CHECK: %[[SWITCHBOX_9_2:.*]] = aie.switchbox(%[[TILE_9_2]]) { // CHECK: } // CHECK: %[[SWITCHBOX_9_3:.*]] = aie.switchbox(%[[TILE_9_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_9_4:.*]] = aie.switchbox(%[[TILE_9_4]]) { // CHECK: } // CHECK: %[[SWITCHBOX_10_1:.*]] = aie.switchbox(%[[TILE_10_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_2:.*]] = aie.switchbox(%[[TILE_10_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_3:.*]] = aie.switchbox(%[[TILE_10_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_4:.*]] = aie.switchbox(%[[TILE_10_4]]) { // CHECK: } @@ -291,110 +291,110 @@ // CHECK: %[[SWITCHBOX_12_4:.*]] = aie.switchbox(%[[TILE_12_4]]) { // CHECK: } // CHECK: %[[SWITCHBOX_12_5:.*]] = aie.switchbox(%[[TILE_12_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_13_1:.*]] = aie.switchbox(%[[TILE_13_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_13_2:.*]] = aie.switchbox(%[[TILE_13_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_13_3:.*]] = aie.switchbox(%[[TILE_13_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_13_4:.*]] = aie.switchbox(%[[TILE_13_4]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_13_5:.*]] = aie.switchbox(%[[TILE_13_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_4_5:.*]] = aie.switchbox(%[[TILE_4_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_0:.*]] = aie.switchbox(%[[TILE_10_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_10_0:.*]] = aie.shim_mux(%[[TILE_10_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_4_6:.*]] = aie.switchbox(%[[TILE_4_6]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_11_0:.*]] = aie.switchbox(%[[TILE_11_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_11_0:.*]] = aie.shim_mux(%[[TILE_11_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_12_0:.*]] = aie.tile(12, 0) // CHECK: %[[SWITCHBOX_12_0:.*]] = aie.switchbox(%[[TILE_12_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_13_0:.*]] = aie.switchbox(%[[TILE_13_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_14_2:.*]] = aie.switchbox(%[[TILE_14_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_14_3:.*]] = aie.switchbox(%[[TILE_14_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_14_4:.*]] = aie.switchbox(%[[TILE_14_4]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_14_5:.*]] = aie.switchbox(%[[TILE_14_5]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_15_2:.*]] = aie.tile(15, 2) // CHECK: %[[SWITCHBOX_15_2:.*]] = aie.switchbox(%[[TILE_15_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_16_2:.*]] = aie.tile(16, 2) // CHECK: %[[SWITCHBOX_16_2:.*]] = aie.switchbox(%[[TILE_16_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_17_0:.*]] = aie.tile(17, 0) // CHECK: %[[SWITCHBOX_17_0:.*]] = aie.switchbox(%[[TILE_17_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_17_1:.*]] = aie.tile(17, 1) // CHECK: %[[SWITCHBOX_17_1:.*]] = aie.switchbox(%[[TILE_17_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_17_2:.*]] = aie.tile(17, 2) // CHECK: %[[SWITCHBOX_17_2:.*]] = aie.switchbox(%[[TILE_17_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_18_0:.*]] = aie.switchbox(%[[TILE_18_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_18_0:.*]] = aie.shim_mux(%[[TILE_18_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -558,27 +558,27 @@ module { %switchbox_2_3 = aie.switchbox(%tile_2_3) { } %switchbox_2_4 = aie.switchbox(%tile_2_4) { - aie.connect + aie.connect } %switchbox_2_5 = aie.switchbox(%tile_2_5) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_3_1 = aie.switchbox(%tile_3_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_3_2 = aie.switchbox(%tile_3_2) { - aie.connect + aie.connect } %switchbox_3_3 = aie.switchbox(%tile_3_3) { - aie.connect + aie.connect } %switchbox_3_4 = aie.switchbox(%tile_3_4) { - aie.connect + aie.connect } %switchbox_3_5 = aie.switchbox(%tile_3_5) { - aie.connect + aie.connect } %switchbox_4_1 = aie.switchbox(%tile_4_1) { } @@ -599,7 +599,7 @@ module { %switchbox_5_5 = aie.switchbox(%tile_5_5) { } %switchbox_5_6 = aie.switchbox(%tile_5_6) { - aie.connect + aie.connect } %switchbox_6_1 = aie.switchbox(%tile_6_1) { } @@ -612,32 +612,32 @@ module { %switchbox_6_5 = aie.switchbox(%tile_6_5) { } %switchbox_6_6 = aie.switchbox(%tile_6_6) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_7_1 = aie.switchbox(%tile_7_1) { } %switchbox_7_2 = aie.switchbox(%tile_7_2) { } %switchbox_7_3 = aie.switchbox(%tile_7_3) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_7_4 = aie.switchbox(%tile_7_4) { - aie.connect + aie.connect } %switchbox_7_5 = aie.switchbox(%tile_7_5) { - aie.connect + aie.connect } %switchbox_7_6 = aie.switchbox(%tile_7_6) { - aie.connect + aie.connect } %switchbox_8_1 = aie.switchbox(%tile_8_1) { } %switchbox_8_2 = aie.switchbox(%tile_8_2) { } %switchbox_8_3 = aie.switchbox(%tile_8_3) { - aie.connect + aie.connect } %switchbox_8_4 = aie.switchbox(%tile_8_4) { } @@ -674,31 +674,31 @@ module { %switchbox_12_4 = aie.switchbox(%tile_12_4) { } %switchbox_12_5 = aie.switchbox(%tile_12_5) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_13_1 = aie.switchbox(%tile_13_1) { - aie.connect + aie.connect } %switchbox_13_2 = aie.switchbox(%tile_13_2) { - aie.connect + aie.connect } %switchbox_13_3 = aie.switchbox(%tile_13_3) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_13_4 = aie.switchbox(%tile_13_4) { - aie.connect + aie.connect } %switchbox_13_5 = aie.switchbox(%tile_13_5) { - aie.connect - aie.connect - } - aie.flow(%tile_3_0, DMA : 0, %tile_3_0, North : 0) - aie.flow(%tile_4_5, West : 0, %tile_6_0, DMA : 0) - aie.flow(%tile_10_0, DMA : 0, %tile_9_3, West : 0) - aie.flow(%tile_4_6, East : 0, %tile_2_0, DMA : 0) - aie.flow(%tile_11_0, DMA : 0, %tile_13_0, North : 0) - aie.flow(%tile_14_5, West : 0, %tile_18_0, DMA : 0) + aie.connect + aie.connect + } + aie.flow(%tile_3_0, DMA : 0, %tile_3_0, NORTH : 0) + aie.flow(%tile_4_5, WEST : 0, %tile_6_0, DMA : 0) + aie.flow(%tile_10_0, DMA : 0, %tile_9_3, WEST : 0) + aie.flow(%tile_4_6, EAST : 0, %tile_2_0, DMA : 0) + aie.flow(%tile_11_0, DMA : 0, %tile_13_0, NORTH : 0) + aie.flow(%tile_14_5, WEST : 0, %tile_18_0, DMA : 0) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_simple.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_simple.mlir index 833fc77e7..20c7ddfbf 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_simple.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_simple.mlir @@ -6,17 +6,17 @@ // CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) // CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) // CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: aie.packet_flow(16) { -// CHECK: aie.packet_source<%[[TILE_0_1]], Core : 0> -// CHECK: aie.packet_dest<%[[TILE_1_2]], Core : 0> +// CHECK: aie.packet_source<%[[TILE_0_1]], CORE : 0> +// CHECK: aie.packet_dest<%[[TILE_1_2]], CORE : 0> // CHECK: aie.packet_dest<%[[TILE_0_2]], DMA : 1> // CHECK: } // CHECK: } @@ -26,10 +26,10 @@ module { %01 = aie.tile(0, 1) %12 = aie.tile(1, 2) %02 = aie.tile(0, 2) - aie.flow(%01, DMA : 0, %12, Core : 1) + aie.flow(%01, DMA : 0, %12, CORE : 1) aie.packet_flow(0x10) { - aie.packet_source < %01, Core : 0> - aie.packet_dest < %12, Core : 0> + aie.packet_source < %01, CORE : 0> + aie.packet_dest < %12, CORE : 0> aie.packet_dest < %02, DMA : 1> } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_simple2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_simple2.mlir index 9db838065..fa93123d7 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_simple2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_simple2.mlir @@ -6,13 +6,13 @@ // CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -20,6 +20,6 @@ module { aie.device(xcvc1902) { %0 = aie.tile(2, 3) %1 = aie.tile(3, 2) - aie.flow(%0, Core : 1, %1, DMA : 0) + aie.flow(%0, CORE : 1, %1, DMA : 0) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_simple_flows.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_simple_flows.mlir index 8b98d04cd..1e674a31e 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_simple_flows.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_simple_flows.mlir @@ -5,13 +5,13 @@ // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -19,8 +19,8 @@ module { aie.device(xcvc1902) { %t23 = aie.tile(2, 3) %t22 = aie.tile(2, 2) - aie.flow(%t23, Core : 0, %t22, Core : 1) - aie.flow(%t22, Core : 0, %t22, Core : 0) - aie.flow(%t22, Core : 1, %t23, Core : 1) + aie.flow(%t23, CORE : 0, %t22, CORE : 1) + aie.flow(%t22, CORE : 0, %t22, CORE : 0) + aie.flow(%t22, CORE : 1, %t23, CORE : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_simple_flows2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_simple_flows2.mlir index 524443a6e..3ed0acc32 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_simple_flows2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_simple_flows2.mlir @@ -6,18 +6,18 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -26,7 +26,7 @@ module { %t23 = aie.tile(2, 3) %t22 = aie.tile(2, 2) %t11 = aie.tile(1, 1) - aie.flow(%t23, Core : 0, %t22, Core : 1) - aie.flow(%t22, Core : 0, %t11, Core : 0) + aie.flow(%t23, CORE : 0, %t22, CORE : 1) + aie.flow(%t22, CORE : 0, %t11, CORE : 0) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_simple_flows_shim.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_simple_flows_shim.mlir index 4ccabe4e1..102d18cf6 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_simple_flows_shim.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_simple_flows_shim.mlir @@ -5,13 +5,13 @@ // CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } @@ -19,7 +19,7 @@ module { aie.device(xcvc1902) { %t20 = aie.tile(2, 0) %t21 = aie.tile(2, 1) - aie.flow(%t21, Core : 0, %t20, DMA : 1) + aie.flow(%t21, CORE : 0, %t20, DMA : 1) } } @@ -29,16 +29,16 @@ module { // CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) // CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/unit_vecmul_4x4.mlir b/compiler/plugins/target/AMD-AIE/aie/test/unit_vecmul_4x4.mlir index 936eb6a73..3412f6a1c 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/unit_vecmul_4x4.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/unit_vecmul_4x4.mlir @@ -859,1452 +859,1452 @@ // CHECK: cf.br ^bb1 // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) // CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) // CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) // CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) // CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) // CHECK: %[[SWITCHBOX_8_0:.*]] = aie.switchbox(%[[TILE_8_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_9_0:.*]] = aie.tile(9, 0) // CHECK: %[[SWITCHBOX_9_0:.*]] = aie.switchbox(%[[TILE_9_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_9_1:.*]] = aie.tile(9, 1) // CHECK: %[[SWITCHBOX_9_1:.*]] = aie.switchbox(%[[TILE_9_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_9_2:.*]] = aie.switchbox(%[[TILE_9_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_0:.*]] = aie.switchbox(%[[TILE_10_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_1:.*]] = aie.switchbox(%[[TILE_10_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_2:.*]] = aie.switchbox(%[[TILE_10_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_8_1:.*]] = aie.tile(8, 1) // CHECK: %[[SWITCHBOX_8_1:.*]] = aie.switchbox(%[[TILE_8_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_10_0:.*]] = aie.shim_mux(%[[TILE_10_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_9_3:.*]] = aie.switchbox(%[[TILE_9_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_11_0:.*]] = aie.switchbox(%[[TILE_11_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_11_0:.*]] = aie.shim_mux(%[[TILE_11_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_3:.*]] = aie.switchbox(%[[TILE_10_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_12_0:.*]] = aie.tile(12, 0) // CHECK: %[[SWITCHBOX_12_0:.*]] = aie.switchbox(%[[TILE_12_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_13_0:.*]] = aie.tile(13, 0) // CHECK: %[[SWITCHBOX_13_0:.*]] = aie.switchbox(%[[TILE_13_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_14_0:.*]] = aie.tile(14, 0) // CHECK: %[[SWITCHBOX_14_0:.*]] = aie.switchbox(%[[TILE_14_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_15_0:.*]] = aie.tile(15, 0) // CHECK: %[[SWITCHBOX_15_0:.*]] = aie.switchbox(%[[TILE_15_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_16_0:.*]] = aie.tile(16, 0) // CHECK: %[[SWITCHBOX_16_0:.*]] = aie.switchbox(%[[TILE_16_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_17_0:.*]] = aie.tile(17, 0) // CHECK: %[[SWITCHBOX_17_0:.*]] = aie.switchbox(%[[TILE_17_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_18_0:.*]] = aie.switchbox(%[[TILE_18_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_18_0:.*]] = aie.shim_mux(%[[TILE_18_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_11_1:.*]] = aie.switchbox(%[[TILE_11_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_11_2:.*]] = aie.switchbox(%[[TILE_11_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_11_3:.*]] = aie.tile(11, 3) // CHECK: %[[SWITCHBOX_11_3:.*]] = aie.switchbox(%[[TILE_11_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_19_0:.*]] = aie.switchbox(%[[TILE_19_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_19_0:.*]] = aie.shim_mux(%[[TILE_19_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_12_1:.*]] = aie.tile(12, 1) // CHECK: %[[SWITCHBOX_12_1:.*]] = aie.switchbox(%[[TILE_12_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_13_1:.*]] = aie.tile(13, 1) // CHECK: %[[SWITCHBOX_13_1:.*]] = aie.switchbox(%[[TILE_13_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_14_1:.*]] = aie.tile(14, 1) // CHECK: %[[SWITCHBOX_14_1:.*]] = aie.switchbox(%[[TILE_14_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_15_1:.*]] = aie.tile(15, 1) // CHECK: %[[SWITCHBOX_15_1:.*]] = aie.switchbox(%[[TILE_15_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_16_1:.*]] = aie.tile(16, 1) // CHECK: %[[SWITCHBOX_16_1:.*]] = aie.switchbox(%[[TILE_16_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_17_1:.*]] = aie.tile(17, 1) // CHECK: %[[SWITCHBOX_17_1:.*]] = aie.switchbox(%[[TILE_17_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_18_1:.*]] = aie.switchbox(%[[TILE_18_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_20_0:.*]] = aie.tile(20, 0) // CHECK: %[[SWITCHBOX_20_0:.*]] = aie.switchbox(%[[TILE_20_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_21_0:.*]] = aie.tile(21, 0) // CHECK: %[[SWITCHBOX_21_0:.*]] = aie.switchbox(%[[TILE_21_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_22_0:.*]] = aie.tile(22, 0) // CHECK: %[[SWITCHBOX_22_0:.*]] = aie.switchbox(%[[TILE_22_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_23_0:.*]] = aie.tile(23, 0) // CHECK: %[[SWITCHBOX_23_0:.*]] = aie.switchbox(%[[TILE_23_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_24_0:.*]] = aie.tile(24, 0) // CHECK: %[[SWITCHBOX_24_0:.*]] = aie.switchbox(%[[TILE_24_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_25_0:.*]] = aie.tile(25, 0) // CHECK: %[[SWITCHBOX_25_0:.*]] = aie.switchbox(%[[TILE_25_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_26_0:.*]] = aie.switchbox(%[[TILE_26_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_26_0:.*]] = aie.shim_mux(%[[TILE_26_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_9_4:.*]] = aie.switchbox(%[[TILE_9_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_19_1:.*]] = aie.switchbox(%[[TILE_19_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_27_0:.*]] = aie.switchbox(%[[TILE_27_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_27_0:.*]] = aie.shim_mux(%[[TILE_27_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_12_2:.*]] = aie.tile(12, 2) // CHECK: %[[SWITCHBOX_12_2:.*]] = aie.switchbox(%[[TILE_12_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_13_2:.*]] = aie.tile(13, 2) // CHECK: %[[SWITCHBOX_13_2:.*]] = aie.switchbox(%[[TILE_13_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_14_2:.*]] = aie.tile(14, 2) // CHECK: %[[SWITCHBOX_14_2:.*]] = aie.switchbox(%[[TILE_14_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_15_2:.*]] = aie.tile(15, 2) // CHECK: %[[SWITCHBOX_15_2:.*]] = aie.switchbox(%[[TILE_15_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_16_2:.*]] = aie.tile(16, 2) // CHECK: %[[SWITCHBOX_16_2:.*]] = aie.switchbox(%[[TILE_16_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_17_2:.*]] = aie.tile(17, 2) // CHECK: %[[SWITCHBOX_17_2:.*]] = aie.switchbox(%[[TILE_17_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_18_2:.*]] = aie.switchbox(%[[TILE_18_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_19_2:.*]] = aie.switchbox(%[[TILE_19_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_20_1:.*]] = aie.tile(20, 1) // CHECK: %[[SWITCHBOX_20_1:.*]] = aie.switchbox(%[[TILE_20_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_20_2:.*]] = aie.tile(20, 2) // CHECK: %[[SWITCHBOX_20_2:.*]] = aie.switchbox(%[[TILE_20_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_21_1:.*]] = aie.tile(21, 1) // CHECK: %[[SWITCHBOX_21_1:.*]] = aie.switchbox(%[[TILE_21_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_22_1:.*]] = aie.tile(22, 1) // CHECK: %[[SWITCHBOX_22_1:.*]] = aie.switchbox(%[[TILE_22_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_23_1:.*]] = aie.tile(23, 1) // CHECK: %[[SWITCHBOX_23_1:.*]] = aie.switchbox(%[[TILE_23_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_24_1:.*]] = aie.tile(24, 1) // CHECK: %[[SWITCHBOX_24_1:.*]] = aie.switchbox(%[[TILE_24_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_25_1:.*]] = aie.tile(25, 1) // CHECK: %[[SWITCHBOX_25_1:.*]] = aie.switchbox(%[[TILE_25_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_26_1:.*]] = aie.switchbox(%[[TILE_26_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_28_0:.*]] = aie.tile(28, 0) // CHECK: %[[SWITCHBOX_28_0:.*]] = aie.switchbox(%[[TILE_28_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_29_0:.*]] = aie.tile(29, 0) // CHECK: %[[SWITCHBOX_29_0:.*]] = aie.switchbox(%[[TILE_29_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_30_0:.*]] = aie.tile(30, 0) // CHECK: %[[SWITCHBOX_30_0:.*]] = aie.switchbox(%[[TILE_30_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_31_0:.*]] = aie.tile(31, 0) // CHECK: %[[SWITCHBOX_31_0:.*]] = aie.switchbox(%[[TILE_31_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_32_0:.*]] = aie.tile(32, 0) // CHECK: %[[SWITCHBOX_32_0:.*]] = aie.switchbox(%[[TILE_32_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_33_0:.*]] = aie.tile(33, 0) // CHECK: %[[SWITCHBOX_33_0:.*]] = aie.switchbox(%[[TILE_33_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_34_0:.*]] = aie.switchbox(%[[TILE_34_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_34_0:.*]] = aie.shim_mux(%[[TILE_34_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_4:.*]] = aie.switchbox(%[[TILE_10_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_12_3:.*]] = aie.tile(12, 3) // CHECK: %[[SWITCHBOX_12_3:.*]] = aie.switchbox(%[[TILE_12_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_13_3:.*]] = aie.tile(13, 3) // CHECK: %[[SWITCHBOX_13_3:.*]] = aie.switchbox(%[[TILE_13_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_14_3:.*]] = aie.tile(14, 3) // CHECK: %[[SWITCHBOX_14_3:.*]] = aie.switchbox(%[[TILE_14_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_15_3:.*]] = aie.tile(15, 3) // CHECK: %[[SWITCHBOX_15_3:.*]] = aie.switchbox(%[[TILE_15_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_16_3:.*]] = aie.tile(16, 3) // CHECK: %[[SWITCHBOX_16_3:.*]] = aie.switchbox(%[[TILE_16_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_17_3:.*]] = aie.tile(17, 3) // CHECK: %[[SWITCHBOX_17_3:.*]] = aie.switchbox(%[[TILE_17_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_18_3:.*]] = aie.tile(18, 3) // CHECK: %[[SWITCHBOX_18_3:.*]] = aie.switchbox(%[[TILE_18_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_19_3:.*]] = aie.tile(19, 3) // CHECK: %[[SWITCHBOX_19_3:.*]] = aie.switchbox(%[[TILE_19_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_20_3:.*]] = aie.tile(20, 3) // CHECK: %[[SWITCHBOX_20_3:.*]] = aie.switchbox(%[[TILE_20_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_27_1:.*]] = aie.switchbox(%[[TILE_27_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_35_0:.*]] = aie.switchbox(%[[TILE_35_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_35_0:.*]] = aie.shim_mux(%[[TILE_35_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_7_5:.*]] = aie.switchbox(%[[TILE_7_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_8_5:.*]] = aie.switchbox(%[[TILE_8_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_9_5:.*]] = aie.switchbox(%[[TILE_9_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_10_5:.*]] = aie.switchbox(%[[TILE_10_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_11_5:.*]] = aie.tile(11, 5) // CHECK: %[[SWITCHBOX_11_5:.*]] = aie.switchbox(%[[TILE_11_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_12_5:.*]] = aie.tile(12, 5) // CHECK: %[[SWITCHBOX_12_5:.*]] = aie.switchbox(%[[TILE_12_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_13_5:.*]] = aie.tile(13, 5) // CHECK: %[[SWITCHBOX_13_5:.*]] = aie.switchbox(%[[TILE_13_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_14_5:.*]] = aie.tile(14, 5) // CHECK: %[[SWITCHBOX_14_5:.*]] = aie.switchbox(%[[TILE_14_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_15_4:.*]] = aie.tile(15, 4) // CHECK: %[[SWITCHBOX_15_4:.*]] = aie.switchbox(%[[TILE_15_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_15_5:.*]] = aie.tile(15, 5) // CHECK: %[[SWITCHBOX_15_5:.*]] = aie.switchbox(%[[TILE_15_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_21_3:.*]] = aie.tile(21, 3) // CHECK: %[[SWITCHBOX_21_3:.*]] = aie.switchbox(%[[TILE_21_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_22_3:.*]] = aie.tile(22, 3) // CHECK: %[[SWITCHBOX_22_3:.*]] = aie.switchbox(%[[TILE_22_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_23_3:.*]] = aie.tile(23, 3) // CHECK: %[[SWITCHBOX_23_3:.*]] = aie.switchbox(%[[TILE_23_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_24_2:.*]] = aie.tile(24, 2) // CHECK: %[[SWITCHBOX_24_2:.*]] = aie.switchbox(%[[TILE_24_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_24_3:.*]] = aie.tile(24, 3) // CHECK: %[[SWITCHBOX_24_3:.*]] = aie.switchbox(%[[TILE_24_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_25_2:.*]] = aie.tile(25, 2) // CHECK: %[[SWITCHBOX_25_2:.*]] = aie.switchbox(%[[TILE_25_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_26_2:.*]] = aie.switchbox(%[[TILE_26_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_28_1:.*]] = aie.tile(28, 1) // CHECK: %[[SWITCHBOX_28_1:.*]] = aie.switchbox(%[[TILE_28_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_29_1:.*]] = aie.tile(29, 1) // CHECK: %[[SWITCHBOX_29_1:.*]] = aie.switchbox(%[[TILE_29_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_30_1:.*]] = aie.tile(30, 1) // CHECK: %[[SWITCHBOX_30_1:.*]] = aie.switchbox(%[[TILE_30_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_31_1:.*]] = aie.tile(31, 1) // CHECK: %[[SWITCHBOX_31_1:.*]] = aie.switchbox(%[[TILE_31_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_32_1:.*]] = aie.tile(32, 1) // CHECK: %[[SWITCHBOX_32_1:.*]] = aie.switchbox(%[[TILE_32_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_33_1:.*]] = aie.tile(33, 1) // CHECK: %[[SWITCHBOX_33_1:.*]] = aie.switchbox(%[[TILE_33_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_34_1:.*]] = aie.switchbox(%[[TILE_34_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_36_0:.*]] = aie.tile(36, 0) // CHECK: %[[SWITCHBOX_36_0:.*]] = aie.switchbox(%[[TILE_36_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_37_0:.*]] = aie.tile(37, 0) // CHECK: %[[SWITCHBOX_37_0:.*]] = aie.switchbox(%[[TILE_37_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_38_0:.*]] = aie.tile(38, 0) // CHECK: %[[SWITCHBOX_38_0:.*]] = aie.switchbox(%[[TILE_38_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_39_0:.*]] = aie.tile(39, 0) // CHECK: %[[SWITCHBOX_39_0:.*]] = aie.switchbox(%[[TILE_39_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_40_0:.*]] = aie.tile(40, 0) // CHECK: %[[SWITCHBOX_40_0:.*]] = aie.switchbox(%[[TILE_40_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_41_0:.*]] = aie.tile(41, 0) // CHECK: %[[SWITCHBOX_41_0:.*]] = aie.switchbox(%[[TILE_41_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_42_0:.*]] = aie.switchbox(%[[TILE_42_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_42_0:.*]] = aie.shim_mux(%[[TILE_42_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_11_4:.*]] = aie.tile(11, 4) // CHECK: %[[SWITCHBOX_11_4:.*]] = aie.switchbox(%[[TILE_11_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_12_4:.*]] = aie.tile(12, 4) // CHECK: %[[SWITCHBOX_12_4:.*]] = aie.switchbox(%[[TILE_12_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_13_4:.*]] = aie.tile(13, 4) // CHECK: %[[SWITCHBOX_13_4:.*]] = aie.switchbox(%[[TILE_13_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_14_4:.*]] = aie.tile(14, 4) // CHECK: %[[SWITCHBOX_14_4:.*]] = aie.switchbox(%[[TILE_14_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_16_4:.*]] = aie.tile(16, 4) // CHECK: %[[SWITCHBOX_16_4:.*]] = aie.switchbox(%[[TILE_16_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_17_4:.*]] = aie.tile(17, 4) // CHECK: %[[SWITCHBOX_17_4:.*]] = aie.switchbox(%[[TILE_17_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_21_2:.*]] = aie.tile(21, 2) // CHECK: %[[SWITCHBOX_21_2:.*]] = aie.switchbox(%[[TILE_21_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_22_2:.*]] = aie.tile(22, 2) // CHECK: %[[SWITCHBOX_22_2:.*]] = aie.switchbox(%[[TILE_22_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_23_2:.*]] = aie.tile(23, 2) // CHECK: %[[SWITCHBOX_23_2:.*]] = aie.switchbox(%[[TILE_23_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_27_2:.*]] = aie.switchbox(%[[TILE_27_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_35_1:.*]] = aie.switchbox(%[[TILE_35_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_43_0:.*]] = aie.switchbox(%[[TILE_43_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_43_0:.*]] = aie.shim_mux(%[[TILE_43_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_18_4:.*]] = aie.tile(18, 4) // CHECK: %[[SWITCHBOX_18_4:.*]] = aie.switchbox(%[[TILE_18_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_19_4:.*]] = aie.tile(19, 4) // CHECK: %[[SWITCHBOX_19_4:.*]] = aie.switchbox(%[[TILE_19_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_20_4:.*]] = aie.tile(20, 4) // CHECK: %[[SWITCHBOX_20_4:.*]] = aie.switchbox(%[[TILE_20_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_25_3:.*]] = aie.tile(25, 3) // CHECK: %[[SWITCHBOX_25_3:.*]] = aie.switchbox(%[[TILE_25_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_26_3:.*]] = aie.tile(26, 3) // CHECK: %[[SWITCHBOX_26_3:.*]] = aie.switchbox(%[[TILE_26_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_28_2:.*]] = aie.tile(28, 2) // CHECK: %[[SWITCHBOX_28_2:.*]] = aie.switchbox(%[[TILE_28_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_29_2:.*]] = aie.tile(29, 2) // CHECK: %[[SWITCHBOX_29_2:.*]] = aie.switchbox(%[[TILE_29_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_30_2:.*]] = aie.tile(30, 2) // CHECK: %[[SWITCHBOX_30_2:.*]] = aie.switchbox(%[[TILE_30_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_31_2:.*]] = aie.tile(31, 2) // CHECK: %[[SWITCHBOX_31_2:.*]] = aie.switchbox(%[[TILE_31_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_32_2:.*]] = aie.tile(32, 2) // CHECK: %[[SWITCHBOX_32_2:.*]] = aie.switchbox(%[[TILE_32_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_33_2:.*]] = aie.tile(33, 2) // CHECK: %[[SWITCHBOX_33_2:.*]] = aie.switchbox(%[[TILE_33_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_34_2:.*]] = aie.switchbox(%[[TILE_34_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_35_2:.*]] = aie.switchbox(%[[TILE_35_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_36_2:.*]] = aie.tile(36, 2) // CHECK: %[[SWITCHBOX_36_2:.*]] = aie.switchbox(%[[TILE_36_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_37_2:.*]] = aie.tile(37, 2) // CHECK: %[[SWITCHBOX_37_2:.*]] = aie.switchbox(%[[TILE_37_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_38_2:.*]] = aie.tile(38, 2) // CHECK: %[[SWITCHBOX_38_2:.*]] = aie.switchbox(%[[TILE_38_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_39_2:.*]] = aie.tile(39, 2) // CHECK: %[[SWITCHBOX_39_2:.*]] = aie.switchbox(%[[TILE_39_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_40_2:.*]] = aie.tile(40, 2) // CHECK: %[[SWITCHBOX_40_2:.*]] = aie.switchbox(%[[TILE_40_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_41_1:.*]] = aie.tile(41, 1) // CHECK: %[[SWITCHBOX_41_1:.*]] = aie.switchbox(%[[TILE_41_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_41_2:.*]] = aie.tile(41, 2) // CHECK: %[[SWITCHBOX_41_2:.*]] = aie.switchbox(%[[TILE_41_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_42_1:.*]] = aie.switchbox(%[[TILE_42_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_44_0:.*]] = aie.tile(44, 0) // CHECK: %[[SWITCHBOX_44_0:.*]] = aie.switchbox(%[[TILE_44_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_45_0:.*]] = aie.tile(45, 0) // CHECK: %[[SWITCHBOX_45_0:.*]] = aie.switchbox(%[[TILE_45_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_46_0:.*]] = aie.switchbox(%[[TILE_46_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_46_0:.*]] = aie.shim_mux(%[[TILE_46_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_16_5:.*]] = aie.tile(16, 5) // CHECK: %[[SWITCHBOX_16_5:.*]] = aie.switchbox(%[[TILE_16_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_17_5:.*]] = aie.tile(17, 5) // CHECK: %[[SWITCHBOX_17_5:.*]] = aie.switchbox(%[[TILE_17_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_18_5:.*]] = aie.tile(18, 5) // CHECK: %[[SWITCHBOX_18_5:.*]] = aie.switchbox(%[[TILE_18_5]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_21_4:.*]] = aie.tile(21, 4) // CHECK: %[[SWITCHBOX_21_4:.*]] = aie.switchbox(%[[TILE_21_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_22_4:.*]] = aie.tile(22, 4) // CHECK: %[[SWITCHBOX_22_4:.*]] = aie.switchbox(%[[TILE_22_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_23_4:.*]] = aie.tile(23, 4) // CHECK: %[[SWITCHBOX_23_4:.*]] = aie.switchbox(%[[TILE_23_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_24_4:.*]] = aie.tile(24, 4) // CHECK: %[[SWITCHBOX_24_4:.*]] = aie.switchbox(%[[TILE_24_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_25_4:.*]] = aie.tile(25, 4) // CHECK: %[[SWITCHBOX_25_4:.*]] = aie.switchbox(%[[TILE_25_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_26_4:.*]] = aie.tile(26, 4) // CHECK: %[[SWITCHBOX_26_4:.*]] = aie.switchbox(%[[TILE_26_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_27_4:.*]] = aie.tile(27, 4) // CHECK: %[[SWITCHBOX_27_4:.*]] = aie.switchbox(%[[TILE_27_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_28_4:.*]] = aie.tile(28, 4) // CHECK: %[[SWITCHBOX_28_4:.*]] = aie.switchbox(%[[TILE_28_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_29_4:.*]] = aie.tile(29, 4) // CHECK: %[[SWITCHBOX_29_4:.*]] = aie.switchbox(%[[TILE_29_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_30_4:.*]] = aie.tile(30, 4) // CHECK: %[[SWITCHBOX_30_4:.*]] = aie.switchbox(%[[TILE_30_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_31_4:.*]] = aie.tile(31, 4) // CHECK: %[[SWITCHBOX_31_4:.*]] = aie.switchbox(%[[TILE_31_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_32_4:.*]] = aie.tile(32, 4) // CHECK: %[[SWITCHBOX_32_4:.*]] = aie.switchbox(%[[TILE_32_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_33_4:.*]] = aie.tile(33, 4) // CHECK: %[[SWITCHBOX_33_4:.*]] = aie.switchbox(%[[TILE_33_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_34_4:.*]] = aie.tile(34, 4) // CHECK: %[[SWITCHBOX_34_4:.*]] = aie.switchbox(%[[TILE_34_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_35_4:.*]] = aie.tile(35, 4) // CHECK: %[[SWITCHBOX_35_4:.*]] = aie.switchbox(%[[TILE_35_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_36_4:.*]] = aie.tile(36, 4) // CHECK: %[[SWITCHBOX_36_4:.*]] = aie.switchbox(%[[TILE_36_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_37_4:.*]] = aie.tile(37, 4) // CHECK: %[[SWITCHBOX_37_4:.*]] = aie.switchbox(%[[TILE_37_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_38_4:.*]] = aie.tile(38, 4) // CHECK: %[[SWITCHBOX_38_4:.*]] = aie.switchbox(%[[TILE_38_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_39_4:.*]] = aie.tile(39, 4) // CHECK: %[[SWITCHBOX_39_4:.*]] = aie.switchbox(%[[TILE_39_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_40_4:.*]] = aie.tile(40, 4) // CHECK: %[[SWITCHBOX_40_4:.*]] = aie.switchbox(%[[TILE_40_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_41_4:.*]] = aie.tile(41, 4) // CHECK: %[[SWITCHBOX_41_4:.*]] = aie.switchbox(%[[TILE_41_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_42_3:.*]] = aie.tile(42, 3) // CHECK: %[[SWITCHBOX_42_3:.*]] = aie.switchbox(%[[TILE_42_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_42_4:.*]] = aie.tile(42, 4) // CHECK: %[[SWITCHBOX_42_4:.*]] = aie.switchbox(%[[TILE_42_4]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_43_3:.*]] = aie.tile(43, 3) // CHECK: %[[SWITCHBOX_43_3:.*]] = aie.switchbox(%[[TILE_43_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_44_3:.*]] = aie.tile(44, 3) // CHECK: %[[SWITCHBOX_44_3:.*]] = aie.switchbox(%[[TILE_44_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_45_2:.*]] = aie.tile(45, 2) // CHECK: %[[SWITCHBOX_45_2:.*]] = aie.switchbox(%[[TILE_45_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[TILE_45_3:.*]] = aie.tile(45, 3) // CHECK: %[[SWITCHBOX_45_3:.*]] = aie.switchbox(%[[TILE_45_3]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_46_1:.*]] = aie.switchbox(%[[TILE_46_1]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_46_2:.*]] = aie.switchbox(%[[TILE_46_2]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_47_0:.*]] = aie.switchbox(%[[TILE_47_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_47_0:.*]] = aie.shim_mux(%[[TILE_47_0]]) { -// CHECK-DAG: aie.connect -// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect +// CHECK-DAG: aie.connect // CHECK: } // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/user_assigned.mlir b/compiler/plugins/target/AMD-AIE/aie/test/user_assigned.mlir index 6272e334b..a95df956b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/user_assigned.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/user_assigned.mlir @@ -5,9 +5,9 @@ // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[IN:.*]] = aie.buffer(%[[TILE_2_1]]) {address = 8192 : i32, sym_name = "in"} : memref<16xi32> // CHECK: %[[OUT:.*]] = aie.buffer(%[[TILE_2_1]]) {address = 1824 : i32, sym_name = "out"} : memref<16xi32> -// CHECK: %[[LOCK_2_1:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 1 : i32} +// CHECK: %[[LOCK_2_1:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 1 : i8} // CHECK: %[[LOCK_2_1_0:.*]] = aie.lock(%[[TILE_2_1]], 1) -// CHECK: %[[LOCK_2_1_1:.*]] = aie.lock(%[[TILE_2_1]], 2) {init = 1 : i32} +// CHECK: %[[LOCK_2_1_1:.*]] = aie.lock(%[[TILE_2_1]], 2) {init = 1 : i8} // CHECK: %[[LOCK_2_1_2:.*]] = aie.lock(%[[TILE_2_1]], 3) // CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { // CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb4, ^bb1) @@ -47,9 +47,9 @@ module @aie_module { %t01 = aie.tile(2, 1) %buf01_0 = aie.buffer(%t01) { address = 8192 : i32, sym_name = "in" } : memref<16xi32> %buf01_1 = aie.buffer(%t01) { address = 1824 : i32, sym_name = "out" } : memref<16xi32> - %l01_0 = aie.lock(%t01, 0) { init = 1 : i32 } + %l01_0 = aie.lock(%t01, 0) { init = 1 : i8 } %l01_1 = aie.lock(%t01, 1) - %l01_2 = aie.lock(%t01, 2) { init = 1 : i32 } + %l01_2 = aie.lock(%t01, 2) { init = 1 : i8 } %l01_3 = aie.lock(%t01, 3) %m01 = aie.memtile_dma(%t01) { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^dma0) diff --git a/compiler/plugins/target/AMD-AIE/air/CMakeLists.txt b/compiler/plugins/target/AMD-AIE/air/CMakeLists.txt index 3281a2acd..61659076d 100644 --- a/compiler/plugins/target/AMD-AIE/air/CMakeLists.txt +++ b/compiler/plugins/target/AMD-AIE/air/CMakeLists.txt @@ -21,6 +21,22 @@ iree_cc_library( # AIR Dialect ############################################################################### +function(replace_string_in_file _file _match_string _replace_string) + if(NOT (EXISTS ${_file})) + message(FATAL_ERROR "file ${_file} does not exist") + endif() + file(READ "${_file}" _file_contents) + if(_file_contents STREQUAL "") + message(FATAL_ERROR "empty file contents for ${_file}") + endif() + string(REPLACE "${_match_string}" "${_replace_string}" _file_contents "${_file_contents}") + if(_file_contents STREQUAL "") + message(FATAL_ERROR "empty replacement contents for ${_file}") + endif() + file(WRITE "${_file}" "${_file_contents}") +endfunction() + + iree_cc_library( NAME AIRDialectIR @@ -164,6 +180,49 @@ iree_cc_library( MLIRTransforms ) +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/include/air/Conversion/PassDetail.h + "aie/Dialect/AIEX/IR" "aie") +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/include/air/Conversion/AIRToAIESchedulingUtils.h + "aie/Dialect/AIE/IR" "aie") +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/lib/Conversion/AIRToAIEPass.cpp + "aie/Dialect/AIE/IR" "aie") +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/lib/Conversion/AIRLoweringPass.cpp + "aie/Dialect/AIE/IR" "aie") +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/lib/Conversion/AIRRtToNpuPass.cpp + "aie/Dialect/AIEX/IR" "aie") + +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/lib/Conversion/AIRToAIESchedulingUtils.cpp + "AIE::WireBundle::DMA" "mlir::iree_compiler::AMDAIE::StrmSwPortType::DMA") +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/lib/Conversion/AIRToAIEPass.cpp + "AIE::AIETargetModel" "mlir::iree_compiler::AMDAIE::AMDAIEDeviceModel") +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/lib/Conversion/AIRToAIEPass.cpp + "/*initial_value*/ nullptr," "") +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/lib/Conversion/AIRToAIEPass.cpp + "AIE::TileID" "mlir::iree_compiler::AMDAIE::TileLoc") +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/lib/Conversion/AIRToAIEPass.cpp + "AIE::WireBundle::Trace" "mlir::iree_compiler::AMDAIE::StrmSwPortType::TRACE") +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/lib/Conversion/AIRToAIEPass.cpp + "memtileToSizeMap[t] = m.getTargetModel().getMemTileSize()" + "memtileToSizeMap[t] = m.getTargetModel().getMemTileSize(t.getCol(), t.getRow())") + +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/lib/Conversion/AIRRtToNpuPass.cpp + "&target_model" "target_model") +replace_string_in_file( + ${IREE_MLIR_AIR_SOURCE_DIR}/lib/Conversion/AIRRtToNpuPass.cpp + "AIE::WireBundle::Trace" "mlir::iree_compiler::AMDAIE::StrmSwPortType::TRACE") + iree_cc_library( NAME AIRConversionPasses diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/IR/AMDAIEOps.cpp b/compiler/plugins/target/AMD-AIE/iree-amd-aie/IR/AMDAIEOps.cpp index dd812930c..1c6e4866e 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/IR/AMDAIEOps.cpp +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/IR/AMDAIEOps.cpp @@ -373,10 +373,10 @@ void LogicalObjectFifoFromMemrefOp::build( SmallVector tiles; tiles.reserve(tileLocations.size()); for (auto [column, row] : tileLocations) { - auto colIndex = b.create(b.getUnknownLoc(), column); - auto rowIndex = b.create(b.getUnknownLoc(), row); + auto getCol = b.create(b.getUnknownLoc(), column); + auto getRow = b.create(b.getUnknownLoc(), row); auto tileOp = - b.create(b.getUnknownLoc(), colIndex, rowIndex); + b.create(b.getUnknownLoc(), getCol, getRow); tiles.push_back(tileOp.getResult()); } // For deterministic order. diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/PluginRegistration.cpp b/compiler/plugins/target/AMD-AIE/iree-amd-aie/PluginRegistration.cpp index 134f3e30f..2ef29d294 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/PluginRegistration.cpp +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/PluginRegistration.cpp @@ -4,8 +4,8 @@ // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -#include "aie/Dialect/AIE/IR/AIEDialect.h" -#include "aie/Dialect/AIEX/IR/AIEXDialect.h" +#include "aie/AIEDialect.h" +#include "aie/AIEXDialect.h" #include "aie/Passes.h" #include "aievec/AIEVecDialect.h" #include "aievec/Passes.h" diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AIETarget.cpp b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AIETarget.cpp index a9a1175e7..b48afaac1 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AIETarget.cpp +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AIETarget.cpp @@ -9,8 +9,8 @@ #include #include "XCLBinGen.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" -#include "aie/Dialect/AIEX/IR/AIEXDialect.h" +#include "aie/AIEDialect.h" +#include "aie/AIEXDialect.h" #include "aievec/AIEVecDialect.h" #include "aievec/Passes.h" #include "aievec/XLLVMDialect.h" diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AIETarget.h b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AIETarget.h index 2e1ae9d79..cb5ccbae8 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AIETarget.h +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AIETarget.h @@ -9,6 +9,7 @@ #include +#include "aie/AIEDialect.h" #include "iree/compiler/Dialect/HAL/Target/TargetBackend.h" #include "iree/compiler/Dialect/HAL/Target/TargetDevice.h" #include "iree/compiler/Utils/OptionUtils.h" diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AIETargetDirect.h b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AIETargetDirect.h deleted file mode 100644 index ebbd07668..000000000 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AIETargetDirect.h +++ /dev/null @@ -1,24 +0,0 @@ -// Copyright 2024 The IREE Authors -// -// Licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception - -#ifndef IREE_AMD_AIE_TARGET_DIRECT_AIETARGET_H_ -#define IREE_AMD_AIE_TARGET_DIRECT_AIETARGET_H_ - -#include - -#include "iree-amd-aie/Target/AIETarget.h" -#include "iree/compiler/Dialect/HAL/Target/TargetBackend.h" -#include "iree/compiler/Dialect/HAL/Target/TargetDevice.h" -#include "iree/compiler/Utils/OptionUtils.h" - -namespace mlir::iree_compiler::AMDAIE { - -std::shared_ptr createBackendDirect( - const AMDAIEOptions &options); - -} // namespace mlir::iree_compiler::AMDAIE - -#endif // IREE_AMD_AIE_TARGET_DIRECT_AIETARGET_H_ diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargetBCF.cpp b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargetBCF.cpp index 249dbe7e4..48fc13527 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargetBCF.cpp +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargetBCF.cpp @@ -5,8 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception #include "AMDAIETargets.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" -#include "aie/Passes.h" +#include "aie/AIEDialect.h" #include "llvm/ADT/StringExtras.h" #include "llvm/IR/Module.h" @@ -17,6 +16,7 @@ using namespace xilinx::AIE; std::string utohexstr(uint32_t u) { return "0x" + llvm::utohexstr(u); } namespace mlir::iree_compiler::AMDAIE { + LogicalResult AIETranslateToBCF(ModuleOp module, raw_ostream &output, int tileCol, int tileRow) { DenseMap tiles; @@ -27,7 +27,7 @@ LogicalResult AIETranslateToBCF(ModuleOp module, raw_ostream &output, DeviceOp deviceOp = *(module.getOps().begin()); collectTiles(deviceOp, tiles); - ::collectBuffers(deviceOp, buffers); + collectBuffers(deviceOp, buffers); // _entry_point _main_init // _symbol _main _after _main_init @@ -43,8 +43,8 @@ LogicalResult AIETranslateToBCF(ModuleOp module, raw_ostream &output, AMDAIEDeviceModel deviceModel = getDeviceModel(static_cast(deviceOp.getDevice())); for (auto tile : deviceOp.getOps()) - if (tile.colIndex() == tileCol && tile.rowIndex() == tileRow) { - TileLoc srcCoord = {tile.colIndex(), tile.rowIndex()}; + if (tile.getCol() == tileCol && tile.getRow() == tileRow) { + TileLoc srcCoord = {tile.getCol(), tile.getRow()}; std::string corefunc = std::string("core_") + std::to_string(tile.getCol()) + "_" + @@ -57,7 +57,7 @@ LogicalResult AIETranslateToBCF(ModuleOp module, raw_ostream &output, << " // Don't put data in code memory\n"; int stacksize = 0; - if (auto core = tile.getCoreOp()) stacksize = core.getStackSize(); + if (auto core = getCoreOp(tile)) stacksize = core.getStackSize(); output << "_stack DM_stack " << utohexstr(deviceModel.getMemInternalBaseAddress()) << " " << utohexstr(stacksize) << " // stack for core\n"; @@ -78,21 +78,15 @@ LogicalResult AIETranslateToBCF(ModuleOp module, raw_ostream &output, // remaining buffer) if (tiles.count(TileLoc(*tile))) { for (auto buf : buffers[tiles[TileLoc(*tile)]]) { - std::string bufName(buf.name().getValue()); - int bufferBaseAddr = getBufferBaseAddress(buf); - int numBytes = buf.getAllocationSize(); - if (buf.getInitialValue() && srcCoord == tile) { - output << "_overlay " << bufName << " " - << utohexstr(offset + bufferBaseAddr) << " // " - << numBytes << " bytes\n"; - } else { - output << "_symbol " << bufName << " " - << utohexstr(offset + bufferBaseAddr) << " " << numBytes - << '\n'; - output << "_extern " << bufName << "\n"; - output << "_reserved DMb " << utohexstr(offset + bufferBaseAddr) - << " " << numBytes << '\n'; - } + std::string bufName(name(buf).getValue()); + int bufferBaseAddr = buf.getAddress().value(); + int numBytes = getAllocationSize(buf); + output << "_symbol " << bufName << " " + << utohexstr(offset + bufferBaseAddr) << " " << numBytes + << '\n'; + output << "_extern " << bufName << "\n"; + output << "_reserved DMb " << utohexstr(offset + bufferBaseAddr) + << " " << numBytes << '\n'; output << "\n"; } } @@ -118,8 +112,8 @@ LogicalResult AIETranslateToBCF(ModuleOp module, raw_ostream &output, "the core can't see\n"; // chess's libc expects a _main not a main (despite what me_basic.c looks // like...) - output << "_resolve _main core_" << tile.getCol() << "_" << tile.getRow() - << "\n"; + output << "_resolve _main core_" << std::to_string(tile.getCol()) << "_" + << std::to_string(tile.getRow()) << "\n"; } return success(); diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargetCDODirect.cpp b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargetCDODirect.cpp index b8e7d3607..40eaa2f73 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargetCDODirect.cpp +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargetCDODirect.cpp @@ -11,8 +11,8 @@ #include #include "AMDAIETargets.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" -#include "aie/Dialect/AIE/IR/AIEEnums.h" +#include "aie/AIEDialect.h" +#include "aie/AIEEnums.h" #include "iree-amd-aie/aie_runtime/iree_aie_configure.h" #include "iree-amd-aie/aie_runtime/iree_aie_runtime.h" #include "llvm/ADT/STLExtras.h" @@ -31,8 +31,6 @@ using namespace mlir; using xilinx::AIE::AMSelOp; using xilinx::AIE::BufferOp; -using xilinx::AIE::CascadeDir; -using xilinx::AIE::ConfigureCascadeOp; using xilinx::AIE::ConnectOp; using xilinx::AIE::CoreOp; using xilinx::AIE::DeviceOp; @@ -40,17 +38,15 @@ using xilinx::AIE::DMABDOp; using xilinx::AIE::DMABDPACKETOp; using xilinx::AIE::DMAChannelDir; using xilinx::AIE::DMAStartOp; -using xilinx::AIE::Interconnect; +using xilinx::AIE::LockAction; using xilinx::AIE::LockOp; using xilinx::AIE::MasterSetOp; using xilinx::AIE::MemOp; using xilinx::AIE::MemTileDMAOp; using xilinx::AIE::PacketRuleOp; using xilinx::AIE::PacketRulesOp; -using xilinx::AIE::ShimDMAOp; using xilinx::AIE::ShimMuxOp; using xilinx::AIE::SwitchboxOp; -using xilinx::AIE::TileElement; using xilinx::AIE::TileOp; using xilinx::AIE::UseLockOp; using xilinx::AIE::WireBundle; @@ -59,50 +55,6 @@ using Path = std::filesystem::path; namespace { -mlir::iree_compiler::AMDAIE::StrmSwPortType toAMDAIEStrmT(WireBundle w) { - using mlir::iree_compiler::AMDAIE::StrmSwPortType; - switch (w) { - case WireBundle::Core: - return StrmSwPortType::CORE; - case WireBundle::DMA: - return StrmSwPortType::DMA; - case WireBundle::FIFO: - return StrmSwPortType::FIFO; - case WireBundle::South: - return StrmSwPortType::SOUTH; - case WireBundle::West: - return StrmSwPortType::WEST; - case WireBundle::North: - return StrmSwPortType::NORTH; - case WireBundle::East: - return StrmSwPortType::EAST; - case WireBundle::PLIO: - llvm::report_fatal_error("unhandled PLIO"); - case WireBundle::NOC: - return StrmSwPortType::NOC; - case WireBundle::Trace: - return StrmSwPortType::TRACE; - case WireBundle::Ctrl: - return StrmSwPortType::CTRL; - default: - llvm::report_fatal_error("unhandled WireBundle"); - } -} - -mlir::iree_compiler::AMDAIE::Cascade::Direction toDir(CascadeDir dir) { - switch (dir) { - case xilinx::AIE::CascadeDir::South: - return mlir::iree_compiler::AMDAIE::Cascade::Direction::SOUTH; - case xilinx::AIE::CascadeDir::North: - return mlir::iree_compiler::AMDAIE::Cascade::Direction::NORTH; - case xilinx::AIE::CascadeDir::West: - return mlir::iree_compiler::AMDAIE::Cascade::Direction::WEST; - case xilinx::AIE::CascadeDir::East: - return mlir::iree_compiler::AMDAIE::Cascade::Direction::EAST; - } - llvm::report_fatal_error("unhandled cascade dir"); -} - mlir::iree_compiler::AMDAIE::Lock::Action toLock(xilinx::AIE::LockAction l) { switch (l) { case xilinx::AIE::LockAction::Acquire: @@ -136,13 +88,14 @@ LogicalResult configureLocksAndBd(Block &block, const TileLoc &tileLoc, case Lock::Action::Acquire: case Lock::Action::AcquireGreaterEqual: acqEn = op.getAcqEn(); - acqLockId = lock.getLockIDValue(); - acqValue = op.getLockValue(); - if (op.acquireGE()) acqValue.value() = -acqValue.value(); + acqLockId = lock.getLockID(); + acqValue = op.getValue().value_or(1); + if (op.getAction() == LockAction::AcquireGreaterEqual) + acqValue.value() = -acqValue.value(); break; case Lock::Action::Release: - relLockId = lock.getLockIDValue(); - relValue = op.getLockValue(); + relLockId = lock.getLockID(); + relValue = op.getValue().value_or(1); break; } } @@ -168,7 +121,7 @@ LogicalResult configureLocksAndBd(Block &block, const TileLoc &tileLoc, "expected only one dma_bd_packet"); auto packetOp = *maybePacketOps.begin(); packetType = packetOp.getPacketType(); - packetID = packetOp.getPacketID(); + packetID = packetOp.getPacketId(); } BufferOp bufferOp = cast(bdOp.getBuffer().getDefiningOp()); @@ -197,8 +150,8 @@ LogicalResult configureLocksAndBd(Block &block, const TileLoc &tileLoc, *bdOp.getNextBdId())} : std::nullopt, packetType, packetID, *bufferOp.getAddress(), - bdOp.getLenInBytes(), bdOp.getOffsetInBytes(), - bdOp.getBufferElementTypeWidthInBytes(), maybeDims, + getLenInBytes(bdOp), getOffsetInBytes(bdOp), + getBufferElementTypeWidthInBytes(bdOp), maybeDims, maybePadDims))) { return failure(); } @@ -211,7 +164,7 @@ LogicalResult addAieElfsToCDO(const AMDAIEDeviceModel &deviceModel, for (auto tileOp : device.getOps()) { TileLoc tileLoc{tileOp.getCol(), tileOp.getRow()}; if (deviceModel.isShimNOCorPLTile(tileLoc.col, tileLoc.row)) continue; - if (auto coreOp = tileOp.getCoreOp()) { + if (auto coreOp = getCoreOp(tileOp)) { std::string fileName; if (auto elfFile = coreOp.getElfFile()) fileName = *elfFile; @@ -234,17 +187,18 @@ LogicalResult addInitConfigToCDO(const AMDAIEDeviceModel &deviceModel, if (deviceModel.isShimTile(tileOp.getCol(), tileOp.getRow())) { continue; } - if (auto coreOp = tileOp.getCoreOp(); + if (auto coreOp = getCoreOp(tileOp); coreOp && failed(resetUnResetCore(deviceModel, tileLoc))) { return failure(); } } // Set locks with explicit initializers - WalkResult r = device.walk([&](LockOp lockOp) { + WalkResult r; + r = device.walk([&](LockOp lockOp) { if (lockOp.getLockID() && lockOp.getInit()) { - TileLoc tileLoc = {lockOp.getTileOp().getCol(), - lockOp.getTileOp().getRow()}; + TileOp t = xilinx::AIE::getTileOp(*lockOp.getOperation()); + TileLoc tileLoc = {t.getCol(), t.getRow()}; Lock lock{tileLoc, static_cast(*lockOp.getLockID()), static_cast(*lockOp.getInit())}; if (failed(initializeLock(deviceModel, lock))) @@ -254,23 +208,23 @@ LogicalResult addInitConfigToCDO(const AMDAIEDeviceModel &deviceModel, }); if (r.wasInterrupted()) return failure(); - auto memOps = llvm::to_vector_of(device.getOps()); + auto memOps = llvm::to_vector_of(device.getOps()); llvm::append_range(memOps, device.getOps()); - llvm::append_range(memOps, device.getOps()); - for (TileElement memOp : memOps) { - TileLoc tileLoc = {memOp.getTileID().col, memOp.getTileID().row}; + for (Operation *memOp : memOps) { + TileOp t = xilinx::AIE::getTileOp(*memOp); + TileLoc tileLoc = {t.getCol(), t.getRow()}; if (deviceModel.isShimNOCorPLTile(tileLoc.col, tileLoc.row)) { continue; } // handle DMA ops separately - for (Block &block : memOp.getOperation()->getRegion(0)) { + for (Block &block : memOp->getRegion(0)) { if (block.getOps().empty()) continue; if (failed(configureLocksAndBd(block, tileLoc, deviceModel))) return failure(); } - for (Block &block : memOp.getOperation()->getRegion(0)) { + for (Block &block : memOp->getRegion(0)) { for (auto op : block.getOps()) { DMABDOp bd = *op.getDest()->getOps().begin(); int chNum = op.getChannelIndex(); @@ -286,14 +240,14 @@ LogicalResult addInitConfigToCDO(const AMDAIEDeviceModel &deviceModel, // StreamSwitch (switchbox) configuration for (auto switchboxOp : device.getOps()) { - SwitchBox swb = {switchboxOp.colIndex(), switchboxOp.rowIndex()}; + TileOp t = xilinx::AIE::getTileOp(*switchboxOp.getOperation()); + SwitchBox swb = {t.getCol(), t.getRow()}; std::vector connects; for (auto connectOp : switchboxOp.getOps()) { - connects.emplace_back(Port{toAMDAIEStrmT(connectOp.getSourceBundle()), - connectOp.getSourceChannel()}, - Port{toAMDAIEStrmT(connectOp.getDestBundle()), - connectOp.getDestChannel()}, - Connect::Interconnect::SWB, swb.col, swb.row); + connects.emplace_back( + Port{connectOp.getSourceBundle(), connectOp.getSourceChannel()}, + Port{connectOp.getDestBundle(), connectOp.getDestChannel()}, + Connect::Interconnect::SWB, swb.col, swb.row); } if (failed(configureStreamSwitch(deviceModel, swb, connects))) { return failure(); @@ -308,7 +262,7 @@ LogicalResult addInitConfigToCDO(const AMDAIEDeviceModel &deviceModel, static_cast(amsel.getMsel())}); } if (failed(configureSwitchPacketMasters( - deviceModel, swb, toAMDAIEStrmT(masterSetOp.getDestBundle()), + deviceModel, swb, masterSetOp.getDestBundle(), masterSetOp.getDestChannel(), amSels, masterSetOp->hasAttr("keep_pkt_header")))) return failure(); @@ -321,12 +275,10 @@ LogicalResult addInitConfigToCDO(const AMDAIEDeviceModel &deviceModel, AMSelOp amselOp = cast(packetRuleOp.getAmsel().getDefiningOp()); if (failed(configureSwitchPacketSlaves( - deviceModel, swb, - toAMDAIEStrmT(packetRulesOp.getSourceBundle()), + deviceModel, swb, packetRulesOp.getSourceBundle(), packetRulesOp.getSourceChannel(), - AMSel{static_cast(amselOp.arbiterIndex()), - static_cast(amselOp.getMselValue())}, - packetRuleOp.valueInt(), packetRuleOp.maskInt(), slot))) + AMSel{amselOp.getArbiterID(), amselOp.getMsel()}, + packetRuleOp.getValue(), packetRuleOp.getMask(), slot))) return failure(); slot++; } @@ -334,29 +286,20 @@ LogicalResult addInitConfigToCDO(const AMDAIEDeviceModel &deviceModel, } for (auto muxOp : device.getOps()) { - SwitchBox swb = {muxOp.getTileOp().getCol(), muxOp.getTileOp().getRow()}; + TileOp t = xilinx::AIE::getTileOp(*muxOp.getOperation()); + SwitchBox swb = {t.getCol(), t.getRow()}; std::vector connects; for (auto connectOp : muxOp.getOps()) { - connects.emplace_back(Port{toAMDAIEStrmT(connectOp.getSourceBundle()), - connectOp.getSourceChannel()}, - Port{toAMDAIEStrmT(connectOp.getDestBundle()), - connectOp.getDestChannel()}, - Connect::Interconnect::SHIMMUX, swb.col, swb.row); + connects.emplace_back( + Port{connectOp.getSourceBundle(), connectOp.getSourceChannel()}, + Port{connectOp.getDestBundle(), connectOp.getDestChannel()}, + Connect::Interconnect::SHIMMUX, swb.col, swb.row); } if (failed(configureStreamSwitch(deviceModel, swb, connects))) { return failure(); } } - // Cascade configuration - for (auto configOp : device.getOps()) { - TileOp tile = cast(configOp.getTile().getDefiningOp()); - TileLoc tileLoc = {tile.getCol(), tile.getCol()}; - Cascade casc = {tileLoc, toDir(configOp.getInputDir()), - toDir(configOp.getOutputDir())}; - if (failed(configureCascade(deviceModel, casc))) return failure(); - } - return success(); } @@ -365,7 +308,7 @@ LogicalResult addCoreEnableToCDO(const AMDAIEDeviceModel &deviceModel, // Start execution of all the cores. for (auto tileOp : device.getOps()) { TileLoc tileLoc = {tileOp.getCol(), tileOp.getRow()}; - if (auto coreOp = tileOp.getCoreOp(); + if (auto coreOp = getCoreOp(tileOp); coreOp && failed(coreEnable(deviceModel, tileLoc))) return failure(); } diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargetLdScript.cpp b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargetLdScript.cpp index 63c4a6f37..a106f1e53 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargetLdScript.cpp +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargetLdScript.cpp @@ -5,7 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception #include "AMDAIETargets.h" -#include "aie/Dialect/AIE/IR/AIEDialect.h" +#include "aie/AIEDialect.h" using namespace mlir; using namespace xilinx; @@ -15,9 +15,9 @@ using namespace xilinx::AIE; // with the given offset. The offset is different depending on where the buffers // are accessed from. static void writeLDScriptMap(raw_ostream &output, BufferOp buf, int offset) { - std::string bufName(buf.name().getValue()); - int bufferBaseAddr = getBufferBaseAddress(buf); - int numBytes = buf.getAllocationSize(); + std::string bufName(name(buf).getValue()); + int bufferBaseAddr = buf.getAddress().value(); + int numBytes = getAllocationSize(buf); output << ". = 0x" << llvm::utohexstr(offset + bufferBaseAddr) << ";\n"; output << bufName << " = .;\n"; output << ". += 0x" << llvm::utohexstr(numBytes) << ";\n"; @@ -65,15 +65,15 @@ LogicalResult mlir::iree_compiler::AMDAIE::AIETranslateToLdScript( AMDAIEDeviceModel deviceModel = getDeviceModel(static_cast(deviceOp.getDevice())); for (auto tile : deviceOp.getOps()) - if (tile.colIndex() == tileCol && tile.rowIndex() == tileRow) { - TileLoc srcCoord = {tile.colIndex(), tile.rowIndex()}; + if (tile.getCol() == tileCol && tile.getRow() == tileRow) { + TileLoc srcCoord = {tile.getCol(), tile.getRow()}; // Figure out how much memory we have left for random allocations - auto core = tile.getCoreOp(); + auto core = getCoreOp(tile); int max = core.getStackSize(); for (auto buf : buffers[tiles[srcCoord]]) { - int bufferBaseAddr = getBufferBaseAddress(buf); - int numBytes = buf.getAllocationSize(); + int bufferBaseAddr = buf.getAddress().value(); + int numBytes = getAllocationSize(buf); max = std::max(max, bufferBaseAddr + numBytes); } int origin = deviceModel.getMemInternalBaseAddress() + max; @@ -101,7 +101,7 @@ SECTIONS } > data )THESCRIPT"; auto doBuffer = [&](std::optional tile, int offset, - std::string dir) { + const std::string& dir) { if (tile) { if (tiles.count({tile->col, tile->row})) for (auto buf : buffers[tiles[{tile->col, tile->row}]]) @@ -120,7 +120,7 @@ SECTIONS << ";\n"; output << "_sp_start_value_DM_stack = .;\n"; - if (auto core = tile.getCoreOp()) + if (auto core = getCoreOp(tile)) output << ". += 0x" << llvm::utohexstr(core.getStackSize()) << "; /* stack */\n"; else @@ -138,9 +138,9 @@ SECTIONS output << " .bss : { *(.bss) } > data\n"; output << " .bss.DMb.4 : { *(.bss.DMb.4) } > data\n"; output << "}\n"; - if (auto coreOp = tile.getCoreOp()) { - output << "PROVIDE(main = core_" << tile.getCol() << "_" - << tile.getRow() << ");\n"; + if (auto coreOp = getCoreOp(tile)) { + output << "PROVIDE(main = core_" << std::to_string(tile.getCol()) << "_" + << std::to_string(tile.getRow()) << ");\n"; } } return success(); diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargets.h b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargets.h index f6a0c398e..5052fadd8 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargets.h +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIETargets.h @@ -7,7 +7,7 @@ #ifndef AIE_TARGETS_AIETARGETS_H #define AIE_TARGETS_AIETARGETS_H -#include "aie/Dialect/AIE/IR/AIEDialect.h" +#include "aie/AIEDialect.h" #include "aie/Passes.h" #include "iree-amd-aie/aie_runtime/iree_aie_runtime.h" #include "llvm/Support/raw_ostream.h" @@ -15,9 +15,6 @@ #include "mlir/Support/LogicalResult.h" namespace mlir::iree_compiler::AMDAIE { -mlir::LogicalResult AIETranslateToNPU(mlir::ModuleOp module, - llvm::raw_ostream &output); - std::vector AIETranslateToNPU(mlir::ModuleOp); mlir::LogicalResult AIETranslateToLdScript(mlir::ModuleOp module, @@ -32,26 +29,6 @@ mlir::LogicalResult AIETranslateToCDODirect( mlir::ModuleOp m, llvm::StringRef workDirPath, bool bigEndian = false, bool emitUnified = false, bool cdoDebug = false, bool aieSim = false, bool enableCores = true); - -inline void collectTiles( - xilinx::AIE::DeviceOp &device, - DenseMap &tiles) { - for (auto tile : device.getOps()) { - int colIndex = tile.colIndex(); - int rowIndex = tile.rowIndex(); - tiles[{colIndex, rowIndex}] = tile; - } -} - -inline void collectBuffers( - xilinx::AIE::DeviceOp &device, - DenseMap> &buffers) { - for (xilinx::AIE::BufferOp buffer : device.getOps()) { - Operation *tileOp = buffer.getTile().getDefiningOp(); - buffers[tileOp].push_back(buffer); - } -} - } // namespace mlir::iree_compiler::AMDAIE #endif diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/XCLBinGen.cpp b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/XCLBinGen.cpp index 9b5b3f317..18d4c3cfe 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/XCLBinGen.cpp +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/XCLBinGen.cpp @@ -14,7 +14,6 @@ #include #include "AMDAIETargets.h" -#include "aie/Targets/AIETargets.h" #include "aievec/Passes.h" #include "iree-amd-aie/Transforms/Passes.h" #include "iree/compiler/Utils/ToolUtils.h" @@ -142,21 +141,17 @@ static FailureOr findAMDAIETool(std::string toolName, Path toolBinExe = ""; if (!amdAIEInstallDir.empty()) { toolBinExe = amdAIEInstallDir / toolName; - if (llvm::sys::fs::exists(toolBinExe.native())) - return toolBinExe; + if (llvm::sys::fs::exists(toolBinExe.native())) return toolBinExe; toolBinExe = amdAIEInstallDir / "bin" / toolName; - if (llvm::sys::fs::exists(toolBinExe.native())) - return toolBinExe; + if (llvm::sys::fs::exists(toolBinExe.native())) return toolBinExe; toolBinExe = amdAIEInstallDir / "tools" / toolName; - if (llvm::sys::fs::exists(toolBinExe.native())) - return toolBinExe; + if (llvm::sys::fs::exists(toolBinExe.native())) return toolBinExe; } toolBinExe = mlir::iree_compiler::findTool(toolName); - if (llvm::sys::fs::exists(toolBinExe.native())) - return toolBinExe; + if (llvm::sys::fs::exists(toolBinExe.native())) return toolBinExe; llvm::errs() << "Could not find " << toolName << ". Check your --iree-amd-aie-install-dir flag"; @@ -321,7 +316,8 @@ static std::optional runTool( stats.TotalTime) .count(); std::string exitStatusStr = result == 0 ? "Succeeded" : "Failed"; - llvm::outs() << "\n" << exitStatusStr << " in totalTime " << totalTime + llvm::outs() << "\n" + << exitStatusStr << " in totalTime " << totalTime << " [s]. Exit code=" << result << "\n"; llvm::outs() << outputFromFile << "\n"; } @@ -468,9 +464,9 @@ static LogicalResult generateCoreElfFiles( std::string errorMessage; for (auto tileOp : tileOps) { - int col = tileOp.colIndex(); - int row = tileOp.rowIndex(); - auto coreOp = tileOp.getCoreOp(); + int col = tileOp.getCol(); + int row = tileOp.getRow(); + auto coreOp = getCoreOp(tileOp); if (!coreOp) continue; std::string elfFileName; diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEConvertCoreForallToFor.cpp b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEConvertCoreForallToFor.cpp index 4f985efce..8e3ec6093 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEConvertCoreForallToFor.cpp +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEConvertCoreForallToFor.cpp @@ -13,7 +13,7 @@ // //===----------------------------------------------------------------------===// -#include "aie/Dialect/AIE/IR/AIEDialect.h" +#include "aie/AIEDialect.h" #include "iree-amd-aie/Transforms/Passes.h" #include "mlir/Dialect/SCF/IR/SCF.h" #include "mlir/Dialect/SCF/Transforms/Transforms.h" diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEDistributeCoresAndObjectFifos.cpp b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEDistributeCoresAndObjectFifos.cpp index 9adfec4a5..bfb24ecba 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEDistributeCoresAndObjectFifos.cpp +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIEDistributeCoresAndObjectFifos.cpp @@ -4,7 +4,7 @@ // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -#include "aie/Dialect/AIE/IR/AIEDialect.h" +#include "aie/AIEDialect.h" #include "iree-amd-aie/IR/AMDAIEOps.h" #include "iree-amd-aie/Transforms/AMDAIEDmaUtils.h" #include "iree-amd-aie/Transforms/Passes.h" @@ -31,14 +31,6 @@ namespace { // Utilities //===----------------------------------------------------------------------===// -/// Comparator for a pair of `amdaie.dma_cpy_nd` on the first tile operation's -/// column index. -bool dmaColComparator( - std::pair> &a, - std::pair> &b) { - return TileOp::tileColumnComparator(a.second[0], b.second[0]); -}; - /// Utility to use tuple coordinates as key of a `DenseMap`. struct LocationMapInfo { static SmallVector> getEmptyKey() { diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIELowerToAIE.cpp b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIELowerToAIE.cpp index d6f26d522..8c1f21e48 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIELowerToAIE.cpp +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Transforms/AMDAIELowerToAIE.cpp @@ -13,8 +13,8 @@ #include -#include "aie/Dialect/AIE/IR/AIEDialect.h" -#include "aie/Dialect/AIEX/IR/AIEXDialect.h" +#include "aie/AIEDialect.h" +#include "aie/AIEXDialect.h" #include "iree-amd-aie/IR/AMDAIEDialect.h" #include "iree-amd-aie/IR/AMDAIEOps.h" #include "iree-amd-aie/Transforms/AMDAIEUtils.h" diff --git a/experimental/delegate/README.md b/experimental/delegate/README.md index 002ac7e88..6b15bb37f 100644 --- a/experimental/delegate/README.md +++ b/experimental/delegate/README.md @@ -211,12 +211,10 @@ cd export IREE_ROOT=$PWD cd iree-amd-aie/experimental/delegate export IREE_INSTALL_DIR=$IREE_ROOT/iree-build/ -export MLIR_AIE_INSTALL_DIR=$IREE_ROOT/iree-amd-aie/third_party/mlir-aie/install export PEANO_INSTALL_DIR=$IREE_ROOT/install export VITIS_INSTALL_PATH=/proj/xbuilds/2023.2_released/installs/lin64/Vitis/2023.2 ../../build_tools/ci/run_matmul_test.sh results_dir_tmp $IREE_INSTALL_DIR \ - $MLIR_AIE_INSTALL_DIR $PEANO_INSTALL_DIR /opt/xilinx/xrt \ $VITIS_INSTALL_PATH 0 ``` diff --git a/iree_compiler_plugin.cmake b/iree_compiler_plugin.cmake index 1061b273b..7ec4465b4 100644 --- a/iree_compiler_plugin.cmake +++ b/iree_compiler_plugin.cmake @@ -10,7 +10,6 @@ include_directories(${Boost_INCLUDE_DIRS}) set(IREE_AMD_AIE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") set(IREE_AMD_AIE_RUNTIME_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}/runtime/src) set(IREE_MLIR_AIR_SOURCE_DIR "${IREE_AMD_AIE_SOURCE_DIR}/third_party/mlir-air/mlir") -set(IREE_MLIR_AIE_SOURCE_DIR "${IREE_AMD_AIE_SOURCE_DIR}/third_party/mlir-aie") add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/compiler/plugins/target/AMD-AIE target/AMD-AIE) add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/tests/samples AMD-AIE/tests/samples) diff --git a/iree_runtime_plugin.cmake b/iree_runtime_plugin.cmake index 080c78bbe..b76099120 100644 --- a/iree_runtime_plugin.cmake +++ b/iree_runtime_plugin.cmake @@ -8,7 +8,6 @@ include(FetchContent) set(IREE_AMD_AIE_SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}") set(IREE_MLIR_AIR_SOURCE_DIR "${IREE_AMD_AIE_SOURCE_DIR}/third_party/mlir-air/mlir") -set(IREE_MLIR_AIE_SOURCE_DIR "${IREE_AMD_AIE_SOURCE_DIR}/third_party/mlir-aie") set(IREE_AMD_AIE_ENABLE_XRT_DRIVER OFF) if("xrt" IN_LIST IREE_EXTERNAL_HAL_DRIVERS) diff --git a/runtime/src/iree-amd-aie/aie_runtime/AMDAIEEnums.td b/runtime/src/iree-amd-aie/aie_runtime/AMDAIEEnums.td index 8fd168ca1..4b0df4b44 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/AMDAIEEnums.td +++ b/runtime/src/iree-amd-aie/aie_runtime/AMDAIEEnums.td @@ -10,7 +10,7 @@ include "mlir/IR/AttrTypeBase.td" include "mlir/IR/EnumAttr.td" -def AMDAIE_AMDAIEDevice: I32EnumAttr<"AMDAIEDevice", +def AMDAIEDeviceAttr: I32EnumAttr<"AMDAIEDevice", "Enum with target AMDAIE devices.", [ I32EnumAttrCase<"xcvc1902", 1>, @@ -36,4 +36,24 @@ def DMAChannelDir: I32EnumAttr<"DMAChannelDir", let cppNamespace = "mlir::iree_compiler::AMDAIE"; } +def StrmSwPortTypeAttr: I32EnumAttr<"StrmSwPortType", "", + [ + I32EnumAttrCase<"CORE", 0>, + I32EnumAttrCase<"DMA", 1>, + I32EnumAttrCase<"CTRL", 2>, + I32EnumAttrCase<"FIFO", 3>, + I32EnumAttrCase<"SOUTH", 4>, + I32EnumAttrCase<"WEST", 5>, + I32EnumAttrCase<"NORTH", 6>, + I32EnumAttrCase<"EAST", 7>, + I32EnumAttrCase<"TRACE", 8>, + I32EnumAttrCase<"UCTRLR", 9>, + I32EnumAttrCase<"SS_PORT_TYPE_MAX", 10>, + // "illegal" types after max + I32EnumAttrCase<"NOC", 11> + ]> +{ + let cppNamespace = "mlir::iree_compiler::AMDAIE"; +} + #endif // IREE_AIE_RUNTIME_AMDAIEENUMS diff --git a/runtime/src/iree-amd-aie/aie_runtime/CMakeLists.txt b/runtime/src/iree-amd-aie/aie_runtime/CMakeLists.txt index b8ec1077c..2f5d6d452 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/CMakeLists.txt +++ b/runtime/src/iree-amd-aie/aie_runtime/CMakeLists.txt @@ -39,26 +39,26 @@ message(STATUS "OpenSSL include directories:" ${OPENSSL_INCLUDE_DIR}) # https://stackoverflow.com/a/49216539/9045206 function(remove_flag_from_target _target _flag) - get_target_property(_target_cxx_flags ${_target} COMPILE_OPTIONS) - if(_target_cxx_flags) - list(REMOVE_ITEM _target_cxx_flags ${_flag}) - set_target_properties(${_target} PROPERTIES COMPILE_OPTIONS "${_target_cxx_flags}") - endif() + get_target_property(_target_cxx_flags ${_target} COMPILE_OPTIONS) + if(_target_cxx_flags) + list(REMOVE_ITEM _target_cxx_flags ${_flag}) + set_target_properties(${_target} PROPERTIES COMPILE_OPTIONS "${_target_cxx_flags}") + endif() endfunction() function(replace_string_in_file _file _match_string _replace_string) - if(NOT (EXISTS ${_file})) - message(FATAL_ERROR "file ${_file} does not exist") - endif() - file(READ "${_file}" _file_contents) - if(_file_contents STREQUAL "") - message(FATAL_ERROR "empty file contents for ${_file}") - endif() - string(REPLACE "${_match_string}" "${_replace_string}" _file_contents "${_file_contents}") - if(_file_contents STREQUAL "") - message(FATAL_ERROR "empty replacement contents for ${_file}") - endif() - file(WRITE "${_file}" "${_file_contents}") + if(NOT (EXISTS ${_file})) + message(FATAL_ERROR "file ${_file} does not exist") + endif() + file(READ "${_file}" _file_contents) + if(_file_contents STREQUAL "") + message(FATAL_ERROR "empty file contents for ${_file}") + endif() + string(REPLACE "${_match_string}" "${_replace_string}" _file_contents "${_file_contents}") + if(_file_contents STREQUAL "") + message(FATAL_ERROR "empty replacement contents for ${_file}") + endif() + file(WRITE "${_file}" "${_file_contents}") endfunction() # ############################################################################## diff --git a/runtime/src/iree-amd-aie/aie_runtime/iree_aie_router.h b/runtime/src/iree-amd-aie/aie_runtime/iree_aie_router.h index cfc829158..e14ae7ee2 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/iree_aie_router.h +++ b/runtime/src/iree-amd-aie/aie_runtime/iree_aie_router.h @@ -20,7 +20,8 @@ struct Port { StrmSwPortType bundle; int channel; - Port() = delete; + // mlir-air legacy + Port() : bundle(), channel() {} Port(StrmSwPortType b, int c) : bundle(b), channel(c) {} typedef std::tuple TupleType; Port(TupleType t) : Port(std::get<0>(t), std::get<1>(t)) {} diff --git a/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.cc b/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.cc index 0a01481a8..969f0623b 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.cc +++ b/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.cc @@ -440,6 +440,13 @@ uint32_t AMDAIEDeviceModel::getNumDestSwitchBoxConnections( return strmMod->MstrConfig[CheckedAieRtCompatStrmSwPortType(bundle)].NumPorts; } +// the difference between this fn and the one it calls is SwitchBox vs Switchbox +uint32_t AMDAIEDeviceModel::getNumDestSwitchboxConnections( + int col, int row, StrmSwPortType bundle) const { + return getNumDestSwitchBoxConnections(static_cast(col), + static_cast(row), bundle); +} + uint32_t AMDAIEDeviceModel::getColumnShift() const { return configPtr.ColShift; } diff --git a/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.h b/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.h index 01b9403b5..ebc049e2e 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.h +++ b/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.h @@ -70,9 +70,9 @@ static_assert(static_cast(DMAChannelDir::MM2S) == struct SwitchDMAConnection { DMAChannelDir direction; - int channel; + uint8_t channel; - SwitchDMAConnection(DMAChannelDir direction, int channel) + SwitchDMAConnection(DMAChannelDir direction, uint8_t channel) : direction(direction), channel(channel) {} bool operator==(const SwitchDMAConnection& rhs) const { @@ -134,21 +134,10 @@ enum class AMDAIEDmaBdProp : uint8_t { MAX = sizeof(XAie_DmaBdProp) }; -enum class StrmSwPortType : uint8_t { - CORE = ::StrmSwPortType::CORE, - DMA, - CTRL, - FIFO, - SOUTH, - WEST, - NORTH, - EAST, - TRACE, - UCTRLR, - SS_PORT_TYPE_MAX, - // "illegal" types after max - NOC, -}; +static_assert(static_cast(StrmSwPortType::CORE) == + ::StrmSwPortType::CORE, + "mlir::iree_compiler::AMDAIE::StrmSwPortType is out of sync with " + "aie-rt's StrmSwPortType"); static_assert(static_cast(StrmSwPortType::CORE) == 0, "mlir::iree_compiler::AMDAIE::StrmSwPortType is out of sync with " "aie-rt's StrmSwPortType"); @@ -199,6 +188,9 @@ inline ::XAie_TxnOpcode txnToTxn(XAie_TxnOpcode t) { return static_cast<::XAie_TxnOpcode>(t); } +// mlir-air legacy +enum class AIEArch : uint8_t { AIE1 = 1, AIE2 = 2 }; + /* * This struct is meant to be a thin wrapper around aie-rt, which provides * the canonical representation/metadata for AIE devices; attributes like number @@ -306,6 +298,12 @@ struct AMDAIEDeviceModel { AMDAIETileType tileType) const; AMDAIEDevice device; + + // mlir-air legacy + uint32_t getNumDestSwitchboxConnections(int col, int row, + StrmSwPortType bundle) const; + uint32_t getNumMemTileRows() const { return 1; } + AIEArch getTargetArch() const { return AIEArch::AIE2; } }; struct AMDAIEDeviceModel getDeviceModel(AMDAIEDevice device); @@ -316,11 +314,10 @@ bool isNPUDevice(mlir::iree_compiler::AMDAIE::AMDAIEDevice d); /// ================== stringification utils ============================= /// ====================================================================== -std::string to_string(const int& value); -std::string to_string(const uint32_t& value); -std::string to_string(const uint64_t& value); - #define TO_STRINGS(_) \ + _(int) \ + _(uint32_t) \ + _(uint64_t) \ _(AMDAIEDmaProp) \ _(AMDAIETileType) \ _(AieRC) \ @@ -410,16 +407,6 @@ static_assert(XAIE_OK == 0); to_string(r)); \ } while (0) -#define TRY_XAIE_API_EMIT_ERROR(OP, API, ...) \ - do { \ - LLVM_DEBUG(llvm::dbgs() << "XAIE API: " << #API << " with args: "); \ - LLVM_DEBUG(SHOW_ARGS(llvm::dbgs(), __VA_ARGS__)); \ - LLVM_DEBUG(llvm::dbgs() << "\n"); \ - LLVM_DEBUG(llvm::dbgs().flush()); \ - if (auto r = API(__VA_ARGS__)) \ - return OP.emitOpError() << #API " failed with " << r; \ - } while (0) - #define TRY_XAIE_API_LOGICAL_RESULT(API, ...) \ do { \ LLVM_DEBUG(llvm::dbgs() << "XAIE API: " << #API << " with args: "); \ diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/CMakeLists.txt b/runtime/src/iree-amd-aie/aie_runtime/test/CMakeLists.txt index 869820505..24f4383d4 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/test/CMakeLists.txt +++ b/runtime/src/iree-amd-aie/aie_runtime/test/CMakeLists.txt @@ -31,17 +31,6 @@ iree_lit_test( "hostonly" ) -iree_cc_test( - NAME - DeviceModelTestCppTest - SRCS - DeviceModelTest.cpp - DEPS - gtest - iree::target::amd-aie::aie::AIEDialectIR - iree-amd-aie::aie_runtime::iree_aie_runtime_static -) - iree_cc_test( NAME test_0335_aie_dma_tile_dma_packet_switch_mode @@ -105,10 +94,4 @@ iree_lit_test( "hostonly" ) - -target_include_directories( - iree-amd-aie_aie_runtime_test_DeviceModelTestCppTest - PRIVATE "${IREE_MLIR_AIE_SOURCE_DIR}/include" -) - add_subdirectory(cdo) diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/DeviceModelTest.cpp b/runtime/src/iree-amd-aie/aie_runtime/test/DeviceModelTest.cpp deleted file mode 100644 index 63bf66110..000000000 --- a/runtime/src/iree-amd-aie/aie_runtime/test/DeviceModelTest.cpp +++ /dev/null @@ -1,487 +0,0 @@ -// Copyright 2024 The IREE Authors -// -// Licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception - -#include -#include - -extern "C" { -#include "xaiengine.h" -#include "xaiengine/xaie_ss_aieml.h" -#undef s8 -#undef u8 -#undef u16 -#undef s32 -#undef u32 -#undef u64 -} - -#include "aie/Dialect/AIE/IR/AIEDialect.h" -#include "aie/Dialect/AIE/IR/AIETargetModel.h" -#include "gtest/gtest-param-test.h" -#include "gtest/gtest.h" -#include "iree-amd-aie/aie_runtime/iree_aie_runtime.h" -#include "llvm/Support/FormatVariadic.h" - -// Without this using you do not get the operator<< overloads in -// iree_aie_runtime.h. -using namespace mlir::iree_compiler::AMDAIE; - -namespace { -using mlir::iree_compiler::AMDAIE::StrmSwPortType; -const std::map - _STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE = { - {StrmSwPortType::CORE, xilinx::AIE::WireBundle::Core}, - {StrmSwPortType::DMA, xilinx::AIE::WireBundle::DMA}, - {StrmSwPortType::CTRL, xilinx::AIE::WireBundle::Ctrl}, - {StrmSwPortType::FIFO, xilinx::AIE::WireBundle::FIFO}, - {StrmSwPortType::SOUTH, xilinx::AIE::WireBundle::South}, - {StrmSwPortType::WEST, xilinx::AIE::WireBundle::West}, - {StrmSwPortType::NORTH, xilinx::AIE::WireBundle::North}, - {StrmSwPortType::EAST, xilinx::AIE::WireBundle::East}, - {StrmSwPortType::TRACE, xilinx::AIE::WireBundle::Trace}, -}; - -xilinx::AIE::WireBundle STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType s) { - return _STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE.at(s); -} - -template -class AMDAIENPUDeviceModelParameterizedTupleNPU4ColTestFixture - : public ::testing::TestWithParam> { - public: - explicit AMDAIENPUDeviceModelParameterizedTupleNPU4ColTestFixture() - : deviceModel(mlir::iree_compiler::AMDAIE::getDeviceModel(D)), - targetModel(xilinx::AIE::getTargetModel(T)) {} - - protected: - AMDAIEDeviceModel deviceModel; - const xilinx::AIE::AIETargetModel &targetModel; -}; - -template -class AMDAIENPUDeviceModelParameterizedTupleTestNPU4ColFixture - : public AMDAIENPUDeviceModelParameterizedTupleNPU4ColTestFixture< - AMDAIEDevice::npu1_4col, xilinx::AIE::AIEDevice::npu1_4col, - Types...> {}; - -class AMDAIENPUDeviceModelParameterizedNumColsNumRowsNPU4ColTestFixture - : public AMDAIENPUDeviceModelParameterizedTupleTestNPU4ColFixture {}; - -class - AMDAIENPUDeviceModelParameterizedAllPairsTimesAllSwitchesNPU4ColTestFixture - : public AMDAIENPUDeviceModelParameterizedTupleTestNPU4ColFixture {}; - -class AMDAIENPUDeviceModelParameterizedAllPairsTimesAllPairsNPU4ColTestFixture - : public AMDAIENPUDeviceModelParameterizedTupleTestNPU4ColFixture< - int, int, int, int> {}; - -class AMDAIENPUDeviceModelParameterizedSixTupleNPU4ColTestFixture - : public AMDAIENPUDeviceModelParameterizedTupleTestNPU4ColFixture< - int, int, StrmSwPortType, StrmSwPortType, int, int> {}; - -TEST(SameNumRowsCols_NPU1, Test0) { - AMDAIEDeviceModel deviceModel = - mlir::iree_compiler::AMDAIE::getDeviceModel(AMDAIEDevice::npu1); - const xilinx::AIE::AIETargetModel &targetModel = - xilinx::AIE::getTargetModel(xilinx::AIE::AIEDevice::npu1); - - EXPECT_EQ(deviceModel.rows(), targetModel.rows()); - EXPECT_EQ(deviceModel.columns(), targetModel.columns()); -} - -TEST(SameNumRowsCols_NPU1_4Col, Test0) { - AMDAIEDeviceModel deviceModel = - mlir::iree_compiler::AMDAIE::getDeviceModel(AMDAIEDevice::npu1_4col); - const xilinx::AIE::AIETargetModel &targetModel = - xilinx::AIE::getTargetModel(xilinx::AIE::AIEDevice::npu1_4col); - - // https://github.com/Xilinx/aie-rt/blob/38fcf1f9eb7c678defaf8c19ffb50a679b644452/driver/src/global/xaiegbl.c#L203 - // mlir-aie gets this wrong; the relationship is partitionStartCol + - // partitionNumCols < devNumCols - // mlir-aie sets devNumCols == partitionNumCols - EXPECT_EQ(deviceModel.rows(), targetModel.rows()); - EXPECT_NE(deviceModel.columns(), targetModel.columns()); -} - -TEST_P(AMDAIENPUDeviceModelParameterizedNumColsNumRowsNPU4ColTestFixture, - CoreTilesAgree) { - auto [c, r] = GetParam(); - mlir::iree_compiler::AMDAIE::AMDAIETileType tt = - deviceModel.getTileType(c, r); - EXPECT_EQ(deviceModel.isCoreTile(c, r), targetModel.isCoreTile(c, r)) - << "Core tile disagree; " << tt; - if (deviceModel.isCoreTile(c, r)) { - EXPECT_EQ(deviceModel.getLocalMemorySize(c, r), - targetModel.getLocalMemorySize()) - << "local size don't agree"; - } -} - -TEST_P(AMDAIENPUDeviceModelParameterizedNumColsNumRowsNPU4ColTestFixture, - MemTilesAgree) { - auto [c, r] = GetParam(); - - EXPECT_EQ(deviceModel.isMemTile(c, r), targetModel.isMemTile(c, r)) - << "Mem tile disagree; " << deviceModel.getTileType(c, r) << " " << c - << ", " << r << "\n"; - if (deviceModel.isMemTile(c, r)) { - EXPECT_EQ(deviceModel.getMemTileSize(c, r), targetModel.getMemTileSize()) - << "memtile memory size don't agree; " << c << ", " << r << "\n"; - } -} - -TEST_P(AMDAIENPUDeviceModelParameterizedNumColsNumRowsNPU4ColTestFixture, - ShimNOCTileAgree) { - auto [c, r] = GetParam(); - EXPECT_EQ(deviceModel.isShimNOCTile(c, r), targetModel.isShimNOCTile(c, r)) - << "ShimNOC tile disagree; " << deviceModel.getTileType(c, r); -} - -TEST_P(AMDAIENPUDeviceModelParameterizedNumColsNumRowsNPU4ColTestFixture, - ShimPLTileAgree) { - auto [c, r] = GetParam(); - EXPECT_EQ(deviceModel.isShimPLTile(c, r), targetModel.isShimPLTile(c, r)) - << "ShimPL tile disagree; " << deviceModel.getTileType(c, r); -} - -TEST_P(AMDAIENPUDeviceModelParameterizedNumColsNumRowsNPU4ColTestFixture, - NumLocksAgree) { - auto [c, r] = GetParam(); - EXPECT_EQ(deviceModel.getNumLocks(c, r), targetModel.getNumLocks(c, r)); -} - -TEST_P(AMDAIENPUDeviceModelParameterizedNumColsNumRowsNPU4ColTestFixture, - NumBDsAgree) { - auto [c, r] = GetParam(); - EXPECT_EQ(deviceModel.getNumBDs(c, r), targetModel.getNumBDs(c, r)); -} - -TEST_P(AMDAIENPUDeviceModelParameterizedNumColsNumRowsNPU4ColTestFixture, - MemWestAgree) { - auto [c, r] = GetParam(); - TileLoc dloc = {c, r}; - xilinx::AIE::TileID tloc = {c, r}; - auto d = deviceModel.getMemWest(dloc); - auto t = targetModel.getMemWest(tloc); - - EXPECT_EQ(d.has_value(), t.has_value()) << "MemWest disagree on exist "; - if (d.has_value()) { - EXPECT_EQ(d->col, t->col) << "MemWest disagree on col"; - EXPECT_EQ(d->row, t->row) << "MemWest disagree on row"; - } -} - -TEST_P(AMDAIENPUDeviceModelParameterizedNumColsNumRowsNPU4ColTestFixture, - MemEastAgree) { - auto [c, r] = GetParam(); - TileLoc dloc = {c, r}; - xilinx::AIE::TileID tloc = {c, r}; - auto d = deviceModel.getMemEast(dloc); - auto t = targetModel.getMemEast(tloc); - EXPECT_EQ(d.has_value(), t.has_value()) << "MemEast disagree on exist "; - if (d.has_value()) { - EXPECT_EQ(d->col, t->col) << "MemEast disagree on col"; - EXPECT_EQ(d->row, t->row) << "MemEast disagree on row"; - } -} - -TEST_P(AMDAIENPUDeviceModelParameterizedNumColsNumRowsNPU4ColTestFixture, - MemNorthAgree) { - auto [c, r] = GetParam(); - TileLoc dloc = {c, r}; - xilinx::AIE::TileID tloc = {c, r}; - auto d = deviceModel.getMemNorth(dloc); - auto t = targetModel.getMemNorth(tloc); - EXPECT_EQ(d.has_value(), t.has_value()) << "MemNorth disagree on exist "; - if (d.has_value()) { - EXPECT_EQ(d->col, t->col) << "MemNorth disagree on col"; - EXPECT_EQ(d->row, t->row) << "MemNorth disagree on row"; - } -} - -TEST_P(AMDAIENPUDeviceModelParameterizedNumColsNumRowsNPU4ColTestFixture, - MemSouthAgree) { - auto [c, r] = GetParam(); - TileLoc dloc = {c, r}; - xilinx::AIE::TileID tloc = {c, r}; - auto d = deviceModel.getMemSouth(dloc); - auto t = targetModel.getMemSouth(tloc); - EXPECT_EQ(d.has_value(), t.has_value()) << "MemSouth disagree on exist "; - if (d.has_value()) { - EXPECT_EQ(d->col, t->col) << "MemSouth disagree on col"; - EXPECT_EQ(d->row, t->row) << "MemSouth disagree on row"; - } -} - -TEST_P(AMDAIENPUDeviceModelParameterizedAllPairsTimesAllPairsNPU4ColTestFixture, - HasMemWestAgree) { - auto [c, r, cc, rr] = GetParam(); - EXPECT_EQ(deviceModel.hasMemWest(c, r, cc, rr), - targetModel.isMemWest(c, r, cc, rr)) - << "hasMemWest disagree"; -} - -TEST_P(AMDAIENPUDeviceModelParameterizedAllPairsTimesAllPairsNPU4ColTestFixture, - HasMemEastAgree) { - auto [c, r, cc, rr] = GetParam(); - EXPECT_EQ(deviceModel.hasMemEast(c, r, cc, rr), - targetModel.isMemEast(c, r, cc, rr)) - << "hasMemEast disagree"; -} - -TEST_P(AMDAIENPUDeviceModelParameterizedAllPairsTimesAllPairsNPU4ColTestFixture, - HasMemNorthAgree) { - auto [c, r, cc, rr] = GetParam(); - EXPECT_EQ(deviceModel.hasMemNorth(c, r, cc, rr), - targetModel.isMemNorth(c, r, cc, rr)) - << "hasMemNorth disagree"; -} - -TEST_P(AMDAIENPUDeviceModelParameterizedAllPairsTimesAllPairsNPU4ColTestFixture, - HasMemSouthAgree) { - auto [c, r, cc, rr] = GetParam(); - EXPECT_EQ(deviceModel.hasMemSouth(c, r, cc, rr), - targetModel.isMemSouth(c, r, cc, rr)) - << "hasMemSouth disagree"; -} - -const std::map, std::tuple, - std::less<>> - NumSourceSwitchBoxConnectionsFails{ - // c, r, port, deviceModelNumSrc, targetModelNumSrc - {{0, 0, StrmSwPortType::TRACE}, {2, 1}}, - // trace - {{1, 0, StrmSwPortType::TRACE}, {2, 1}}, - {{2, 0, StrmSwPortType::TRACE}, {2, 1}}, - {{3, 0, StrmSwPortType::TRACE}, {2, 1}}, - {{4, 0, StrmSwPortType::TRACE}, {2, 1}}, - // east - {{3, 0, StrmSwPortType::EAST}, {4, 0}}, - {{3, 2, StrmSwPortType::EAST}, {4, 0}}, - {{3, 3, StrmSwPortType::EAST}, {4, 0}}, - {{3, 4, StrmSwPortType::EAST}, {4, 0}}, - {{3, 5, StrmSwPortType::EAST}, {4, 0}}}; - -TEST_P( - AMDAIENPUDeviceModelParameterizedAllPairsTimesAllSwitchesNPU4ColTestFixture, - NumSourceSwitchBoxConnections) { - auto [c, r, strmSwPortType] = GetParam(); - auto srcSw = static_cast(strmSwPortType); - auto wireB = STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(srcSw); - auto deviceModelNumSrc = - deviceModel.getNumSourceSwitchBoxConnections(c, r, srcSw); - auto targetModelNumSrc = - targetModel.getNumSourceSwitchboxConnections(c, r, wireB); - const auto tup = std::make_tuple(c, r, srcSw); - if (NumSourceSwitchBoxConnectionsFails.count(tup)) { - auto [d, t] = NumSourceSwitchBoxConnectionsFails.at(tup); - EXPECT_EQ(deviceModelNumSrc, d); - EXPECT_EQ(targetModelNumSrc, t); - } else - EXPECT_EQ(deviceModelNumSrc, targetModelNumSrc) - << "diff src # for switch typ: " << srcSw << "\n"; -} - -const std::map, std::tuple, - std::less<>> - NumDestSwitchBoxConnectionsFails{ - // c, r, port, deviceModelNumSrc, targetModelNumSrc - {{3, 0, StrmSwPortType::EAST}, {4, 0}}, - {{3, 2, StrmSwPortType::EAST}, {4, 0}}, - {{3, 3, StrmSwPortType::EAST}, {4, 0}}, - {{3, 4, StrmSwPortType::EAST}, {4, 0}}, - {{3, 5, StrmSwPortType::EAST}, {4, 0}}}; - -TEST_P( - AMDAIENPUDeviceModelParameterizedAllPairsTimesAllSwitchesNPU4ColTestFixture, - NumDestSwitchBoxConnections) { - auto [c, r, strmSwPortType] = GetParam(); - auto dstSw = static_cast(strmSwPortType); - auto wireB = STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(dstSw); - auto deviceModelNumDst = - deviceModel.getNumDestSwitchBoxConnections(c, r, dstSw); - auto targetModelNumDst = - targetModel.getNumDestSwitchboxConnections(c, r, wireB); - const auto tup = std::make_tuple(c, r, dstSw); - if (NumDestSwitchBoxConnectionsFails.count(tup)) { - auto [d, t] = NumDestSwitchBoxConnectionsFails.at(tup); - EXPECT_EQ(deviceModelNumDst, d); - EXPECT_EQ(targetModelNumDst, t); - - } else - EXPECT_EQ(deviceModelNumDst, targetModelNumDst) - << "diff dest # for switch typ: " << dstSw << "\n"; -} - -class AMDAIENPUDeviceModelParameterizedMemtileConnectivityNPU4ColTestFixture - : public AMDAIENPUDeviceModelParameterizedTupleTestNPU4ColFixture {}; - -#define X false -#define O true - -const std::vector> MEMTILE_CONNECTIVITY = { - {O, X, X, X, X, X, O, O, O, O, O, O, O, O, O, O, O}, - {X, O, X, X, X, X, O, O, O, O, O, O, O, O, O, O, O}, - {X, X, O, X, X, X, O, O, O, O, O, O, O, O, O, O, O}, - {X, X, X, O, X, X, O, O, O, O, O, O, O, O, O, O, O}, - {X, X, X, X, O, X, O, O, O, O, O, O, O, O, O, O, O}, - {X, X, X, X, X, O, O, O, O, O, O, O, O, O, O, O, O}, - {X, X, X, X, X, O, X, O, O, O, O, O, O, O, O, O, O}, - {O, O, O, O, O, O, O, O, X, X, X, O, X, X, X, X, X}, - {O, O, O, O, O, O, O, X, O, X, X, X, O, X, X, X, X}, - {O, O, O, O, O, O, O, X, X, O, X, X, X, O, X, X, X}, - {O, O, O, O, O, O, O, X, X, X, O, X, X, X, O, X, X}, - {O, O, O, O, O, O, O, X, X, X, X, X, X, X, X, O, X}, - {O, O, O, O, O, O, O, X, X, X, X, X, X, X, X, X, O}, - {O, O, O, O, O, O, O, O, X, X, X, O, X, X, X, X, X}, - {O, O, O, O, O, O, O, X, O, X, X, X, O, X, X, X, X}, - {O, O, O, O, O, O, O, X, X, O, X, X, X, O, X, X, X}, - {O, O, O, O, O, O, O, X, X, X, O, X, X, X, O, X, X}, - {X, X, X, X, X, O, X, O, O, O, O, X, X, X, X, X, X}}; - -#undef X -#undef O - -TEST_P(AMDAIENPUDeviceModelParameterizedMemtileConnectivityNPU4ColTestFixture, - VerifyAIERTAIE2MemTileConnectivity) { - auto [slavePhyPort, masterPhyPort] = GetParam(); - ::StrmSwPortType slaveLogicalPortType, masterLogicalPortType; - uint8_t slaveLogicalPortNum, masterLogicalPortNum; - - XAie_LocType tileLoc = XAie_TileLoc(/*col=*/3, /*row=*/1); - XAie_StrmSwPhysicalToLogicalPort(&deviceModel.devInst, tileLoc, - XAIE_STRMSW_SLAVE, slavePhyPort, - &slaveLogicalPortType, &slaveLogicalPortNum); - XAie_StrmSwPhysicalToLogicalPort( - &deviceModel.devInst, tileLoc, XAIE_STRMSW_MASTER, masterPhyPort, - &masterLogicalPortType, &masterLogicalPortNum); - - AieRC RC = _XAieMl_MemTile_StrmSwCheckPortValidity( - slaveLogicalPortType, slaveLogicalPortNum, masterLogicalPortType, - masterLogicalPortNum); - - bool connected = MEMTILE_CONNECTIVITY[slavePhyPort][masterPhyPort]; - EXPECT_EQ(RC == XAIE_OK, connected) - << "slave: " << slaveLogicalPortType << (int)slaveLogicalPortNum << ": " - << slavePhyPort << "\n" - << "master: " << masterLogicalPortType << (int)masterLogicalPortNum - << ": " << masterPhyPort << "\n\n"; -} - -TEST_P(AMDAIENPUDeviceModelParameterizedSixTupleNPU4ColTestFixture, - IsLegalMemtileConnection) { - auto [c, r, srcStrmSwPortType, destStrmSwPortType, srcChan, dstChan] = - GetParam(); - - // TODO(max): maybe there's a way in gtest for the generators to be - // parameterized? - if ((srcStrmSwPortType == StrmSwPortType::CTRL || - destStrmSwPortType == StrmSwPortType::CTRL) && - (srcChan > 0 || dstChan > 0)) { - return; - } - if (srcStrmSwPortType == StrmSwPortType::TRACE && srcChan > 0) return; - if (srcStrmSwPortType == StrmSwPortType::NORTH && srcChan > 3) return; - if (destStrmSwPortType == StrmSwPortType::SOUTH && dstChan > 3) return; - - auto srcSw = srcStrmSwPortType; - auto srcWireB = STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(srcSw); - if (deviceModel.isMemTile(c, r)) { - auto destSw = destStrmSwPortType; - auto destWireb = STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(destSw); - auto deviceModelIsLegal = deviceModel.isLegalTileConnection( - c, r, srcSw, srcChan, destSw, dstChan); - auto targetModelIsLegal = targetModel.isLegalTileConnection( - c, r, srcWireB, srcChan, destWireb, dstChan); - - EXPECT_EQ(deviceModelIsLegal, targetModelIsLegal) - << "c,r: " << c << ", " << r << "\n" - << "src: " << to_string(srcSw) << ", " << srcChan << "\n" - << "dst: " << to_string(destSw) << ", " << dstChan << "\n\n"; - } -} - -TEST(IsLegalMemtileConnectionSouth4, Test0) { - AMDAIEDeviceModel deviceModel = - mlir::iree_compiler::AMDAIE::getDeviceModel(AMDAIEDevice::npu1_4col); - const xilinx::AIE::AIETargetModel &targetModel = - xilinx::AIE::getTargetModel(xilinx::AIE::AIEDevice::npu1_4col); - - auto deviceModelIsLegal = deviceModel.isLegalTileConnection( - 0, 1, StrmSwPortType::DMA, 2, StrmSwPortType::SOUTH, 4); - auto targetModelIsLegal = targetModel.isLegalTileConnection( - 0, 1, xilinx::AIE::WireBundle::DMA, 2, xilinx::AIE::WireBundle::South, 4); - EXPECT_EQ(deviceModelIsLegal, targetModelIsLegal); -} - -// setting a partition (i.e. using XAie_SetupPartitionConfig) actually changes -// the devNCols to the number of cols in the partition -// https://github.com/Xilinx/aie-rt/blob/38fcf1f9eb7c678defaf8c19ffb50a679b644452/driver/src/global/xaiegbl.c#L120 -#define NPU1_4COL_NUM_COLS 4 -#define NPU1_4COL_NUM_ROWS 6 - -INSTANTIATE_TEST_SUITE_P( - NumRowsNumColsTests, - AMDAIENPUDeviceModelParameterizedNumColsNumRowsNPU4ColTestFixture, - ::testing::Combine(::testing::Range(0, NPU1_4COL_NUM_COLS), - ::testing::Range(0, NPU1_4COL_NUM_ROWS))); - -INSTANTIATE_TEST_SUITE_P( - AllPairsTimesAllPairsTests, - AMDAIENPUDeviceModelParameterizedAllPairsTimesAllPairsNPU4ColTestFixture, - ::testing::Combine(::testing::Range(0, NPU1_4COL_NUM_COLS), - ::testing::Range(0, NPU1_4COL_NUM_ROWS), - ::testing::Range(0, NPU1_4COL_NUM_COLS), - ::testing::Range(0, NPU1_4COL_NUM_ROWS))); - -INSTANTIATE_TEST_SUITE_P( - AllPairsTimesAllSwitchesTests, - AMDAIENPUDeviceModelParameterizedAllPairsTimesAllSwitchesNPU4ColTestFixture, - ::testing::Combine( - ::testing::Range(0, NPU1_4COL_NUM_COLS), - ::testing::Range(0, NPU1_4COL_NUM_ROWS), - ::testing::Values(StrmSwPortType::CORE, StrmSwPortType::DMA, - StrmSwPortType::CTRL, StrmSwPortType::FIFO, - StrmSwPortType::SOUTH, StrmSwPortType::WEST, - StrmSwPortType::NORTH, StrmSwPortType::EAST, - StrmSwPortType::TRACE))); - -INSTANTIATE_TEST_SUITE_P( - VerifyAIERTAIE2MemTileConnectivity, - AMDAIENPUDeviceModelParameterizedMemtileConnectivityNPU4ColTestFixture, - ::testing::Combine(::testing::Range(0, (int)MEMTILE_CONNECTIVITY.size()), - ::testing::Range(0, - (int)MEMTILE_CONNECTIVITY[0].size()))); - -#define MAX_CHANNELS 6 - -// Figure 6-9: Stream-switch ports and connectivity matrix -const std::vector legalSlaves{ - StrmSwPortType::DMA, StrmSwPortType::CTRL, StrmSwPortType::SOUTH, - StrmSwPortType::NORTH, StrmSwPortType::TRACE}; -const std::vector legalMasters{ - StrmSwPortType::DMA, StrmSwPortType::CTRL, StrmSwPortType::SOUTH, - StrmSwPortType::NORTH}; - -INSTANTIATE_TEST_SUITE_P( - IsLegalMemtileConnectionTests, - AMDAIENPUDeviceModelParameterizedSixTupleNPU4ColTestFixture, - ::testing::Combine(::testing::Range(0, NPU1_4COL_NUM_COLS), - ::testing::Range(0, NPU1_4COL_NUM_ROWS), - ::testing::ValuesIn(legalSlaves), - ::testing::ValuesIn(legalMasters), - ::testing::Range(0, MAX_CHANNELS), - ::testing::Range(0, MAX_CHANNELS))); - -} // namespace - -int main(int argc, char **argv) { - ::testing::InitGoogleTest(&argc, argv); - return RUN_ALL_TESTS(); -} diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/CMakeLists.txt b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/CMakeLists.txt index b20e0518c..664c78da6 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/CMakeLists.txt +++ b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/CMakeLists.txt @@ -14,11 +14,6 @@ iree_cc_binary( iree_target_amd-aie_Target_AIETargets ) -target_include_directories( - iree-amd-aie_aie_runtime_test_cdo_aie_cdo_gen_test - PRIVATE "${IREE_MLIR_AIE_SOURCE_DIR}/include" -) - file(GLOB _mlir_files *.mlir) iree_lit_test_suite( diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/add_12_i8_using_2d_dma_op_with_padding.mlir b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/add_12_i8_using_2d_dma_op_with_padding.mlir index a074fc581..d901ffd92 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/add_12_i8_using_2d_dma_op_with_padding.mlir +++ b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/add_12_i8_using_2d_dma_op_with_padding.mlir @@ -4,8 +4,8 @@ module { aie.device(npu1_1col) { %tile_0_1 = aie.tile(0, 1) %objFifo_in0_cons_buff_0 = aie.buffer(%tile_0_1) {address = 0 : i32, sym_name = "objFifo_in0_cons_buff_0"} : memref<64x64xi8> - %objFifo_in0_cons_prod_lock = aie.lock(%tile_0_1, 0) {init = 1 : i32, sym_name = "objFifo_in0_cons_prod_lock"} - %objFifo_in0_cons_cons_lock = aie.lock(%tile_0_1, 1) {init = 0 : i32, sym_name = "objFifo_in0_cons_cons_lock"} + %objFifo_in0_cons_prod_lock = aie.lock(%tile_0_1, 0) {init = 1 : i8, sym_name = "objFifo_in0_cons_prod_lock"} + %objFifo_in0_cons_cons_lock = aie.lock(%tile_0_1, 1) {init = 0 : i8, sym_name = "objFifo_in0_cons_cons_lock"} %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb2, repeat_count = 1) ^bb1: // 2 preds: ^bb0, ^bb1 diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/add_21_i8_using_dma_op_with_padding.mlir b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/add_21_i8_using_dma_op_with_padding.mlir index d307ac0ca..124032d72 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/add_21_i8_using_dma_op_with_padding.mlir +++ b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/add_21_i8_using_dma_op_with_padding.mlir @@ -5,8 +5,8 @@ module { %tile_0_1 = aie.tile(0, 1) %objFifo_in0_cons_buff_0 = aie.buffer(%tile_0_1) {address = 0 : i32, sym_name = "objFifo_in0_cons_buff_0"} : memref<16xi8> %objFifo_in0_cons_buff_1 = aie.buffer(%tile_0_1) {address = 16 : i32, sym_name = "objFifo_in0_cons_buff_1"} : memref<16xi8> - %objFifo_in0_cons_prod_lock = aie.lock(%tile_0_1, 0) {init = 2 : i32, sym_name = "objFifo_in0_cons_prod_lock"} - %objFifo_in0_cons_cons_lock = aie.lock(%tile_0_1, 1) {init = 0 : i32, sym_name = "objFifo_in0_cons_cons_lock"} + %objFifo_in0_cons_prod_lock = aie.lock(%tile_0_1, 0) {init = 2 : i8, sym_name = "objFifo_in0_cons_prod_lock"} + %objFifo_in0_cons_cons_lock = aie.lock(%tile_0_1, 1) {init = 0 : i8, sym_name = "objFifo_in0_cons_cons_lock"} %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3, repeat_count = 1) ^bb1: // pred: ^bb0 diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/add_378_i32_using_dma_op_with_padding.mlir b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/add_378_i32_using_dma_op_with_padding.mlir index 6bfe6cba7..970cc441a 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/add_378_i32_using_dma_op_with_padding.mlir +++ b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/add_378_i32_using_dma_op_with_padding.mlir @@ -5,8 +5,8 @@ module { %tile_0_1 = aie.tile(0, 1) %objFifo_in0_cons_buff_0 = aie.buffer(%tile_0_1) {address = 0 : i32, sym_name = "objFifo_in0_cons_buff_0"} : memref<16xi32> %objFifo_in0_cons_buff_1 = aie.buffer(%tile_0_1) {address = 64 : i32, sym_name = "objFifo_in0_cons_buff_1"} : memref<16xi32> - %objFifo_in0_cons_prod_lock = aie.lock(%tile_0_1, 0) {init = 2 : i32, sym_name = "objFifo_in0_cons_prod_lock"} - %objFifo_in0_cons_cons_lock = aie.lock(%tile_0_1, 1) {init = 0 : i32, sym_name = "objFifo_in0_cons_cons_lock"} + %objFifo_in0_cons_prod_lock = aie.lock(%tile_0_1, 0) {init = 2 : i8, sym_name = "objFifo_in0_cons_prod_lock"} + %objFifo_in0_cons_cons_lock = aie.lock(%tile_0_1, 1) {init = 0 : i8, sym_name = "objFifo_in0_cons_cons_lock"} %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3, repeat_count = 1) ^bb1: // pred: ^bb0 diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/aie_cdo_gen_test.cxx b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/aie_cdo_gen_test.cxx index d73da2e1d..fcc0d39d7 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/aie_cdo_gen_test.cxx +++ b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/aie_cdo_gen_test.cxx @@ -4,10 +4,11 @@ // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +#include #include -#include "aie/Dialect/AIE/IR/AIEDialect.h" -#include "aie/Dialect/AIEX/IR/AIEXDialect.h" +#include "aie/AIEDialect.h" +#include "aie/AIEXDialect.h" #include "iree-amd-aie/Target/AMDAIETargets.h" #include "iree-amd-aie/Target/XCLBinGen.h" #include "llvm/Support/Debug.h" diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_16x16_8xi32__dispatch_0_matmul_16x1_0.aiecc.mlir b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_16x16_8xi32__dispatch_0_matmul_16x1_0.aiecc.mlir index d50db45e3..2c25fb39e 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_16x16_8xi32__dispatch_0_matmul_16x1_0.aiecc.mlir +++ b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_16x16_8xi32__dispatch_0_matmul_16x1_0.aiecc.mlir @@ -7,18 +7,18 @@ aie.device(npu1_4col) { %tile_1_1 = aie.tile(1, 1) %tile_2_1 = aie.tile(2, 1) %tile_0_2 = aie.tile(0, 2) - %lock_1_1 = aie.lock(%tile_1_1, 1) {init = 1 : i32} - %lock_1_1_0 = aie.lock(%tile_1_1, 0) {init = 0 : i32} - %lock_0_1 = aie.lock(%tile_0_1, 1) {init = 1 : i32} - %lock_0_1_1 = aie.lock(%tile_0_1, 0) {init = 0 : i32} - %lock_2_1 = aie.lock(%tile_2_1, 1) {init = 1 : i32} - %lock_2_1_2 = aie.lock(%tile_2_1, 0) {init = 0 : i32} - %lock_0_2 = aie.lock(%tile_0_2, 5) {init = 1 : i32} - %lock_0_2_3 = aie.lock(%tile_0_2, 4) {init = 0 : i32} - %lock_0_2_4 = aie.lock(%tile_0_2, 3) {init = 1 : i32} - %lock_0_2_5 = aie.lock(%tile_0_2, 2) {init = 0 : i32} - %lock_0_2_6 = aie.lock(%tile_0_2, 1) {init = 1 : i32} - %lock_0_2_7 = aie.lock(%tile_0_2, 0) {init = 0 : i32} + %lock_1_1 = aie.lock(%tile_1_1, 1) {init = 1 : i8} + %lock_1_1_0 = aie.lock(%tile_1_1, 0) {init = 0 : i8} + %lock_0_1 = aie.lock(%tile_0_1, 1) {init = 1 : i8} + %lock_0_1_1 = aie.lock(%tile_0_1, 0) {init = 0 : i8} + %lock_2_1 = aie.lock(%tile_2_1, 1) {init = 1 : i8} + %lock_2_1_2 = aie.lock(%tile_2_1, 0) {init = 0 : i8} + %lock_0_2 = aie.lock(%tile_0_2, 5) {init = 1 : i8} + %lock_0_2_3 = aie.lock(%tile_0_2, 4) {init = 0 : i8} + %lock_0_2_4 = aie.lock(%tile_0_2, 3) {init = 1 : i8} + %lock_0_2_5 = aie.lock(%tile_0_2, 2) {init = 0 : i8} + %lock_0_2_6 = aie.lock(%tile_0_2, 1) {init = 1 : i8} + %lock_0_2_7 = aie.lock(%tile_0_2, 0) {init = 0 : i8} %buf5 = aie.buffer(%tile_0_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf5"} : memref<16x8xi32> %buf4 = aie.buffer(%tile_1_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf4"} : memref<8x16xi32> %buf3 = aie.buffer(%tile_2_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf3"} : memref<16x16xi32> @@ -50,49 +50,49 @@ aie.device(npu1_4col) { aie.next_bd ^bb6 } %switchbox_0_0 = aie.switchbox(%tile_0_0) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %shim_mux_0_0 = aie.shim_mux(%tile_0_0) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_0_1 = aie.switchbox(%tile_0_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_1_0 = aie.tile(1, 0) %switchbox_1_0 = aie.switchbox(%tile_1_0) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_1_1 = aie.switchbox(%tile_1_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_2_0 = aie.tile(2, 0) %switchbox_2_0 = aie.switchbox(%tile_2_0) { - aie.connect + aie.connect } %switchbox_2_1 = aie.switchbox(%tile_2_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_0_2 = aie.switchbox(%tile_0_2) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %tile_1_2 = aie.tile(1, 2) %switchbox_1_2 = aie.switchbox(%tile_1_2) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_2_2 = aie.tile(2, 2) %switchbox_2_2 = aie.switchbox(%tile_2_2) { - aie.connect + aie.connect } %memtile_dma_2_1 = aie.memtile_dma(%tile_2_1) { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3, repeat_count = 1) diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_16x64_32xi8__dispatch_0_matmul_tran_0.aiecc.mlir b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_16x64_32xi8__dispatch_0_matmul_tran_0.aiecc.mlir index 2e45df56c..38a4189e6 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_16x64_32xi8__dispatch_0_matmul_tran_0.aiecc.mlir +++ b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_16x64_32xi8__dispatch_0_matmul_tran_0.aiecc.mlir @@ -7,18 +7,18 @@ aie.device(npu1_4col) { %tile_1_1 = aie.tile(1, 1) %tile_2_1 = aie.tile(2, 1) %tile_0_2 = aie.tile(0, 2) - %lock_1_1 = aie.lock(%tile_1_1, 1) {init = 1 : i32} - %lock_1_1_0 = aie.lock(%tile_1_1, 0) {init = 0 : i32} - %lock_0_1 = aie.lock(%tile_0_1, 1) {init = 1 : i32} - %lock_0_1_1 = aie.lock(%tile_0_1, 0) {init = 0 : i32} - %lock_2_1 = aie.lock(%tile_2_1, 1) {init = 1 : i32} - %lock_2_1_2 = aie.lock(%tile_2_1, 0) {init = 0 : i32} - %lock_0_2 = aie.lock(%tile_0_2, 5) {init = 1 : i32} - %lock_0_2_3 = aie.lock(%tile_0_2, 4) {init = 0 : i32} - %lock_0_2_4 = aie.lock(%tile_0_2, 3) {init = 1 : i32} - %lock_0_2_5 = aie.lock(%tile_0_2, 2) {init = 0 : i32} - %lock_0_2_6 = aie.lock(%tile_0_2, 1) {init = 1 : i32} - %lock_0_2_7 = aie.lock(%tile_0_2, 0) {init = 0 : i32} + %lock_1_1 = aie.lock(%tile_1_1, 1) {init = 1 : i8} + %lock_1_1_0 = aie.lock(%tile_1_1, 0) {init = 0 : i8} + %lock_0_1 = aie.lock(%tile_0_1, 1) {init = 1 : i8} + %lock_0_1_1 = aie.lock(%tile_0_1, 0) {init = 0 : i8} + %lock_2_1 = aie.lock(%tile_2_1, 1) {init = 1 : i8} + %lock_2_1_2 = aie.lock(%tile_2_1, 0) {init = 0 : i8} + %lock_0_2 = aie.lock(%tile_0_2, 5) {init = 1 : i8} + %lock_0_2_3 = aie.lock(%tile_0_2, 4) {init = 0 : i8} + %lock_0_2_4 = aie.lock(%tile_0_2, 3) {init = 1 : i8} + %lock_0_2_5 = aie.lock(%tile_0_2, 2) {init = 0 : i8} + %lock_0_2_6 = aie.lock(%tile_0_2, 1) {init = 1 : i8} + %lock_0_2_7 = aie.lock(%tile_0_2, 0) {init = 0 : i8} %buf5 = aie.buffer(%tile_0_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf5"} : memref<16x64xi8> %buf4 = aie.buffer(%tile_1_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf4"} : memref<32x64xi8> %buf3 = aie.buffer(%tile_2_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf3"} : memref<16x32xi32> @@ -50,49 +50,49 @@ aie.device(npu1_4col) { aie.next_bd ^bb6 } %switchbox_0_0 = aie.switchbox(%tile_0_0) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %shim_mux_0_0 = aie.shim_mux(%tile_0_0) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_0_1 = aie.switchbox(%tile_0_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_1_0 = aie.tile(1, 0) %switchbox_1_0 = aie.switchbox(%tile_1_0) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_1_1 = aie.switchbox(%tile_1_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_2_0 = aie.tile(2, 0) %switchbox_2_0 = aie.switchbox(%tile_2_0) { - aie.connect + aie.connect } %switchbox_2_1 = aie.switchbox(%tile_2_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_0_2 = aie.switchbox(%tile_0_2) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %tile_1_2 = aie.tile(1, 2) %switchbox_1_2 = aie.switchbox(%tile_1_2) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_2_2 = aie.tile(2, 2) %switchbox_2_2 = aie.switchbox(%tile_2_2) { - aie.connect + aie.connect } %memtile_dma_2_1 = aie.memtile_dma(%tile_2_1) { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3, repeat_count = 1) diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_512x512_512xi32__dispatch_0_matmul__0.aiecc.mlir b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_512x512_512xi32__dispatch_0_matmul__0.aiecc.mlir index 1a69613f0..099b66f48 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_512x512_512xi32__dispatch_0_matmul__0.aiecc.mlir +++ b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_512x512_512xi32__dispatch_0_matmul__0.aiecc.mlir @@ -26,142 +26,142 @@ aie.device(npu1_4col) { %tile_1_5 = aie.tile(1, 5) %tile_2_5 = aie.tile(2, 5) %tile_3_5 = aie.tile(3, 5) - %lock_3_1 = aie.lock(%tile_3_1, 9) {init = 4 : i32} - %lock_3_1_0 = aie.lock(%tile_3_1, 8) {init = 0 : i32} - %lock_3_1_1 = aie.lock(%tile_3_1, 7) {init = 1 : i32} - %lock_3_1_2 = aie.lock(%tile_3_1, 6) {init = 0 : i32} - %lock_3_1_3 = aie.lock(%tile_3_1, 5) {init = 1 : i32} - %lock_3_1_4 = aie.lock(%tile_3_1, 4) {init = 0 : i32} - %lock_3_1_5 = aie.lock(%tile_3_1, 3) {init = 1 : i32} - %lock_3_1_6 = aie.lock(%tile_3_1, 2) {init = 0 : i32} - %lock_3_1_7 = aie.lock(%tile_3_1, 1) {init = 1 : i32} - %lock_3_1_8 = aie.lock(%tile_3_1, 0) {init = 0 : i32} - %lock_2_1 = aie.lock(%tile_2_1, 9) {init = 4 : i32} - %lock_2_1_9 = aie.lock(%tile_2_1, 8) {init = 0 : i32} - %lock_2_1_10 = aie.lock(%tile_2_1, 7) {init = 1 : i32} - %lock_2_1_11 = aie.lock(%tile_2_1, 6) {init = 0 : i32} - %lock_2_1_12 = aie.lock(%tile_2_1, 5) {init = 1 : i32} - %lock_2_1_13 = aie.lock(%tile_2_1, 4) {init = 0 : i32} - %lock_2_1_14 = aie.lock(%tile_2_1, 3) {init = 1 : i32} - %lock_2_1_15 = aie.lock(%tile_2_1, 2) {init = 0 : i32} - %lock_2_1_16 = aie.lock(%tile_2_1, 1) {init = 1 : i32} - %lock_2_1_17 = aie.lock(%tile_2_1, 0) {init = 0 : i32} - %lock_1_1 = aie.lock(%tile_1_1, 9) {init = 4 : i32} - %lock_1_1_18 = aie.lock(%tile_1_1, 8) {init = 0 : i32} - %lock_1_1_19 = aie.lock(%tile_1_1, 7) {init = 1 : i32} - %lock_1_1_20 = aie.lock(%tile_1_1, 6) {init = 0 : i32} - %lock_1_1_21 = aie.lock(%tile_1_1, 5) {init = 1 : i32} - %lock_1_1_22 = aie.lock(%tile_1_1, 4) {init = 0 : i32} - %lock_1_1_23 = aie.lock(%tile_1_1, 3) {init = 1 : i32} - %lock_1_1_24 = aie.lock(%tile_1_1, 2) {init = 0 : i32} - %lock_1_1_25 = aie.lock(%tile_1_1, 1) {init = 1 : i32} - %lock_1_1_26 = aie.lock(%tile_1_1, 0) {init = 0 : i32} - %lock_0_1 = aie.lock(%tile_0_1, 9) {init = 4 : i32} - %lock_0_1_27 = aie.lock(%tile_0_1, 8) {init = 0 : i32} - %lock_0_1_28 = aie.lock(%tile_0_1, 7) {init = 1 : i32} - %lock_0_1_29 = aie.lock(%tile_0_1, 6) {init = 0 : i32} - %lock_0_1_30 = aie.lock(%tile_0_1, 5) {init = 1 : i32} - %lock_0_1_31 = aie.lock(%tile_0_1, 4) {init = 0 : i32} - %lock_0_1_32 = aie.lock(%tile_0_1, 3) {init = 1 : i32} - %lock_0_1_33 = aie.lock(%tile_0_1, 2) {init = 0 : i32} - %lock_0_1_34 = aie.lock(%tile_0_1, 1) {init = 1 : i32} - %lock_0_1_35 = aie.lock(%tile_0_1, 0) {init = 0 : i32} - %lock_0_2 = aie.lock(%tile_0_2, 5) {init = 2 : i32} - %lock_0_2_36 = aie.lock(%tile_0_2, 4) {init = 0 : i32} - %lock_0_2_37 = aie.lock(%tile_0_2, 3) {init = 2 : i32} - %lock_0_2_38 = aie.lock(%tile_0_2, 2) {init = 0 : i32} - %lock_0_2_39 = aie.lock(%tile_0_2, 1) {init = 1 : i32} - %lock_0_2_40 = aie.lock(%tile_0_2, 0) {init = 0 : i32} - %lock_1_2 = aie.lock(%tile_1_2, 5) {init = 2 : i32} - %lock_1_2_41 = aie.lock(%tile_1_2, 4) {init = 0 : i32} - %lock_1_2_42 = aie.lock(%tile_1_2, 3) {init = 2 : i32} - %lock_1_2_43 = aie.lock(%tile_1_2, 2) {init = 0 : i32} - %lock_1_2_44 = aie.lock(%tile_1_2, 1) {init = 1 : i32} - %lock_1_2_45 = aie.lock(%tile_1_2, 0) {init = 0 : i32} - %lock_2_2 = aie.lock(%tile_2_2, 5) {init = 2 : i32} - %lock_2_2_46 = aie.lock(%tile_2_2, 4) {init = 0 : i32} - %lock_2_2_47 = aie.lock(%tile_2_2, 3) {init = 2 : i32} - %lock_2_2_48 = aie.lock(%tile_2_2, 2) {init = 0 : i32} - %lock_2_2_49 = aie.lock(%tile_2_2, 1) {init = 1 : i32} - %lock_2_2_50 = aie.lock(%tile_2_2, 0) {init = 0 : i32} - %lock_3_2 = aie.lock(%tile_3_2, 5) {init = 2 : i32} - %lock_3_2_51 = aie.lock(%tile_3_2, 4) {init = 0 : i32} - %lock_3_2_52 = aie.lock(%tile_3_2, 3) {init = 2 : i32} - %lock_3_2_53 = aie.lock(%tile_3_2, 2) {init = 0 : i32} - %lock_3_2_54 = aie.lock(%tile_3_2, 1) {init = 1 : i32} - %lock_3_2_55 = aie.lock(%tile_3_2, 0) {init = 0 : i32} - %lock_0_3 = aie.lock(%tile_0_3, 5) {init = 2 : i32} - %lock_0_3_56 = aie.lock(%tile_0_3, 4) {init = 0 : i32} - %lock_0_3_57 = aie.lock(%tile_0_3, 3) {init = 2 : i32} - %lock_0_3_58 = aie.lock(%tile_0_3, 2) {init = 0 : i32} - %lock_0_3_59 = aie.lock(%tile_0_3, 1) {init = 1 : i32} - %lock_0_3_60 = aie.lock(%tile_0_3, 0) {init = 0 : i32} - %lock_1_3 = aie.lock(%tile_1_3, 5) {init = 2 : i32} - %lock_1_3_61 = aie.lock(%tile_1_3, 4) {init = 0 : i32} - %lock_1_3_62 = aie.lock(%tile_1_3, 3) {init = 2 : i32} - %lock_1_3_63 = aie.lock(%tile_1_3, 2) {init = 0 : i32} - %lock_1_3_64 = aie.lock(%tile_1_3, 1) {init = 1 : i32} - %lock_1_3_65 = aie.lock(%tile_1_3, 0) {init = 0 : i32} - %lock_2_3 = aie.lock(%tile_2_3, 5) {init = 2 : i32} - %lock_2_3_66 = aie.lock(%tile_2_3, 4) {init = 0 : i32} - %lock_2_3_67 = aie.lock(%tile_2_3, 3) {init = 2 : i32} - %lock_2_3_68 = aie.lock(%tile_2_3, 2) {init = 0 : i32} - %lock_2_3_69 = aie.lock(%tile_2_3, 1) {init = 1 : i32} - %lock_2_3_70 = aie.lock(%tile_2_3, 0) {init = 0 : i32} - %lock_3_3 = aie.lock(%tile_3_3, 5) {init = 2 : i32} - %lock_3_3_71 = aie.lock(%tile_3_3, 4) {init = 0 : i32} - %lock_3_3_72 = aie.lock(%tile_3_3, 3) {init = 2 : i32} - %lock_3_3_73 = aie.lock(%tile_3_3, 2) {init = 0 : i32} - %lock_3_3_74 = aie.lock(%tile_3_3, 1) {init = 1 : i32} - %lock_3_3_75 = aie.lock(%tile_3_3, 0) {init = 0 : i32} - %lock_0_4 = aie.lock(%tile_0_4, 5) {init = 2 : i32} - %lock_0_4_76 = aie.lock(%tile_0_4, 4) {init = 0 : i32} - %lock_0_4_77 = aie.lock(%tile_0_4, 3) {init = 2 : i32} - %lock_0_4_78 = aie.lock(%tile_0_4, 2) {init = 0 : i32} - %lock_0_4_79 = aie.lock(%tile_0_4, 1) {init = 1 : i32} - %lock_0_4_80 = aie.lock(%tile_0_4, 0) {init = 0 : i32} - %lock_1_4 = aie.lock(%tile_1_4, 5) {init = 2 : i32} - %lock_1_4_81 = aie.lock(%tile_1_4, 4) {init = 0 : i32} - %lock_1_4_82 = aie.lock(%tile_1_4, 3) {init = 2 : i32} - %lock_1_4_83 = aie.lock(%tile_1_4, 2) {init = 0 : i32} - %lock_1_4_84 = aie.lock(%tile_1_4, 1) {init = 1 : i32} - %lock_1_4_85 = aie.lock(%tile_1_4, 0) {init = 0 : i32} - %lock_2_4 = aie.lock(%tile_2_4, 5) {init = 2 : i32} - %lock_2_4_86 = aie.lock(%tile_2_4, 4) {init = 0 : i32} - %lock_2_4_87 = aie.lock(%tile_2_4, 3) {init = 2 : i32} - %lock_2_4_88 = aie.lock(%tile_2_4, 2) {init = 0 : i32} - %lock_2_4_89 = aie.lock(%tile_2_4, 1) {init = 1 : i32} - %lock_2_4_90 = aie.lock(%tile_2_4, 0) {init = 0 : i32} - %lock_3_4 = aie.lock(%tile_3_4, 5) {init = 2 : i32} - %lock_3_4_91 = aie.lock(%tile_3_4, 4) {init = 0 : i32} - %lock_3_4_92 = aie.lock(%tile_3_4, 3) {init = 2 : i32} - %lock_3_4_93 = aie.lock(%tile_3_4, 2) {init = 0 : i32} - %lock_3_4_94 = aie.lock(%tile_3_4, 1) {init = 1 : i32} - %lock_3_4_95 = aie.lock(%tile_3_4, 0) {init = 0 : i32} - %lock_0_5 = aie.lock(%tile_0_5, 5) {init = 2 : i32} - %lock_0_5_96 = aie.lock(%tile_0_5, 4) {init = 0 : i32} - %lock_0_5_97 = aie.lock(%tile_0_5, 3) {init = 2 : i32} - %lock_0_5_98 = aie.lock(%tile_0_5, 2) {init = 0 : i32} - %lock_0_5_99 = aie.lock(%tile_0_5, 1) {init = 1 : i32} - %lock_0_5_100 = aie.lock(%tile_0_5, 0) {init = 0 : i32} - %lock_1_5 = aie.lock(%tile_1_5, 5) {init = 2 : i32} - %lock_1_5_101 = aie.lock(%tile_1_5, 4) {init = 0 : i32} - %lock_1_5_102 = aie.lock(%tile_1_5, 3) {init = 2 : i32} - %lock_1_5_103 = aie.lock(%tile_1_5, 2) {init = 0 : i32} - %lock_1_5_104 = aie.lock(%tile_1_5, 1) {init = 1 : i32} - %lock_1_5_105 = aie.lock(%tile_1_5, 0) {init = 0 : i32} - %lock_2_5 = aie.lock(%tile_2_5, 5) {init = 2 : i32} - %lock_2_5_106 = aie.lock(%tile_2_5, 4) {init = 0 : i32} - %lock_2_5_107 = aie.lock(%tile_2_5, 3) {init = 2 : i32} - %lock_2_5_108 = aie.lock(%tile_2_5, 2) {init = 0 : i32} - %lock_2_5_109 = aie.lock(%tile_2_5, 1) {init = 1 : i32} - %lock_2_5_110 = aie.lock(%tile_2_5, 0) {init = 0 : i32} - %lock_3_5 = aie.lock(%tile_3_5, 5) {init = 2 : i32} - %lock_3_5_111 = aie.lock(%tile_3_5, 4) {init = 0 : i32} - %lock_3_5_112 = aie.lock(%tile_3_5, 3) {init = 2 : i32} - %lock_3_5_113 = aie.lock(%tile_3_5, 2) {init = 0 : i32} - %lock_3_5_114 = aie.lock(%tile_3_5, 1) {init = 1 : i32} - %lock_3_5_115 = aie.lock(%tile_3_5, 0) {init = 0 : i32} + %lock_3_1 = aie.lock(%tile_3_1, 9) {init = 4 : i8} + %lock_3_1_0 = aie.lock(%tile_3_1, 8) {init = 0 : i8} + %lock_3_1_1 = aie.lock(%tile_3_1, 7) {init = 1 : i8} + %lock_3_1_2 = aie.lock(%tile_3_1, 6) {init = 0 : i8} + %lock_3_1_3 = aie.lock(%tile_3_1, 5) {init = 1 : i8} + %lock_3_1_4 = aie.lock(%tile_3_1, 4) {init = 0 : i8} + %lock_3_1_5 = aie.lock(%tile_3_1, 3) {init = 1 : i8} + %lock_3_1_6 = aie.lock(%tile_3_1, 2) {init = 0 : i8} + %lock_3_1_7 = aie.lock(%tile_3_1, 1) {init = 1 : i8} + %lock_3_1_8 = aie.lock(%tile_3_1, 0) {init = 0 : i8} + %lock_2_1 = aie.lock(%tile_2_1, 9) {init = 4 : i8} + %lock_2_1_9 = aie.lock(%tile_2_1, 8) {init = 0 : i8} + %lock_2_1_10 = aie.lock(%tile_2_1, 7) {init = 1 : i8} + %lock_2_1_11 = aie.lock(%tile_2_1, 6) {init = 0 : i8} + %lock_2_1_12 = aie.lock(%tile_2_1, 5) {init = 1 : i8} + %lock_2_1_13 = aie.lock(%tile_2_1, 4) {init = 0 : i8} + %lock_2_1_14 = aie.lock(%tile_2_1, 3) {init = 1 : i8} + %lock_2_1_15 = aie.lock(%tile_2_1, 2) {init = 0 : i8} + %lock_2_1_16 = aie.lock(%tile_2_1, 1) {init = 1 : i8} + %lock_2_1_17 = aie.lock(%tile_2_1, 0) {init = 0 : i8} + %lock_1_1 = aie.lock(%tile_1_1, 9) {init = 4 : i8} + %lock_1_1_18 = aie.lock(%tile_1_1, 8) {init = 0 : i8} + %lock_1_1_19 = aie.lock(%tile_1_1, 7) {init = 1 : i8} + %lock_1_1_20 = aie.lock(%tile_1_1, 6) {init = 0 : i8} + %lock_1_1_21 = aie.lock(%tile_1_1, 5) {init = 1 : i8} + %lock_1_1_22 = aie.lock(%tile_1_1, 4) {init = 0 : i8} + %lock_1_1_23 = aie.lock(%tile_1_1, 3) {init = 1 : i8} + %lock_1_1_24 = aie.lock(%tile_1_1, 2) {init = 0 : i8} + %lock_1_1_25 = aie.lock(%tile_1_1, 1) {init = 1 : i8} + %lock_1_1_26 = aie.lock(%tile_1_1, 0) {init = 0 : i8} + %lock_0_1 = aie.lock(%tile_0_1, 9) {init = 4 : i8} + %lock_0_1_27 = aie.lock(%tile_0_1, 8) {init = 0 : i8} + %lock_0_1_28 = aie.lock(%tile_0_1, 7) {init = 1 : i8} + %lock_0_1_29 = aie.lock(%tile_0_1, 6) {init = 0 : i8} + %lock_0_1_30 = aie.lock(%tile_0_1, 5) {init = 1 : i8} + %lock_0_1_31 = aie.lock(%tile_0_1, 4) {init = 0 : i8} + %lock_0_1_32 = aie.lock(%tile_0_1, 3) {init = 1 : i8} + %lock_0_1_33 = aie.lock(%tile_0_1, 2) {init = 0 : i8} + %lock_0_1_34 = aie.lock(%tile_0_1, 1) {init = 1 : i8} + %lock_0_1_35 = aie.lock(%tile_0_1, 0) {init = 0 : i8} + %lock_0_2 = aie.lock(%tile_0_2, 5) {init = 2 : i8} + %lock_0_2_36 = aie.lock(%tile_0_2, 4) {init = 0 : i8} + %lock_0_2_37 = aie.lock(%tile_0_2, 3) {init = 2 : i8} + %lock_0_2_38 = aie.lock(%tile_0_2, 2) {init = 0 : i8} + %lock_0_2_39 = aie.lock(%tile_0_2, 1) {init = 1 : i8} + %lock_0_2_40 = aie.lock(%tile_0_2, 0) {init = 0 : i8} + %lock_1_2 = aie.lock(%tile_1_2, 5) {init = 2 : i8} + %lock_1_2_41 = aie.lock(%tile_1_2, 4) {init = 0 : i8} + %lock_1_2_42 = aie.lock(%tile_1_2, 3) {init = 2 : i8} + %lock_1_2_43 = aie.lock(%tile_1_2, 2) {init = 0 : i8} + %lock_1_2_44 = aie.lock(%tile_1_2, 1) {init = 1 : i8} + %lock_1_2_45 = aie.lock(%tile_1_2, 0) {init = 0 : i8} + %lock_2_2 = aie.lock(%tile_2_2, 5) {init = 2 : i8} + %lock_2_2_46 = aie.lock(%tile_2_2, 4) {init = 0 : i8} + %lock_2_2_47 = aie.lock(%tile_2_2, 3) {init = 2 : i8} + %lock_2_2_48 = aie.lock(%tile_2_2, 2) {init = 0 : i8} + %lock_2_2_49 = aie.lock(%tile_2_2, 1) {init = 1 : i8} + %lock_2_2_50 = aie.lock(%tile_2_2, 0) {init = 0 : i8} + %lock_3_2 = aie.lock(%tile_3_2, 5) {init = 2 : i8} + %lock_3_2_51 = aie.lock(%tile_3_2, 4) {init = 0 : i8} + %lock_3_2_52 = aie.lock(%tile_3_2, 3) {init = 2 : i8} + %lock_3_2_53 = aie.lock(%tile_3_2, 2) {init = 0 : i8} + %lock_3_2_54 = aie.lock(%tile_3_2, 1) {init = 1 : i8} + %lock_3_2_55 = aie.lock(%tile_3_2, 0) {init = 0 : i8} + %lock_0_3 = aie.lock(%tile_0_3, 5) {init = 2 : i8} + %lock_0_3_56 = aie.lock(%tile_0_3, 4) {init = 0 : i8} + %lock_0_3_57 = aie.lock(%tile_0_3, 3) {init = 2 : i8} + %lock_0_3_58 = aie.lock(%tile_0_3, 2) {init = 0 : i8} + %lock_0_3_59 = aie.lock(%tile_0_3, 1) {init = 1 : i8} + %lock_0_3_60 = aie.lock(%tile_0_3, 0) {init = 0 : i8} + %lock_1_3 = aie.lock(%tile_1_3, 5) {init = 2 : i8} + %lock_1_3_61 = aie.lock(%tile_1_3, 4) {init = 0 : i8} + %lock_1_3_62 = aie.lock(%tile_1_3, 3) {init = 2 : i8} + %lock_1_3_63 = aie.lock(%tile_1_3, 2) {init = 0 : i8} + %lock_1_3_64 = aie.lock(%tile_1_3, 1) {init = 1 : i8} + %lock_1_3_65 = aie.lock(%tile_1_3, 0) {init = 0 : i8} + %lock_2_3 = aie.lock(%tile_2_3, 5) {init = 2 : i8} + %lock_2_3_66 = aie.lock(%tile_2_3, 4) {init = 0 : i8} + %lock_2_3_67 = aie.lock(%tile_2_3, 3) {init = 2 : i8} + %lock_2_3_68 = aie.lock(%tile_2_3, 2) {init = 0 : i8} + %lock_2_3_69 = aie.lock(%tile_2_3, 1) {init = 1 : i8} + %lock_2_3_70 = aie.lock(%tile_2_3, 0) {init = 0 : i8} + %lock_3_3 = aie.lock(%tile_3_3, 5) {init = 2 : i8} + %lock_3_3_71 = aie.lock(%tile_3_3, 4) {init = 0 : i8} + %lock_3_3_72 = aie.lock(%tile_3_3, 3) {init = 2 : i8} + %lock_3_3_73 = aie.lock(%tile_3_3, 2) {init = 0 : i8} + %lock_3_3_74 = aie.lock(%tile_3_3, 1) {init = 1 : i8} + %lock_3_3_75 = aie.lock(%tile_3_3, 0) {init = 0 : i8} + %lock_0_4 = aie.lock(%tile_0_4, 5) {init = 2 : i8} + %lock_0_4_76 = aie.lock(%tile_0_4, 4) {init = 0 : i8} + %lock_0_4_77 = aie.lock(%tile_0_4, 3) {init = 2 : i8} + %lock_0_4_78 = aie.lock(%tile_0_4, 2) {init = 0 : i8} + %lock_0_4_79 = aie.lock(%tile_0_4, 1) {init = 1 : i8} + %lock_0_4_80 = aie.lock(%tile_0_4, 0) {init = 0 : i8} + %lock_1_4 = aie.lock(%tile_1_4, 5) {init = 2 : i8} + %lock_1_4_81 = aie.lock(%tile_1_4, 4) {init = 0 : i8} + %lock_1_4_82 = aie.lock(%tile_1_4, 3) {init = 2 : i8} + %lock_1_4_83 = aie.lock(%tile_1_4, 2) {init = 0 : i8} + %lock_1_4_84 = aie.lock(%tile_1_4, 1) {init = 1 : i8} + %lock_1_4_85 = aie.lock(%tile_1_4, 0) {init = 0 : i8} + %lock_2_4 = aie.lock(%tile_2_4, 5) {init = 2 : i8} + %lock_2_4_86 = aie.lock(%tile_2_4, 4) {init = 0 : i8} + %lock_2_4_87 = aie.lock(%tile_2_4, 3) {init = 2 : i8} + %lock_2_4_88 = aie.lock(%tile_2_4, 2) {init = 0 : i8} + %lock_2_4_89 = aie.lock(%tile_2_4, 1) {init = 1 : i8} + %lock_2_4_90 = aie.lock(%tile_2_4, 0) {init = 0 : i8} + %lock_3_4 = aie.lock(%tile_3_4, 5) {init = 2 : i8} + %lock_3_4_91 = aie.lock(%tile_3_4, 4) {init = 0 : i8} + %lock_3_4_92 = aie.lock(%tile_3_4, 3) {init = 2 : i8} + %lock_3_4_93 = aie.lock(%tile_3_4, 2) {init = 0 : i8} + %lock_3_4_94 = aie.lock(%tile_3_4, 1) {init = 1 : i8} + %lock_3_4_95 = aie.lock(%tile_3_4, 0) {init = 0 : i8} + %lock_0_5 = aie.lock(%tile_0_5, 5) {init = 2 : i8} + %lock_0_5_96 = aie.lock(%tile_0_5, 4) {init = 0 : i8} + %lock_0_5_97 = aie.lock(%tile_0_5, 3) {init = 2 : i8} + %lock_0_5_98 = aie.lock(%tile_0_5, 2) {init = 0 : i8} + %lock_0_5_99 = aie.lock(%tile_0_5, 1) {init = 1 : i8} + %lock_0_5_100 = aie.lock(%tile_0_5, 0) {init = 0 : i8} + %lock_1_5 = aie.lock(%tile_1_5, 5) {init = 2 : i8} + %lock_1_5_101 = aie.lock(%tile_1_5, 4) {init = 0 : i8} + %lock_1_5_102 = aie.lock(%tile_1_5, 3) {init = 2 : i8} + %lock_1_5_103 = aie.lock(%tile_1_5, 2) {init = 0 : i8} + %lock_1_5_104 = aie.lock(%tile_1_5, 1) {init = 1 : i8} + %lock_1_5_105 = aie.lock(%tile_1_5, 0) {init = 0 : i8} + %lock_2_5 = aie.lock(%tile_2_5, 5) {init = 2 : i8} + %lock_2_5_106 = aie.lock(%tile_2_5, 4) {init = 0 : i8} + %lock_2_5_107 = aie.lock(%tile_2_5, 3) {init = 2 : i8} + %lock_2_5_108 = aie.lock(%tile_2_5, 2) {init = 0 : i8} + %lock_2_5_109 = aie.lock(%tile_2_5, 1) {init = 1 : i8} + %lock_2_5_110 = aie.lock(%tile_2_5, 0) {init = 0 : i8} + %lock_3_5 = aie.lock(%tile_3_5, 5) {init = 2 : i8} + %lock_3_5_111 = aie.lock(%tile_3_5, 4) {init = 0 : i8} + %lock_3_5_112 = aie.lock(%tile_3_5, 3) {init = 2 : i8} + %lock_3_5_113 = aie.lock(%tile_3_5, 2) {init = 0 : i8} + %lock_3_5_114 = aie.lock(%tile_3_5, 1) {init = 1 : i8} + %lock_3_5_115 = aie.lock(%tile_3_5, 0) {init = 0 : i8} %buf99 = aie.buffer(%tile_0_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf99"} : memref<32x256xi32> %buf98 = aie.buffer(%tile_1_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf98"} : memref<32x256xi32> %buf97 = aie.buffer(%tile_2_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf97"} : memref<32x256xi32> @@ -807,238 +807,238 @@ aie.device(npu1_4col) { aie.next_bd ^bb8 } %switchbox_0_0 = aie.switchbox(%tile_0_0) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %shim_mux_0_0 = aie.shim_mux(%tile_0_0) { - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_0_1 = aie.switchbox(%tile_0_1) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_1_0 = aie.switchbox(%tile_1_0) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_1_1 = aie.switchbox(%tile_1_1) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %shim_mux_1_0 = aie.shim_mux(%tile_1_0) { - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_2_0 = aie.switchbox(%tile_2_0) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_2_1 = aie.switchbox(%tile_2_1) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_3_0 = aie.switchbox(%tile_3_0) { - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_3_1 = aie.switchbox(%tile_3_1) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %shim_mux_2_0 = aie.shim_mux(%tile_2_0) { - aie.connect - aie.connect + aie.connect + aie.connect } %shim_mux_3_0 = aie.shim_mux(%tile_3_0) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_0_2 = aie.switchbox(%tile_0_2) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_0_3 = aie.switchbox(%tile_0_3) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_0_4 = aie.switchbox(%tile_0_4) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_0_5 = aie.switchbox(%tile_0_5) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_1_2 = aie.switchbox(%tile_1_2) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_1_3 = aie.switchbox(%tile_1_3) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_1_4 = aie.switchbox(%tile_1_4) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_1_5 = aie.switchbox(%tile_1_5) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_2_2 = aie.switchbox(%tile_2_2) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_2_3 = aie.switchbox(%tile_2_3) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_2_4 = aie.switchbox(%tile_2_4) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_2_5 = aie.switchbox(%tile_2_5) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_3_2 = aie.switchbox(%tile_3_2) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_3_3 = aie.switchbox(%tile_3_3) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_3_4 = aie.switchbox(%tile_3_4) { - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_3_5 = aie.switchbox(%tile_3_5) { - aie.connect - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect + aie.connect } %memtile_dma_0_1 = aie.memtile_dma(%tile_0_1) { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb20, repeat_count = 1) diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_64x64_64xbf16__dispatch_0_matmul_64_0.aiecc.mlir b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_64x64_64xbf16__dispatch_0_matmul_64_0.aiecc.mlir index f50c6cc58..a62b69848 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_64x64_64xbf16__dispatch_0_matmul_64_0.aiecc.mlir +++ b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_64x64_64xbf16__dispatch_0_matmul_64_0.aiecc.mlir @@ -7,18 +7,18 @@ aie.device(npu1_4col) { %tile_1_1 = aie.tile(1, 1) %tile_2_1 = aie.tile(2, 1) %tile_0_2 = aie.tile(0, 2) - %lock_1_1 = aie.lock(%tile_1_1, 1) {init = 1 : i32} - %lock_1_1_0 = aie.lock(%tile_1_1, 0) {init = 0 : i32} - %lock_0_1 = aie.lock(%tile_0_1, 1) {init = 1 : i32} - %lock_0_1_1 = aie.lock(%tile_0_1, 0) {init = 0 : i32} - %lock_2_1 = aie.lock(%tile_2_1, 1) {init = 1 : i32} - %lock_2_1_2 = aie.lock(%tile_2_1, 0) {init = 0 : i32} - %lock_0_2 = aie.lock(%tile_0_2, 5) {init = 1 : i32} - %lock_0_2_3 = aie.lock(%tile_0_2, 4) {init = 0 : i32} - %lock_0_2_4 = aie.lock(%tile_0_2, 3) {init = 1 : i32} - %lock_0_2_5 = aie.lock(%tile_0_2, 2) {init = 0 : i32} - %lock_0_2_6 = aie.lock(%tile_0_2, 1) {init = 1 : i32} - %lock_0_2_7 = aie.lock(%tile_0_2, 0) {init = 0 : i32} + %lock_1_1 = aie.lock(%tile_1_1, 1) {init = 1 : i8} + %lock_1_1_0 = aie.lock(%tile_1_1, 0) {init = 0 : i8} + %lock_0_1 = aie.lock(%tile_0_1, 1) {init = 1 : i8} + %lock_0_1_1 = aie.lock(%tile_0_1, 0) {init = 0 : i8} + %lock_2_1 = aie.lock(%tile_2_1, 1) {init = 1 : i8} + %lock_2_1_2 = aie.lock(%tile_2_1, 0) {init = 0 : i8} + %lock_0_2 = aie.lock(%tile_0_2, 5) {init = 1 : i8} + %lock_0_2_3 = aie.lock(%tile_0_2, 4) {init = 0 : i8} + %lock_0_2_4 = aie.lock(%tile_0_2, 3) {init = 1 : i8} + %lock_0_2_5 = aie.lock(%tile_0_2, 2) {init = 0 : i8} + %lock_0_2_6 = aie.lock(%tile_0_2, 1) {init = 1 : i8} + %lock_0_2_7 = aie.lock(%tile_0_2, 0) {init = 0 : i8} %buf5 = aie.buffer(%tile_0_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf5"} : memref<64x64xbf16> %buf4 = aie.buffer(%tile_1_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf4"} : memref<64x64xbf16> %buf3 = aie.buffer(%tile_2_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf3"} : memref<64x64xf32> @@ -50,49 +50,49 @@ aie.device(npu1_4col) { aie.next_bd ^bb6 } %switchbox_0_0 = aie.switchbox(%tile_0_0) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %shim_mux_0_0 = aie.shim_mux(%tile_0_0) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_0_1 = aie.switchbox(%tile_0_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_1_0 = aie.tile(1, 0) %switchbox_1_0 = aie.switchbox(%tile_1_0) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_1_1 = aie.switchbox(%tile_1_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_2_0 = aie.tile(2, 0) %switchbox_2_0 = aie.switchbox(%tile_2_0) { - aie.connect + aie.connect } %switchbox_2_1 = aie.switchbox(%tile_2_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_0_2 = aie.switchbox(%tile_0_2) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %tile_1_2 = aie.tile(1, 2) %switchbox_1_2 = aie.switchbox(%tile_1_2) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_2_2 = aie.tile(2, 2) %switchbox_2_2 = aie.switchbox(%tile_2_2) { - aie.connect + aie.connect } %memtile_dma_2_1 = aie.memtile_dma(%tile_2_1) { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3, repeat_count = 1) diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_64x64_64xi8__dispatch_0_matmul_64x6_0.aiecc.mlir b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_64x64_64xi8__dispatch_0_matmul_64x6_0.aiecc.mlir index 00f59c5c0..c1e980539 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_64x64_64xi8__dispatch_0_matmul_64x6_0.aiecc.mlir +++ b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_64x64_64xi8__dispatch_0_matmul_64x6_0.aiecc.mlir @@ -7,18 +7,18 @@ aie.device(npu1_4col) { %tile_1_1 = aie.tile(1, 1) %tile_2_1 = aie.tile(2, 1) %tile_0_2 = aie.tile(0, 2) - %lock_1_1 = aie.lock(%tile_1_1, 1) {init = 1 : i32} - %lock_1_1_0 = aie.lock(%tile_1_1, 0) {init = 0 : i32} - %lock_0_1 = aie.lock(%tile_0_1, 1) {init = 1 : i32} - %lock_0_1_1 = aie.lock(%tile_0_1, 0) {init = 0 : i32} - %lock_2_1 = aie.lock(%tile_2_1, 1) {init = 1 : i32} - %lock_2_1_2 = aie.lock(%tile_2_1, 0) {init = 0 : i32} - %lock_0_2 = aie.lock(%tile_0_2, 5) {init = 1 : i32} - %lock_0_2_3 = aie.lock(%tile_0_2, 4) {init = 0 : i32} - %lock_0_2_4 = aie.lock(%tile_0_2, 3) {init = 1 : i32} - %lock_0_2_5 = aie.lock(%tile_0_2, 2) {init = 0 : i32} - %lock_0_2_6 = aie.lock(%tile_0_2, 1) {init = 1 : i32} - %lock_0_2_7 = aie.lock(%tile_0_2, 0) {init = 0 : i32} + %lock_1_1 = aie.lock(%tile_1_1, 1) {init = 1 : i8} + %lock_1_1_0 = aie.lock(%tile_1_1, 0) {init = 0 : i8} + %lock_0_1 = aie.lock(%tile_0_1, 1) {init = 1 : i8} + %lock_0_1_1 = aie.lock(%tile_0_1, 0) {init = 0 : i8} + %lock_2_1 = aie.lock(%tile_2_1, 1) {init = 1 : i8} + %lock_2_1_2 = aie.lock(%tile_2_1, 0) {init = 0 : i8} + %lock_0_2 = aie.lock(%tile_0_2, 5) {init = 1 : i8} + %lock_0_2_3 = aie.lock(%tile_0_2, 4) {init = 0 : i8} + %lock_0_2_4 = aie.lock(%tile_0_2, 3) {init = 1 : i8} + %lock_0_2_5 = aie.lock(%tile_0_2, 2) {init = 0 : i8} + %lock_0_2_6 = aie.lock(%tile_0_2, 1) {init = 1 : i8} + %lock_0_2_7 = aie.lock(%tile_0_2, 0) {init = 0 : i8} %buf5 = aie.buffer(%tile_0_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf5"} : memref<64x64xi8> %buf4 = aie.buffer(%tile_1_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf4"} : memref<64x64xi8> %buf3 = aie.buffer(%tile_2_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf3"} : memref<64x64xi32> @@ -50,49 +50,49 @@ aie.device(npu1_4col) { aie.next_bd ^bb6 } %switchbox_0_0 = aie.switchbox(%tile_0_0) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %shim_mux_0_0 = aie.shim_mux(%tile_0_0) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_0_1 = aie.switchbox(%tile_0_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_1_0 = aie.tile(1, 0) %switchbox_1_0 = aie.switchbox(%tile_1_0) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_1_1 = aie.switchbox(%tile_1_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_2_0 = aie.tile(2, 0) %switchbox_2_0 = aie.switchbox(%tile_2_0) { - aie.connect + aie.connect } %switchbox_2_1 = aie.switchbox(%tile_2_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_0_2 = aie.switchbox(%tile_0_2) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %tile_1_2 = aie.tile(1, 2) %switchbox_1_2 = aie.switchbox(%tile_1_2) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_2_2 = aie.tile(2, 2) %switchbox_2_2 = aie.switchbox(%tile_2_2) { - aie.connect + aie.connect } %memtile_dma_2_1 = aie.memtile_dma(%tile_2_1) { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3, repeat_count = 1) diff --git a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_8x32_16xi32__dispatch_0_matmul_8x32_0.aiecc.mlir b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_8x32_16xi32__dispatch_0_matmul_8x32_0.aiecc.mlir index 355b41b6a..0f1fda51a 100644 --- a/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_8x32_16xi32__dispatch_0_matmul_8x32_0.aiecc.mlir +++ b/runtime/src/iree-amd-aie/aie_runtime/test/cdo/matmul_8x32_16xi32__dispatch_0_matmul_8x32_0.aiecc.mlir @@ -7,18 +7,18 @@ aie.device(npu1_4col) { %tile_1_1 = aie.tile(1, 1) %tile_2_1 = aie.tile(2, 1) %tile_0_2 = aie.tile(0, 2) - %lock_1_1 = aie.lock(%tile_1_1, 1) {init = 1 : i32} - %lock_1_1_0 = aie.lock(%tile_1_1, 0) {init = 0 : i32} - %lock_0_1 = aie.lock(%tile_0_1, 1) {init = 1 : i32} - %lock_0_1_1 = aie.lock(%tile_0_1, 0) {init = 0 : i32} - %lock_2_1 = aie.lock(%tile_2_1, 1) {init = 1 : i32} - %lock_2_1_2 = aie.lock(%tile_2_1, 0) {init = 0 : i32} - %lock_0_2 = aie.lock(%tile_0_2, 5) {init = 1 : i32} - %lock_0_2_3 = aie.lock(%tile_0_2, 4) {init = 0 : i32} - %lock_0_2_4 = aie.lock(%tile_0_2, 3) {init = 1 : i32} - %lock_0_2_5 = aie.lock(%tile_0_2, 2) {init = 0 : i32} - %lock_0_2_6 = aie.lock(%tile_0_2, 1) {init = 1 : i32} - %lock_0_2_7 = aie.lock(%tile_0_2, 0) {init = 0 : i32} + %lock_1_1 = aie.lock(%tile_1_1, 1) {init = 1 : i8} + %lock_1_1_0 = aie.lock(%tile_1_1, 0) {init = 0 : i8} + %lock_0_1 = aie.lock(%tile_0_1, 1) {init = 1 : i8} + %lock_0_1_1 = aie.lock(%tile_0_1, 0) {init = 0 : i8} + %lock_2_1 = aie.lock(%tile_2_1, 1) {init = 1 : i8} + %lock_2_1_2 = aie.lock(%tile_2_1, 0) {init = 0 : i8} + %lock_0_2 = aie.lock(%tile_0_2, 5) {init = 1 : i8} + %lock_0_2_3 = aie.lock(%tile_0_2, 4) {init = 0 : i8} + %lock_0_2_4 = aie.lock(%tile_0_2, 3) {init = 1 : i8} + %lock_0_2_5 = aie.lock(%tile_0_2, 2) {init = 0 : i8} + %lock_0_2_6 = aie.lock(%tile_0_2, 1) {init = 1 : i8} + %lock_0_2_7 = aie.lock(%tile_0_2, 0) {init = 0 : i8} %buf5 = aie.buffer(%tile_0_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf5"} : memref<8x16xi32> %buf4 = aie.buffer(%tile_1_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf4"} : memref<16x32xi32> %buf3 = aie.buffer(%tile_2_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "buf3"} : memref<8x32xi32> @@ -50,49 +50,49 @@ aie.device(npu1_4col) { aie.next_bd ^bb6 } %switchbox_0_0 = aie.switchbox(%tile_0_0) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %shim_mux_0_0 = aie.shim_mux(%tile_0_0) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %switchbox_0_1 = aie.switchbox(%tile_0_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_1_0 = aie.tile(1, 0) %switchbox_1_0 = aie.switchbox(%tile_1_0) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_1_1 = aie.switchbox(%tile_1_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_2_0 = aie.tile(2, 0) %switchbox_2_0 = aie.switchbox(%tile_2_0) { - aie.connect + aie.connect } %switchbox_2_1 = aie.switchbox(%tile_2_1) { - aie.connect - aie.connect + aie.connect + aie.connect } %switchbox_0_2 = aie.switchbox(%tile_0_2) { - aie.connect - aie.connect - aie.connect + aie.connect + aie.connect + aie.connect } %tile_1_2 = aie.tile(1, 2) %switchbox_1_2 = aie.switchbox(%tile_1_2) { - aie.connect - aie.connect + aie.connect + aie.connect } %tile_2_2 = aie.tile(2, 2) %switchbox_2_2 = aie.switchbox(%tile_2_2) { - aie.connect + aie.connect } %memtile_dma_2_1 = aie.memtile_dma(%tile_2_1) { %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3, repeat_count = 1) diff --git a/third_party/mlir-aie b/third_party/mlir-aie deleted file mode 160000 index 527370a0d..000000000 --- a/third_party/mlir-aie +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 527370a0d3982a20a8559944fbcaa532356b2819