From a9432426305bc7f6ef1099c2bea51007552b844e Mon Sep 17 00:00:00 2001 From: James Newling Date: Mon, 2 Sep 2024 09:50:45 -0700 Subject: [PATCH 1/2] Assigning lock IDS is done in a subsequent pass --- .../aie/AMDAIEObjectFifoStatefulTransform.cpp | 64 +++---------------- 1 file changed, 8 insertions(+), 56 deletions(-) diff --git a/compiler/plugins/target/AMD-AIE/aie/AMDAIEObjectFifoStatefulTransform.cpp b/compiler/plugins/target/AMD-AIE/aie/AMDAIEObjectFifoStatefulTransform.cpp index 0fd4932ba..1f52fb8a4 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AMDAIEObjectFifoStatefulTransform.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AMDAIEObjectFifoStatefulTransform.cpp @@ -4,9 +4,6 @@ // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -#include -#include - #include "AIEDialect.h" #include "Passes.h" #include "iree-amd-aie/aie_runtime/iree_aie_runtime.h" @@ -15,7 +12,6 @@ #include "mlir/Dialect/MemRef/IR/MemRef.h" #include "mlir/Dialect/SCF/IR/SCF.h" #include "mlir/Dialect/SCF/Utils/Utils.h" -#include "mlir/Dialect/Utils/StaticValueUtils.h" #include "mlir/IR/Attributes.h" #include "mlir/IR/PatternMatch.h" #include "mlir/Pass/Pass.h" @@ -28,7 +24,6 @@ using namespace mlir::iree_compiler::AMDAIE; using xilinx::AIE::AIEObjectFifoType; using xilinx::AIE::BDDimLayoutArrayArrayAttr; using xilinx::AIE::BDDimLayoutArrayAttr; -using xilinx::AIE::BDDimLayoutAttr; using xilinx::AIE::BufferOp; using xilinx::AIE::CoreOp; using xilinx::AIE::DeviceOp; @@ -119,32 +114,6 @@ std::optional getOptionalSharedTile(ObjectFifoLinkOp op) { } // namespace -class LockAnalysis { - DenseMap, int> locksPerTile; - - public: - LockAnalysis(DeviceOp &device) { - for (auto lockOp : device.getOps()) - locksPerTile[{lockOp.getTile(), lockOp.getLockID().value()}] = 1; - } - - /// Given a tile, returns next usable lockID for that tile. - int getLockID(TileOp &tileOp) { - DeviceOp device = tileOp->getParentOfType(); - AMDAIEDeviceModel deviceModel = - getDeviceModel(static_cast(device.getDevice())); - for (int i = 0; - i < deviceModel.getNumLocks(tileOp.getCol(), tileOp.getRow()); i++) { - std::pair lockId = {tileOp, i}; - if (int usageCnt = locksPerTile[lockId]; usageCnt == 0) { - locksPerTile[lockId] = 1; - return i; - } - } - return -1; - } -}; - class DMAChannelAnalysis { DenseMap producerChannelsPerTile; DenseMap consumerChannelsPerTile; @@ -721,7 +690,6 @@ void replaceObjectAcquireOp( void createBuffersAndLocks( OpBuilder builder, DeviceOp device, ObjectFifoCreateOp createOp, std::vector &splitBecauseLink, - LockAnalysis &lockAnalysis, DenseMap &objFifoLinks, DenseMap> &buffersPerFifo, DenseMap> &locksPerFifo) { @@ -817,31 +785,17 @@ void createBuffersAndLocks( numElem = 0; // create corresponding aie2 locks - int prodLockID = lockAnalysis.getLockID(creationTile); - if (prodLockID < 0) { - creationTile->emitOpError("No more locks to allocate!"); - assert(prodLockID >= 0); - } - auto prodLock = builder.create(builder.getUnknownLoc(), creationTile, - prodLockID, numElem); - prodLock.getOperation()->setAttr( - SymbolTable::getSymbolAttrName(), + LockOp prodLock = builder.create( + builder.getUnknownLoc(), creationTile, IntegerAttr{}, + builder.getI8IntegerAttr(numElem), builder.getStringAttr(name(createOp).str() + "_prod_lock")); - std::vector locks{prodLock}; - int consLockID = lockAnalysis.getLockID(creationTile); - if (consLockID < 0) { - creationTile->emitOpError("No more locks to allocate!"); - assert(consLockID >= 0); - } - auto consLock = builder.create(builder.getUnknownLoc(), creationTile, - consLockID, 0); - consLock.getOperation()->setAttr( - SymbolTable::getSymbolAttrName(), + LockOp consLock = builder.create( + builder.getUnknownLoc(), creationTile, IntegerAttr{}, + builder.getI8IntegerAttr(0), builder.getStringAttr(name(createOp).str() + "_cons_lock")); - locks.push_back(consLock); - locksPerFifo[createOp] = locks; + locksPerFifo[createOp] = std::vector{prodLock, consLock}; } /// Translate ObjectFifoCreateOp ops into routing primitives (Flows) and DMA @@ -951,7 +905,6 @@ struct AMDAIEObjectFifoStatefulTransformPass : mlir::OperationPass { void runOnOperation() override { DeviceOp device = getOperation(); - LockAnalysis lockAnalysis(device); DMAChannelAnalysis dmaAnalysis; OpBuilder builder = OpBuilder::atBlockEnd(device.getBody()); // maps each objFifo to its corresponding buffer @@ -980,8 +933,7 @@ struct AMDAIEObjectFifoStatefulTransformPass : mlir::OperationPass { for (ObjectFifoCreateOp createOp : device.getOps()) createBuffersAndLocks(builder, device, createOp, splitBecauseLink, - lockAnalysis, objFifoLinks, buffersPerFifo, - locksPerFifo); + objFifoLinks, buffersPerFifo, locksPerFifo); // Only the objectFifos we split above require DMA communication; the others // rely on shared memory and share the same buffers. From 26216440010ef5ac8336a5acdf1a7e03dbdb4530 Mon Sep 17 00:00:00 2001 From: James Newling Date: Mon, 2 Sep 2024 10:12:00 -0700 Subject: [PATCH 2/2] update tests --- .../aie/test/AIE2_cyclostatic_dma.mlir | 8 ++--- .../AMD-AIE/aie/test/AIE2_cyclostatic_l1.mlir | 4 +-- .../AMD-AIE/aie/test/AIE2_cyclostatic_l2.mlir | 12 +++---- .../aie/test/AIE2_delayed_release.mlir | 4 +-- .../AMD-AIE/aie/test/AIE2_static_l1.mlir | 4 +-- .../aie/test/allocation_info_test.mlir | 32 +++++++++---------- .../AMD-AIE/aie/test/base_test_AIE1.mlir | 12 +++---- .../AMD-AIE/aie/test/base_test_AIE2.mlir | 12 +++---- .../AMD-AIE/aie/test/broadcast_test.mlir | 20 ++++++------ .../aie/test/cyclostatic_AIE2_sharedMem.mlir | 4 +-- .../AMD-AIE/aie/test/link_test_AIE1.mlir | 12 +++---- .../AMD-AIE/aie/test/link_test_AIE2.mlir | 16 +++++----- .../AMD-AIE/aie/test/link_test_DDR_to_L1.mlir | 12 +++---- .../AMD-AIE/aie/test/link_test_L1_to_DDR.mlir | 12 +++---- .../AMD-AIE/aie/test/link_test_broadcast.mlir | 24 +++++++------- .../aie/test/link_test_distribute.mlir | 20 ++++++------ .../AMD-AIE/aie/test/link_test_join.mlir | 24 +++++++------- .../target/AMD-AIE/aie/test/matmul_test.mlir | 24 +++++++------- .../target/AMD-AIE/aie/test/memTile_test.mlir | 8 ++--- .../AMD-AIE/aie/test/nd_dma_base_AIE2.mlir | 16 +++++----- .../aie/test/nd_dma_distribute_AIE2.mlir | 16 +++++----- .../test/nd_dma_multiple_consumers_AIE2.mlir | 28 ++++++++-------- .../AMD-AIE/aie/test/nested_loop_test.mlir | 28 ++++++++-------- .../aie/test/non_adjacency_test_1.mlir | 8 ++--- .../aie/test/non_adjacency_test_2.mlir | 8 ++--- .../aie/test/non_adjacency_test_AIE2.mlir | 8 ++--- .../test/register_external_buffers_test.mlir | 8 ++--- .../same_core_producer_consumer_test.mlir | 4 +-- .../AMD-AIE/aie/test/shimRow_mem_test.mlir | 8 ++--- .../AMD-AIE/aie/test/shim_AIE2_test.mlir | 16 +++++----- .../AMD-AIE/aie/test/shim_broadcast_test.mlir | 16 +++++----- .../AMD-AIE/aie/test/subview_test_1.mlir | 4 +-- .../AMD-AIE/aie/test/subview_test_2.mlir | 8 ++--- .../AMD-AIE/aie/test/subview_test_3.mlir | 8 ++--- 34 files changed, 224 insertions(+), 224 deletions(-) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_dma.mlir b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_dma.mlir index 245bfa622..65036eca3 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_dma.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_dma.mlir @@ -9,12 +9,12 @@ // CHECK: %[[FIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_0"} : memref // CHECK: %[[FIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_1"} : memref // CHECK: %[[FIFO_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_2"} : memref -// CHECK: %[[FIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 0) {init = 3 : i8, sym_name = "fifo_cons_prod_lock"} -// CHECK: %[[FIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 1) {init = 0 : i8, sym_name = "fifo_cons_cons_lock"} +// CHECK: %[[FIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]]) {init = 3 : i8, sym_name = "fifo_cons_prod_lock"} +// CHECK: %[[FIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]]) {init = 0 : i8, sym_name = "fifo_cons_cons_lock"} // CHECK: %[[FIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_0"} : memref // CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref -// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "fifo_prod_lock"} -// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo_cons_lock"} +// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "fifo_prod_lock"} +// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "fifo_cons_lock"} // CHECK: %[[BUF83:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf83"} : memref<4xi32> // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_8_3]], DMA : 0) // CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { diff --git a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l1.mlir index 6b4c7c694..c2b63817e 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l1.mlir @@ -9,8 +9,8 @@ // CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref // CHECK: %[[FIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_2"} : memref // CHECK: %[[FIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_3"} : memref -// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i8, sym_name = "fifo_prod_lock"} -// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo_cons_lock"} +// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 4 : i8, sym_name = "fifo_prod_lock"} +// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "fifo_cons_lock"} // CHECK: %[[BUF23:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "buf23"} : memref<4xi32> // CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { // CHECK: %[[C55_I32:.*]] = arith.constant 55 : i32 diff --git a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l2.mlir index 7009c7003..063bbd18c 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_cyclostatic_l2.mlir @@ -13,18 +13,18 @@ // CHECK: %[[FIFO1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_1"} : memref<1xi32> // CHECK: %[[FIFO1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_2"} : memref<1xi32> // CHECK: %[[FIFO1_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_3"} : memref<1xi32> -// CHECK: %[[FIFO1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 0) {init = 4 : i8, sym_name = "fifo1_cons_prod_lock"} -// CHECK: %[[FIFO1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 1) {init = 0 : i8, sym_name = "fifo1_cons_cons_lock"} +// CHECK: %[[FIFO1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]]) {init = 4 : i8, sym_name = "fifo1_cons_prod_lock"} +// CHECK: %[[FIFO1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]]) {init = 0 : i8, sym_name = "fifo1_cons_cons_lock"} // CHECK: %[[FIFO0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_0"} : memref<1xi32> // CHECK: %[[FIFO0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_1"} : memref<1xi32> // CHECK: %[[FIFO0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_2"} : memref<1xi32> // CHECK: %[[FIFO0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_3"} : memref<1xi32> -// CHECK: %[[FIFO0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 4 : i8, sym_name = "fifo0_cons_prod_lock"} -// CHECK: %[[FIFO0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "fifo0_cons_cons_lock"} +// CHECK: %[[FIFO0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 4 : i8, sym_name = "fifo0_cons_prod_lock"} +// CHECK: %[[FIFO0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 0 : i8, sym_name = "fifo0_cons_cons_lock"} // CHECK: %[[FIFO0_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo0_buff_0"} : memref<1xi32> // CHECK: %[[FIFO0_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo0_buff_1"} : memref<1xi32> -// CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "fifo0_prod_lock"} -// CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo0_cons_lock"} +// CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "fifo0_prod_lock"} +// CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "fifo0_cons_lock"} // CHECK: %[[BUF83:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf83"} : memref<1xi32> // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_8_3]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_delayed_release.mlir b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_delayed_release.mlir index deaf4926a..d77abab08 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_delayed_release.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_delayed_release.mlir @@ -9,8 +9,8 @@ // CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref // CHECK: %[[FIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_2"} : memref // CHECK: %[[FIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_3"} : memref -// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i8, sym_name = "fifo_prod_lock"} -// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo_cons_lock"} +// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 4 : i8, sym_name = "fifo_prod_lock"} +// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "fifo_cons_lock"} // CHECK: %[[BUF23:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "buf23"} : memref<4xi32> // CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { // CHECK: %[[C99_I32:.*]] = arith.constant 99 : i32 diff --git a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_static_l1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_static_l1.mlir index b24ac65dc..8b6290b30 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/AIE2_static_l1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/AIE2_static_l1.mlir @@ -17,8 +17,8 @@ // CHECK-DAG: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref // CHECK-DAG: %[[FIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_2"} : memref // CHECK-DAG: %[[FIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_3"} : memref -// CHECK-DAG: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i8, sym_name = "fifo_prod_lock"} -// CHECK-DAG: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "fifo_cons_lock"} +// CHECK-DAG: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 4 : i8, sym_name = "fifo_prod_lock"} +// CHECK-DAG: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "fifo_cons_lock"} // CHECK-DAG: %[[DSTBUF22:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "dstbuf22"} : memref<16xi32> // CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { // CHECK: %[[C0_I32:.*]] = arith.constant 0 : i32 diff --git a/compiler/plugins/target/AMD-AIE/aie/test/allocation_info_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/allocation_info_test.mlir index 0c9175140..9aef2676c 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/allocation_info_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/allocation_info_test.mlir @@ -13,30 +13,30 @@ // CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) -// CHECK: %[[OF_OUT_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 6) {init = 0 : i8, sym_name = "of_out_1_cons_prod_lock"} -// CHECK: %[[OF_OUT_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 7) {init = 0 : i8, sym_name = "of_out_1_cons_cons_lock"} +// CHECK: %[[OF_OUT_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_out_1_cons_prod_lock"} +// CHECK: %[[OF_OUT_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_out_1_cons_cons_lock"} // CHECK: %[[OF_OUT_1_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_out_1_buff_0"} : memref<64xi16> // CHECK: %[[OF_OUT_1_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_out_1_buff_1"} : memref<64xi16> -// CHECK: %[[OF_OUT_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 2) {init = 2 : i8, sym_name = "of_out_1_prod_lock"} -// CHECK: %[[OF_OUT_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 3) {init = 0 : i8, sym_name = "of_out_1_cons_lock"} +// CHECK: %[[OF_OUT_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 2 : i8, sym_name = "of_out_1_prod_lock"} +// CHECK: %[[OF_OUT_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 0 : i8, sym_name = "of_out_1_cons_lock"} // CHECK: %[[OF_IN_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_0"} : memref<64xi16> // CHECK: %[[OF_IN_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_1"} : memref<64xi16> -// CHECK: %[[OF_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "of_in_1_cons_prod_lock"} -// CHECK: %[[OF_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "of_in_1_cons_cons_lock"} -// CHECK: %[[OF_IN_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 4) {init = 0 : i8, sym_name = "of_in_1_prod_lock"} -// CHECK: %[[OF_IN_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 5) {init = 0 : i8, sym_name = "of_in_1_cons_lock"} -// CHECK: %[[OF_OUT_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 2) {init = 0 : i8, sym_name = "of_out_0_cons_prod_lock"} -// CHECK: %[[OF_OUT_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 3) {init = 0 : i8, sym_name = "of_out_0_cons_cons_lock"} +// CHECK: %[[OF_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 2 : i8, sym_name = "of_in_1_cons_prod_lock"} +// CHECK: %[[OF_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 0 : i8, sym_name = "of_in_1_cons_cons_lock"} +// CHECK: %[[OF_IN_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_in_1_prod_lock"} +// CHECK: %[[OF_IN_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_in_1_cons_lock"} +// CHECK: %[[OF_OUT_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_out_0_cons_prod_lock"} +// CHECK: %[[OF_OUT_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_out_0_cons_cons_lock"} // CHECK: %[[OF_OUT_0_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_0_buff_0"} : memref<64xi16> // CHECK: %[[OF_OUT_0_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_0_buff_1"} : memref<64xi16> -// CHECK: %[[OF_OUT_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i8, sym_name = "of_out_0_prod_lock"} -// CHECK: %[[OF_OUT_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i8, sym_name = "of_out_0_cons_lock"} +// CHECK: %[[OF_OUT_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "of_out_0_prod_lock"} +// CHECK: %[[OF_OUT_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "of_out_0_cons_lock"} // CHECK: %[[OF_IN_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_0"} : memref<64xi16> // CHECK: %[[OF_IN_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_1"} : memref<64xi16> -// CHECK: %[[OF_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of_in_0_cons_prod_lock"} -// CHECK: %[[OF_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of_in_0_cons_cons_lock"} -// CHECK: %[[OF_IN_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "of_in_0_prod_lock"} -// CHECK: %[[OF_IN_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "of_in_0_cons_lock"} +// CHECK: %[[OF_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "of_in_0_cons_prod_lock"} +// CHECK: %[[OF_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "of_in_0_cons_cons_lock"} +// CHECK: %[[OF_IN_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_in_0_prod_lock"} +// CHECK: %[[OF_IN_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_in_0_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_0]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_0]], DMA : 1, %[[TILE_2_3]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE1.mlir index 41fa1a9bb..109b6bff3 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE1.mlir @@ -10,18 +10,18 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} // CHECK: %[[OF1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_0"} : memref<16xi32> // CHECK: %[[OF1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_1"} : memref<16xi32> -// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i8, sym_name = "of1_prod_lock"} -// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i8, sym_name = "of1_cons_lock"} +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of1_cons_lock"} // CHECK: %[[OF0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_0"} : memref<16xi32> // CHECK: %[[OF0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_1"} : memref<16xi32> // CHECK: %[[OF0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_2"} : memref<16xi32> // CHECK: %[[OF0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_3"} : memref<16xi32> -// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "of0_prod_lock"} -// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of0_cons_lock"} +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 4 : i8, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of0_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { // CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE2.mlir index f84f0950c..0997616bb 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/base_test_AIE2.mlir @@ -10,18 +10,18 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} // CHECK: %[[OF1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_0"} : memref<16xi32> // CHECK: %[[OF1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_1"} : memref<16xi32> -// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i8, sym_name = "of1_prod_lock"} -// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i8, sym_name = "of1_cons_lock"} +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of1_cons_lock"} // CHECK: %[[OF0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_0"} : memref<16xi32> // CHECK: %[[OF0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_1"} : memref<16xi32> // CHECK: %[[OF0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_2"} : memref<16xi32> // CHECK: %[[OF0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_3"} : memref<16xi32> -// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "of0_prod_lock"} -// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of0_cons_lock"} +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 4 : i8, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of0_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { // CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/broadcast_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/broadcast_test.mlir index 7f8d8a701..7b4b42253 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/broadcast_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/broadcast_test.mlir @@ -14,28 +14,28 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[BROADCAST_OF_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "broadcast_of_0_cons_buff_0"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "broadcast_of_0_cons_buff_1"} : memref<16xi32> -// CHECK: %[[BROADCAST_OF_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "broadcast_of_0_cons_prod_lock"} -// CHECK: %[[BROADCAST_OF_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "broadcast_of_0_cons_cons_lock"} +// CHECK: %[[BROADCAST_OF_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "broadcast_of_0_cons_prod_lock"} +// CHECK: %[[BROADCAST_OF_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "broadcast_of_0_cons_cons_lock"} // CHECK: %[[BROADCAST_OF_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_4]]) {sym_name = "broadcast_of_1_cons_buff_0"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_4]]) {sym_name = "broadcast_of_1_cons_buff_1"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_1_4]]) {sym_name = "broadcast_of_1_cons_buff_2"} : memref<16xi32> -// CHECK: %[[BROADCAST_OF_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_4]], 0) {init = 3 : i8, sym_name = "broadcast_of_1_cons_prod_lock"} -// CHECK: %[[BROADCAST_OF_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_4]], 1) {init = 0 : i8, sym_name = "broadcast_of_1_cons_cons_lock"} +// CHECK: %[[BROADCAST_OF_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_4]]) {init = 3 : i8, sym_name = "broadcast_of_1_cons_prod_lock"} +// CHECK: %[[BROADCAST_OF_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_4]]) {init = 0 : i8, sym_name = "broadcast_of_1_cons_cons_lock"} // CHECK: %[[BROADCAST_OF_2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "broadcast_of_2_cons_buff_0"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "broadcast_of_2_cons_buff_1"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_2_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "broadcast_of_2_cons_buff_2"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_2_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "broadcast_of_2_cons_buff_3"} : memref<16xi32> -// CHECK: %[[BROADCAST_OF_2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 0) {init = 4 : i8, sym_name = "broadcast_of_2_cons_prod_lock"} -// CHECK: %[[BROADCAST_OF_2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 1) {init = 0 : i8, sym_name = "broadcast_of_2_cons_cons_lock"} +// CHECK: %[[BROADCAST_OF_2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_2]]) {init = 4 : i8, sym_name = "broadcast_of_2_cons_prod_lock"} +// CHECK: %[[BROADCAST_OF_2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_2]]) {init = 0 : i8, sym_name = "broadcast_of_2_cons_cons_lock"} // CHECK: %[[BROADCAST_OF_3_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "broadcast_of_3_cons_buff_0"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_3_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "broadcast_of_3_cons_buff_1"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_3_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "broadcast_of_3_cons_buff_2"} : memref<16xi32> -// CHECK: %[[BROADCAST_OF_3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 3 : i8, sym_name = "broadcast_of_3_cons_prod_lock"} -// CHECK: %[[BROADCAST_OF_3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "broadcast_of_3_cons_cons_lock"} +// CHECK: %[[BROADCAST_OF_3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 3 : i8, sym_name = "broadcast_of_3_cons_prod_lock"} +// CHECK: %[[BROADCAST_OF_3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "broadcast_of_3_cons_cons_lock"} // CHECK: %[[BROADCAST_OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "broadcast_of_buff_0"} : memref<16xi32> // CHECK: %[[BROADCAST_OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "broadcast_of_buff_1"} : memref<16xi32> -// CHECK: %[[BROADCAST_OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 2 : i8, sym_name = "broadcast_of_prod_lock"} -// CHECK: %[[BROADCAST_OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i8, sym_name = "broadcast_of_cons_lock"} +// CHECK: %[[BROADCAST_OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]]) {init = 2 : i8, sym_name = "broadcast_of_prod_lock"} +// CHECK: %[[BROADCAST_OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]]) {init = 0 : i8, sym_name = "broadcast_of_cons_lock"} // CHECK: aie.flow(%[[TILE_1_3]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_3]], DMA : 0, %[[TILE_3_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_3]], DMA : 0, %[[TILE_1_4]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/cyclostatic_AIE2_sharedMem.mlir b/compiler/plugins/target/AMD-AIE/aie/test/cyclostatic_AIE2_sharedMem.mlir index 9c0124fb1..dce755d75 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/cyclostatic_AIE2_sharedMem.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/cyclostatic_AIE2_sharedMem.mlir @@ -9,8 +9,8 @@ // CHECK: %[[FIFO0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "fifo0_buff_1"} : memref<16xi32> // CHECK: %[[FIFO0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "fifo0_buff_2"} : memref<16xi32> // CHECK: %[[FIFO0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "fifo0_buff_3"} : memref<16xi32> -// CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "fifo0_prod_lock"} -// CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "fifo0_cons_lock"} +// CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 4 : i8, sym_name = "fifo0_prod_lock"} +// CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "fifo0_cons_lock"} // CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { // CHECK-DAG: %[[C11_I32:.*]] = arith.constant 11 : i32 // CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE1.mlir index 597a8c409..2d58b49de 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE1.mlir @@ -11,14 +11,14 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[OF2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of2_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of2_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of2_cons_prod_lock"} -// CHECK: %[[OF2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of2_cons_cons_lock"} +// CHECK: %[[OF2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "of2_cons_prod_lock"} +// CHECK: %[[OF2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "of2_cons_cons_lock"} // CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} -// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "of1_prod_lock"} -// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "of1_cons_lock"} +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of1_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_1_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: %[[EXT_BUFF_IN:.*]] = aie.external_buffer {sym_name = "ext_buff_in"} : memref<16xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE2.mlir index 11510f9c8..371eb63f3 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_AIE2.mlir @@ -15,12 +15,12 @@ // CHECK: %[[MEM_OUT_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_3]]) {sym_name = "mem_out_cons_buff_1"} : memref<3000xi32> // CHECK: %[[MEM_OUT_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_0_3]]) {sym_name = "mem_out_cons_buff_2"} : memref<3000xi32> // CHECK: %[[MEM_OUT_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_0_3]]) {sym_name = "mem_out_cons_buff_3"} : memref<3000xi32> -// CHECK: %[[MEM_OUT_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_3]], 0) {init = 4 : i8, sym_name = "mem_out_cons_prod_lock"} -// CHECK: %[[MEM_OUT_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_3]], 1) {init = 0 : i8, sym_name = "mem_out_cons_cons_lock"} +// CHECK: %[[MEM_OUT_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_3]]) {init = 4 : i8, sym_name = "mem_out_cons_prod_lock"} +// CHECK: %[[MEM_OUT_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_3]]) {init = 0 : i8, sym_name = "mem_out_cons_cons_lock"} // CHECK: %[[MEM_IN_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "mem_in_0_cons_buff_0"} : memref<3000xi32> // CHECK: %[[MEM_IN_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "mem_in_0_cons_buff_1"} : memref<3000xi32> -// CHECK: %[[MEM_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 0) {init = 2 : i8, sym_name = "mem_in_0_cons_prod_lock"} -// CHECK: %[[MEM_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 1) {init = 0 : i8, sym_name = "mem_in_0_cons_cons_lock"} +// CHECK: %[[MEM_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]]) {init = 2 : i8, sym_name = "mem_in_0_cons_prod_lock"} +// CHECK: %[[MEM_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]]) {init = 0 : i8, sym_name = "mem_in_0_cons_cons_lock"} // CHECK: %[[MEM_IN_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_0"} : memref<3000xi32> // CHECK: %[[MEM_IN_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_1"} : memref<3000xi32> // CHECK: %[[MEM_IN_1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_2"} : memref<3000xi32> @@ -28,10 +28,10 @@ // CHECK: %[[MEM_IN_1_CONS_BUFF_4:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_4"} : memref<3000xi32> // CHECK: %[[MEM_IN_1_CONS_BUFF_5:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_5"} : memref<3000xi32> // CHECK: %[[MEM_IN_1_CONS_BUFF_6:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_6"} : memref<3000xi32> -// CHECK: %[[MEM_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 0) {init = 7 : i8, sym_name = "mem_in_1_cons_prod_lock"} -// CHECK: %[[MEM_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 1) {init = 0 : i8, sym_name = "mem_in_1_cons_cons_lock"} -// CHECK: %[[MEM_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 0) {init = 0 : i8, sym_name = "mem_in_prod_lock"} -// CHECK: %[[MEM_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 1) {init = 0 : i8, sym_name = "mem_in_cons_lock"} +// CHECK: %[[MEM_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]]) {init = 7 : i8, sym_name = "mem_in_1_cons_prod_lock"} +// CHECK: %[[MEM_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]]) {init = 0 : i8, sym_name = "mem_in_1_cons_cons_lock"} +// CHECK: %[[MEM_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]]) {init = 0 : i8, sym_name = "mem_in_prod_lock"} +// CHECK: %[[MEM_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]]) {init = 0 : i8, sym_name = "mem_in_cons_lock"} // CHECK: aie.flow(%[[TILE_0_0]], DMA : 0, %[[TILE_0_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_0_0]], DMA : 0, %[[TILE_0_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_0_1]], DMA : 0, %[[TILE_0_3]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_DDR_to_L1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_DDR_to_L1.mlir index 881c57e7a..ad0fe6bfb 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_DDR_to_L1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_DDR_to_L1.mlir @@ -11,14 +11,14 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[FROM_MEMTILE_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "from_memTile_cons_buff_0"} : memref<16xi32> // CHECK: %[[FROM_MEMTILE_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "from_memTile_cons_buff_1"} : memref<16xi32> -// CHECK: %[[FROM_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "from_memTile_cons_prod_lock"} -// CHECK: %[[FROM_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "from_memTile_cons_cons_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "from_memTile_cons_prod_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "from_memTile_cons_cons_lock"} // CHECK: %[[TO_MEMTILE_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "to_memTile_cons_buff_0"} : memref<16xi32> // CHECK: %[[TO_MEMTILE_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "to_memTile_cons_buff_1"} : memref<16xi32> -// CHECK: %[[TO_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i8, sym_name = "to_memTile_cons_prod_lock"} -// CHECK: %[[TO_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "to_memTile_cons_cons_lock"} -// CHECK: %[[TO_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "to_memTile_prod_lock"} -// CHECK: %[[TO_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "to_memTile_cons_lock"} +// CHECK: %[[TO_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 2 : i8, sym_name = "to_memTile_cons_prod_lock"} +// CHECK: %[[TO_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 0 : i8, sym_name = "to_memTile_cons_cons_lock"} +// CHECK: %[[TO_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "to_memTile_prod_lock"} +// CHECK: %[[TO_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "to_memTile_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: %[[EXT_BUFF_IN:.*]] = aie.external_buffer {sym_name = "ext_buff_in"} : memref<16xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_L1_to_DDR.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_L1_to_DDR.mlir index 2aec5cdd0..b4af26063 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_L1_to_DDR.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_L1_to_DDR.mlir @@ -9,16 +9,16 @@ // CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[FROM_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "from_memTile_cons_prod_lock"} -// CHECK: %[[FROM_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "from_memTile_cons_cons_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "from_memTile_cons_prod_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "from_memTile_cons_cons_lock"} // CHECK: %[[FROM_MEMTILE_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "from_memTile_buff_0"} : memref<48xi32> // CHECK: %[[FROM_MEMTILE_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "from_memTile_buff_1"} : memref<48xi32> -// CHECK: %[[FROM_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i8, sym_name = "from_memTile_prod_lock"} -// CHECK: %[[FROM_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "from_memTile_cons_lock"} +// CHECK: %[[FROM_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 2 : i8, sym_name = "from_memTile_prod_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 0 : i8, sym_name = "from_memTile_cons_lock"} // CHECK: %[[TO_MEMTILE_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "to_memTile_buff_0"} : memref<16xi32> // CHECK: %[[TO_MEMTILE_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "to_memTile_buff_1"} : memref<16xi32> -// CHECK: %[[TO_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "to_memTile_prod_lock"} -// CHECK: %[[TO_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "to_memTile_cons_lock"} +// CHECK: %[[TO_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "to_memTile_prod_lock"} +// CHECK: %[[TO_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "to_memTile_cons_lock"} // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_0]], DMA : 0) // CHECK: %[[EXT_BUFF_IN:.*]] = aie.external_buffer {sym_name = "ext_buff_in"} : memref<48xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_broadcast.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_broadcast.mlir index 3391c7f5a..5a8f867c5 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_broadcast.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_broadcast.mlir @@ -15,27 +15,27 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[SKIP_CONNECTION_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "skip_connection_cons_buff_0"} : memref<16xi32> // CHECK: %[[SKIP_CONNECTION_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "skip_connection_cons_buff_1"} : memref<16xi32> -// CHECK: %[[SKIP_CONNECTION_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 2) {init = 2 : i8, sym_name = "skip_connection_cons_prod_lock"} -// CHECK: %[[SKIP_CONNECTION_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 3) {init = 0 : i8, sym_name = "skip_connection_cons_cons_lock"} +// CHECK: %[[SKIP_CONNECTION_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 2 : i8, sym_name = "skip_connection_cons_prod_lock"} +// CHECK: %[[SKIP_CONNECTION_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "skip_connection_cons_cons_lock"} // CHECK: %[[SKIP_CONNECTION_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "skip_connection_buff_0"} : memref<16xi32> // CHECK: %[[SKIP_CONNECTION_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "skip_connection_buff_1"} : memref<16xi32> -// CHECK: %[[SKIP_CONNECTION_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i8, sym_name = "skip_connection_prod_lock"} -// CHECK: %[[SKIP_CONNECTION_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i8, sym_name = "skip_connection_cons_lock"} +// CHECK: %[[SKIP_CONNECTION_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "skip_connection_prod_lock"} +// CHECK: %[[SKIP_CONNECTION_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "skip_connection_cons_lock"} // CHECK: %[[LINK2_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_0_cons_buff_0"} : memref<16xi32> // CHECK: %[[LINK2_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_0_cons_buff_1"} : memref<16xi32> -// CHECK: %[[LINK2_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "link2_0_cons_prod_lock"} -// CHECK: %[[LINK2_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "link2_0_cons_cons_lock"} +// CHECK: %[[LINK2_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "link2_0_cons_prod_lock"} +// CHECK: %[[LINK2_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "link2_0_cons_cons_lock"} // CHECK: %[[LINK2_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link2_1_cons_buff_0"} : memref<16xi32> // CHECK: %[[LINK2_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link2_1_cons_buff_1"} : memref<16xi32> // CHECK: %[[LINK2_1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link2_1_cons_buff_2"} : memref<16xi32> -// CHECK: %[[LINK2_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 3 : i8, sym_name = "link2_1_cons_prod_lock"} -// CHECK: %[[LINK2_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "link2_1_cons_cons_lock"} +// CHECK: %[[LINK2_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 3 : i8, sym_name = "link2_1_cons_prod_lock"} +// CHECK: %[[LINK2_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "link2_1_cons_cons_lock"} // CHECK: %[[LINK1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link1_cons_buff_0"} : memref<48xi32> // CHECK: %[[LINK1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link1_cons_buff_1"} : memref<48xi32> -// CHECK: %[[LINK1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i8, sym_name = "link1_cons_prod_lock"} -// CHECK: %[[LINK1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "link1_cons_cons_lock"} -// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "link1_prod_lock"} -// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "link1_cons_lock"} +// CHECK: %[[LINK1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 2 : i8, sym_name = "link1_cons_prod_lock"} +// CHECK: %[[LINK1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 0 : i8, sym_name = "link1_cons_cons_lock"} +// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "link1_prod_lock"} +// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "link1_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_distribute.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_distribute.mlir index 8cfb545a5..70fba47a3 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_distribute.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_distribute.mlir @@ -17,22 +17,22 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[LINK4_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link4_cons_buff_0"} : memref<12xi32> // CHECK: %[[LINK4_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link4_cons_buff_1"} : memref<12xi32> -// CHECK: %[[LINK4_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "link4_cons_prod_lock"} -// CHECK: %[[LINK4_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "link4_cons_cons_lock"} +// CHECK: %[[LINK4_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 2 : i8, sym_name = "link4_cons_prod_lock"} +// CHECK: %[[LINK4_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "link4_cons_cons_lock"} // CHECK: %[[LINK3_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "link3_cons_buff_0"} : memref<20xi32> // CHECK: %[[LINK3_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "link3_cons_buff_1"} : memref<20xi32> -// CHECK: %[[LINK3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "link3_cons_prod_lock"} -// CHECK: %[[LINK3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "link3_cons_cons_lock"} +// CHECK: %[[LINK3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 2 : i8, sym_name = "link3_cons_prod_lock"} +// CHECK: %[[LINK3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 0 : i8, sym_name = "link3_cons_cons_lock"} // CHECK: %[[LINK2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_cons_buff_0"} : memref<4x4xi32> // CHECK: %[[LINK2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_cons_buff_1"} : memref<4x4xi32> -// CHECK: %[[LINK2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "link2_cons_prod_lock"} -// CHECK: %[[LINK2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "link2_cons_cons_lock"} +// CHECK: %[[LINK2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "link2_cons_prod_lock"} +// CHECK: %[[LINK2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "link2_cons_cons_lock"} // CHECK: %[[LINK1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link1_cons_buff_0"} : memref<48xi32> // CHECK: %[[LINK1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link1_cons_buff_1"} : memref<48xi32> -// CHECK: %[[LINK1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 6 : i8, sym_name = "link1_cons_prod_lock"} -// CHECK: %[[LINK1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "link1_cons_cons_lock"} -// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "link1_prod_lock"} -// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "link1_cons_lock"} +// CHECK: %[[LINK1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 6 : i8, sym_name = "link1_cons_prod_lock"} +// CHECK: %[[LINK1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 0 : i8, sym_name = "link1_cons_cons_lock"} +// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "link1_prod_lock"} +// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "link1_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_1]], DMA : 1, %[[TILE_2_3]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/link_test_join.mlir b/compiler/plugins/target/AMD-AIE/aie/test/link_test_join.mlir index 7ba2fe540..a59741eda 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/link_test_join.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/link_test_join.mlir @@ -18,28 +18,28 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[LINK5_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "link5_cons_prod_lock"} -// CHECK: %[[LINK5_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "link5_cons_cons_lock"} +// CHECK: %[[LINK5_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "link5_cons_prod_lock"} +// CHECK: %[[LINK5_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "link5_cons_cons_lock"} // CHECK: %[[LINK5_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link5_buff_0"} : memref<512xi8> // CHECK: %[[LINK5_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link5_buff_1"} : memref<512xi8> -// CHECK: %[[LINK5_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 8 : i8, sym_name = "link5_prod_lock"} -// CHECK: %[[LINK5_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "link5_cons_lock"} +// CHECK: %[[LINK5_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 8 : i8, sym_name = "link5_prod_lock"} +// CHECK: %[[LINK5_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 0 : i8, sym_name = "link5_cons_lock"} // CHECK: %[[LINK4_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link4_buff_0"} : memref<128xi8> // CHECK: %[[LINK4_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link4_buff_1"} : memref<128xi8> -// CHECK: %[[LINK4_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "link4_prod_lock"} -// CHECK: %[[LINK4_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "link4_cons_lock"} +// CHECK: %[[LINK4_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 2 : i8, sym_name = "link4_prod_lock"} +// CHECK: %[[LINK4_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "link4_cons_lock"} // CHECK: %[[LINK3_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "link3_buff_0"} : memref<128xi8> // CHECK: %[[LINK3_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "link3_buff_1"} : memref<128xi8> -// CHECK: %[[LINK3_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "link3_prod_lock"} -// CHECK: %[[LINK3_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "link3_cons_lock"} +// CHECK: %[[LINK3_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 2 : i8, sym_name = "link3_prod_lock"} +// CHECK: %[[LINK3_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 0 : i8, sym_name = "link3_cons_lock"} // CHECK: %[[LINK2_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_buff_0"} : memref<128xi8> // CHECK: %[[LINK2_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_buff_1"} : memref<128xi8> -// CHECK: %[[LINK2_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "link2_prod_lock"} -// CHECK: %[[LINK2_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "link2_cons_lock"} +// CHECK: %[[LINK2_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "link2_prod_lock"} +// CHECK: %[[LINK2_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "link2_cons_lock"} // CHECK: %[[LINK1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "link1_buff_0"} : memref<128xi8> // CHECK: %[[LINK1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "link1_buff_1"} : memref<128xi8> -// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "link1_prod_lock"} -// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "link1_cons_lock"} +// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "link1_prod_lock"} +// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "link1_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_2_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_1]], DMA : 1) // CHECK: aie.flow(%[[TILE_2_3]], DMA : 0, %[[TILE_2_1]], DMA : 2) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/matmul_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/matmul_test.mlir index d9086a941..122471be1 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/matmul_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/matmul_test.mlir @@ -10,24 +10,24 @@ // CHECK: memref.global "public" @inA : memref<16x8xi16> // CHECK: %[[TILE_0_0:.*]] = aie.tile(2, 0) // CHECK: %[[TILE_0_2:.*]] = aie.tile(2, 2) -// CHECK: %[[OUTC_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 4) {init = 0 : i8, sym_name = "outC_cons_prod_lock"} -// CHECK: %[[OUTC_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 5) {init = 0 : i8, sym_name = "outC_cons_cons_lock"} +// CHECK: %[[OUTC_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]]) {init = 0 : i8, sym_name = "outC_cons_prod_lock"} +// CHECK: %[[OUTC_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]]) {init = 0 : i8, sym_name = "outC_cons_cons_lock"} // CHECK: %[[OUTC_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "outC_buff_0"} : memref<16x16xi16> // CHECK: %[[OUTC_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "outC_buff_1"} : memref<16x16xi16> -// CHECK: %[[OUTC_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 4) {init = 2 : i8, sym_name = "outC_prod_lock"} -// CHECK: %[[OUTC_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 5) {init = 0 : i8, sym_name = "outC_cons_lock"} +// CHECK: %[[OUTC_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]]) {init = 2 : i8, sym_name = "outC_prod_lock"} +// CHECK: %[[OUTC_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]]) {init = 0 : i8, sym_name = "outC_cons_lock"} // CHECK: %[[INB_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "inB_cons_buff_0"} : memref<8x16xi16> // CHECK: %[[INB_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "inB_cons_buff_1"} : memref<8x16xi16> -// CHECK: %[[INB_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 2) {init = 2 : i8, sym_name = "inB_cons_prod_lock"} -// CHECK: %[[INB_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 3) {init = 0 : i8, sym_name = "inB_cons_cons_lock"} -// CHECK: %[[INB_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 2) {init = 0 : i8, sym_name = "inB_prod_lock"} -// CHECK: %[[INB_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 3) {init = 0 : i8, sym_name = "inB_cons_lock"} +// CHECK: %[[INB_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]]) {init = 2 : i8, sym_name = "inB_cons_prod_lock"} +// CHECK: %[[INB_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]]) {init = 0 : i8, sym_name = "inB_cons_cons_lock"} +// CHECK: %[[INB_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]]) {init = 0 : i8, sym_name = "inB_prod_lock"} +// CHECK: %[[INB_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]]) {init = 0 : i8, sym_name = "inB_cons_lock"} // CHECK: %[[INA_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "inA_cons_buff_0"} : memref<16x8xi16> // CHECK: %[[INA_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "inA_cons_buff_1"} : memref<16x8xi16> -// CHECK: %[[INA_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 0) {init = 2 : i8, sym_name = "inA_cons_prod_lock"} -// CHECK: %[[INA_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 1) {init = 0 : i8, sym_name = "inA_cons_cons_lock"} -// CHECK: %[[INA_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 0) {init = 0 : i8, sym_name = "inA_prod_lock"} -// CHECK: %[[INA_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 1) {init = 0 : i8, sym_name = "inA_cons_lock"} +// CHECK: %[[INA_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]]) {init = 2 : i8, sym_name = "inA_cons_prod_lock"} +// CHECK: %[[INA_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]]) {init = 0 : i8, sym_name = "inA_cons_cons_lock"} +// CHECK: %[[INA_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]]) {init = 0 : i8, sym_name = "inA_prod_lock"} +// CHECK: %[[INA_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]]) {init = 0 : i8, sym_name = "inA_cons_lock"} // CHECK: aie.flow(%[[TILE_0_0]], DMA : 0, %[[TILE_0_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_0_0]], DMA : 1, %[[TILE_0_2]], DMA : 1) // CHECK: aie.flow(%[[TILE_0_2]], DMA : 0, %[[TILE_0_0]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/memTile_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/memTile_test.mlir index 7d65aa7d3..18b1ed433 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/memTile_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/memTile_test.mlir @@ -8,12 +8,12 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[OF_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of_cons_prod_lock"} -// CHECK: %[[OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of_cons_cons_lock"} +// CHECK: %[[OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "of_cons_prod_lock"} +// CHECK: %[[OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "of_cons_cons_lock"} // CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "of_buff_0"} : memref<16xi32> // CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "of_buff_1"} : memref<16xi32> -// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i8, sym_name = "of_prod_lock"} -// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i8, sym_name = "of_cons_lock"} +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 2 : i8, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]]) {init = 0 : i8, sym_name = "of_cons_lock"} // CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { // CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_base_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_base_AIE2.mlir index 9a1c88d29..ad58eb549 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_base_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_base_AIE2.mlir @@ -11,24 +11,24 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<256xi32> -// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} // CHECK: %[[OF1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_0"} : memref<256xi32> // CHECK: %[[OF1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_1"} : memref<256xi32> -// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i8, sym_name = "of1_prod_lock"} -// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i8, sym_name = "of1_cons_lock"} +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of1_cons_lock"} // CHECK: %[[OF0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_cons_buff_1"} : memref<256xi32> // CHECK: %[[OF0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_cons_buff_2"} : memref<256xi32> // CHECK: %[[OF0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_cons_buff_3"} : memref<256xi32> -// CHECK: %[[OF0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 4 : i8, sym_name = "of0_cons_prod_lock"} -// CHECK: %[[OF0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i8, sym_name = "of0_cons_cons_lock"} +// CHECK: %[[OF0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]]) {init = 4 : i8, sym_name = "of0_cons_prod_lock"} +// CHECK: %[[OF0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]]) {init = 0 : i8, sym_name = "of0_cons_cons_lock"} // CHECK: %[[OF0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_0"} : memref<256xi32> // CHECK: %[[OF0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_1"} : memref<256xi32> // CHECK: %[[OF0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_2"} : memref<256xi32> // CHECK: %[[OF0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_3"} : memref<256xi32> -// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "of0_prod_lock"} -// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of0_cons_lock"} +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 4 : i8, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of0_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_1_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_2]], DMA : 1, %[[TILE_3_3]], DMA : 0) // CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { diff --git a/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_distribute_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_distribute_AIE2.mlir index 3596351cf..da6dcd9f4 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_distribute_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_distribute_AIE2.mlir @@ -14,18 +14,18 @@ // CHECK: %[[TILE_2_3:.*]] = aie.tile(3, 3) // CHECK: %[[OF2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of2_cons_buff_0"} : memref<128xi32> // CHECK: %[[OF2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of2_cons_buff_1"} : memref<128xi32> -// CHECK: %[[OF2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "of2_cons_prod_lock"} -// CHECK: %[[OF2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "of2_cons_cons_lock"} +// CHECK: %[[OF2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 2 : i8, sym_name = "of2_cons_prod_lock"} +// CHECK: %[[OF2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 0 : i8, sym_name = "of2_cons_cons_lock"} // CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of1_cons_buff_0"} : memref<128xi32> // CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of1_cons_buff_1"} : memref<128xi32> -// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} // CHECK: %[[OF0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_1]]) {sym_name = "of0_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_1]]) {sym_name = "of0_cons_buff_1"} : memref<256xi32> -// CHECK: %[[OF0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_1]], 0) {init = 4 : i8, sym_name = "of0_cons_prod_lock"} -// CHECK: %[[OF0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_1]], 1) {init = 0 : i8, sym_name = "of0_cons_cons_lock"} -// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_0]], 0) {init = 0 : i8, sym_name = "of0_prod_lock"} -// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_0]], 1) {init = 0 : i8, sym_name = "of0_cons_lock"} +// CHECK: %[[OF0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_1]]) {init = 4 : i8, sym_name = "of0_cons_prod_lock"} +// CHECK: %[[OF0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_1]]) {init = 0 : i8, sym_name = "of0_cons_cons_lock"} +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_0]]) {init = 0 : i8, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_0]]) {init = 0 : i8, sym_name = "of0_cons_lock"} // CHECK: aie.flow(%[[TILE_1_0]], DMA : 0, %[[TILE_1_1]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_1]], DMA : 1, %[[TILE_2_3]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_multiple_consumers_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_multiple_consumers_AIE2.mlir index ddb070dfa..6fbce4ca6 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_multiple_consumers_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/nd_dma_multiple_consumers_AIE2.mlir @@ -16,38 +16,38 @@ // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[OF3_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of3_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF3_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of3_cons_buff_1"} : memref<256xi32> -// CHECK: %[[OF3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "of3_cons_prod_lock"} -// CHECK: %[[OF3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "of3_cons_cons_lock"} +// CHECK: %[[OF3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 2 : i8, sym_name = "of3_cons_prod_lock"} +// CHECK: %[[OF3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 0 : i8, sym_name = "of3_cons_cons_lock"} // CHECK: %[[OF3_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of3_buff_0"} : memref<256xi32> // CHECK: %[[OF3_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of3_buff_1"} : memref<256xi32> -// CHECK: %[[OF3_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of3_prod_lock"} -// CHECK: %[[OF3_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of3_cons_lock"} +// CHECK: %[[OF3_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "of3_prod_lock"} +// CHECK: %[[OF3_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "of3_cons_lock"} // CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<256xi32> -// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 2) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 3) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 2 : i8, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "of1_cons_cons_lock"} // CHECK: %[[OF1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_0"} : memref<256xi32> // CHECK: %[[OF1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_1"} : memref<256xi32> -// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i8, sym_name = "of1_prod_lock"} -// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i8, sym_name = "of1_cons_lock"} +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of1_cons_lock"} // CHECK: %[[OF0_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_0_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF0_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_0_cons_buff_1"} : memref<256xi32> // CHECK: %[[OF0_0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_0_cons_buff_2"} : memref<256xi32> // CHECK: %[[OF0_0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_0_cons_buff_3"} : memref<256xi32> -// CHECK: %[[OF0_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 4 : i8, sym_name = "of0_0_cons_prod_lock"} -// CHECK: %[[OF0_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i8, sym_name = "of0_0_cons_cons_lock"} +// CHECK: %[[OF0_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]]) {init = 4 : i8, sym_name = "of0_0_cons_prod_lock"} +// CHECK: %[[OF0_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]]) {init = 0 : i8, sym_name = "of0_0_cons_cons_lock"} // CHECK: %[[OF0_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of0_1_cons_buff_0"} : memref<256xi32> // CHECK: %[[OF0_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of0_1_cons_buff_1"} : memref<256xi32> // CHECK: %[[OF0_1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of0_1_cons_buff_2"} : memref<256xi32> // CHECK: %[[OF0_1_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of0_1_cons_buff_3"} : memref<256xi32> -// CHECK: %[[OF0_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 4 : i8, sym_name = "of0_1_cons_prod_lock"} -// CHECK: %[[OF0_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "of0_1_cons_cons_lock"} +// CHECK: %[[OF0_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 4 : i8, sym_name = "of0_1_cons_prod_lock"} +// CHECK: %[[OF0_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "of0_1_cons_cons_lock"} // CHECK: %[[OF0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_0"} : memref<256xi32> // CHECK: %[[OF0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_1"} : memref<256xi32> // CHECK: %[[OF0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_2"} : memref<256xi32> // CHECK: %[[OF0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_3"} : memref<256xi32> -// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "of0_prod_lock"} -// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of0_cons_lock"} +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 4 : i8, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of0_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_1_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_1_2]], DMA : 1, %[[TILE_3_3]], DMA : 1) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/nested_loop_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/nested_loop_test.mlir index 5fb1319f9..8075dad93 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/nested_loop_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/nested_loop_test.mlir @@ -16,38 +16,38 @@ // CHECK: %[[IN8_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in8_cons_buff_1"} : memref<32x32xi32, 1> // CHECK: %[[IN8_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in8_cons_buff_2"} : memref<32x32xi32, 1> // CHECK: %[[IN8_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in8_cons_buff_3"} : memref<32x32xi32, 1> -// CHECK: %[[IN8_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 4) {init = 4 : i8, sym_name = "in8_cons_prod_lock"} -// CHECK: %[[IN8_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 5) {init = 0 : i8, sym_name = "in8_cons_cons_lock"} +// CHECK: %[[IN8_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]]) {init = 4 : i8, sym_name = "in8_cons_prod_lock"} +// CHECK: %[[IN8_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]]) {init = 0 : i8, sym_name = "in8_cons_cons_lock"} // CHECK: %[[IN8_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in8_buff_0"} : memref<32x32xi32, 1> // CHECK: %[[IN8_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in8_buff_1"} : memref<32x32xi32, 1> -// CHECK: %[[IN8_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 4) {init = 2 : i8, sym_name = "in8_prod_lock"} -// CHECK: %[[IN8_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 5) {init = 0 : i8, sym_name = "in8_cons_lock"} +// CHECK: %[[IN8_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "in8_prod_lock"} +// CHECK: %[[IN8_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "in8_cons_lock"} // CHECK: %[[IN7_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in7_cons_buff_0"} : memref<64x32xi32, 1> // CHECK: %[[IN7_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in7_cons_buff_1"} : memref<64x32xi32, 1> -// CHECK: %[[IN7_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i8, sym_name = "in7_cons_prod_lock"} -// CHECK: %[[IN7_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i8, sym_name = "in7_cons_cons_lock"} +// CHECK: %[[IN7_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "in7_cons_prod_lock"} +// CHECK: %[[IN7_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "in7_cons_cons_lock"} // CHECK: %[[IN7_BUFF_0:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in7_buff_0"} : memref<64x32xi32, 1> // CHECK: %[[IN7_BUFF_1:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in7_buff_1"} : memref<64x32xi32, 1> // CHECK: %[[IN7_BUFF_2:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in7_buff_2"} : memref<64x32xi32, 1> // CHECK: %[[IN7_BUFF_3:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in7_buff_3"} : memref<64x32xi32, 1> -// CHECK: %[[IN7_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 2) {init = 4 : i8, sym_name = "in7_prod_lock"} -// CHECK: %[[IN7_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 3) {init = 0 : i8, sym_name = "in7_cons_lock"} +// CHECK: %[[IN7_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]]) {init = 4 : i8, sym_name = "in7_prod_lock"} +// CHECK: %[[IN7_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]]) {init = 0 : i8, sym_name = "in7_cons_lock"} // CHECK: %[[IN2_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "in2_0_cons_buff_0"} : memref<32x64xi32, 1> // CHECK: %[[IN2_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "in2_0_cons_buff_1"} : memref<32x64xi32, 1> // CHECK: %[[IN2_0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "in2_0_cons_buff_2"} : memref<32x64xi32, 1> // CHECK: %[[IN2_0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "in2_0_cons_buff_3"} : memref<32x64xi32, 1> -// CHECK: %[[IN2_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 0) {init = 4 : i8, sym_name = "in2_0_cons_prod_lock"} -// CHECK: %[[IN2_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 1) {init = 0 : i8, sym_name = "in2_0_cons_cons_lock"} +// CHECK: %[[IN2_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]]) {init = 4 : i8, sym_name = "in2_0_cons_prod_lock"} +// CHECK: %[[IN2_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]]) {init = 0 : i8, sym_name = "in2_0_cons_cons_lock"} // CHECK: %[[IN2_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in2_1_cons_buff_0"} : memref<32x64xi32, 1> // CHECK: %[[IN2_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in2_1_cons_buff_1"} : memref<32x64xi32, 1> -// CHECK: %[[IN2_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "in2_1_cons_prod_lock"} -// CHECK: %[[IN2_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "in2_1_cons_cons_lock"} +// CHECK: %[[IN2_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "in2_1_cons_prod_lock"} +// CHECK: %[[IN2_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "in2_1_cons_cons_lock"} // CHECK: %[[IN2_BUFF_0:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in2_buff_0"} : memref<32x64xi32, 1> // CHECK: %[[IN2_BUFF_1:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in2_buff_1"} : memref<32x64xi32, 1> // CHECK: %[[IN2_BUFF_2:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in2_buff_2"} : memref<32x64xi32, 1> // CHECK: %[[IN2_BUFF_3:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in2_buff_3"} : memref<32x64xi32, 1> -// CHECK: %[[IN2_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 0) {init = 4 : i8, sym_name = "in2_prod_lock"} -// CHECK: %[[IN2_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 1) {init = 0 : i8, sym_name = "in2_cons_lock"} +// CHECK: %[[IN2_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]]) {init = 4 : i8, sym_name = "in2_prod_lock"} +// CHECK: %[[IN2_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]]) {init = 0 : i8, sym_name = "in2_cons_lock"} // CHECK: aie.flow(%[[TILE_0_1]], DMA : 0, %[[TILE_1_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_0_1]], DMA : 0, %[[TILE_0_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_0_1]], DMA : 1, %[[TILE_1_2]], DMA : 1) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_1.mlir index 283ea35f9..20b3faef7 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_1.mlir @@ -8,12 +8,12 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OBJFIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> // CHECK: %[[OBJFIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "objfifo_cons_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "objfifo_cons_cons_lock"} +// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 2 : i8, sym_name = "objfifo_cons_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "objfifo_cons_cons_lock"} // CHECK: %[[OBJFIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> // CHECK: %[[OBJFIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> -// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "objfifo_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "objfifo_cons_lock"} +// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "objfifo_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "objfifo_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return diff --git a/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_2.mlir index d6a291c53..a1d712fd0 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_2.mlir @@ -10,12 +10,12 @@ // CHECK: %[[OBJFIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> // CHECK: %[[OBJFIFO_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_2"} : memref<16xi32> // CHECK: %[[OBJFIFO_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_3"} : memref<16xi32> -// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 4 : i8, sym_name = "objfifo_cons_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "objfifo_cons_cons_lock"} +// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 4 : i8, sym_name = "objfifo_cons_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "objfifo_cons_cons_lock"} // CHECK: %[[OBJFIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> // CHECK: %[[OBJFIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> -// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "objfifo_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "objfifo_cons_lock"} +// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "objfifo_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "objfifo_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return diff --git a/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_AIE2.mlir index 17ddfca1f..2c2f738f7 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/non_adjacency_test_AIE2.mlir @@ -8,12 +8,12 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OF_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "of_cons_prod_lock"} -// CHECK: %[[OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "of_cons_cons_lock"} +// CHECK: %[[OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 2 : i8, sym_name = "of_cons_prod_lock"} +// CHECK: %[[OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "of_cons_cons_lock"} // CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> // CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_1"} : memref<16xi32> -// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i8, sym_name = "of_prod_lock"} -// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of_cons_lock"} +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 2 : i8, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of_cons_lock"} // CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return diff --git a/compiler/plugins/target/AMD-AIE/aie/test/register_external_buffers_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/register_external_buffers_test.mlir index 24a142549..bb87d0200 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/register_external_buffers_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/register_external_buffers_test.mlir @@ -9,10 +9,10 @@ // CHECK: %[[EXT_OF_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "ext_of_cons_buff_0"} : memref<16xi32> // CHECK: %[[EXT_OF_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "ext_of_cons_buff_1"} : memref<16xi32> // CHECK: %[[EXT_OF_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "ext_of_cons_buff_2"} : memref<16xi32> -// CHECK: %[[EXT_OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 0) {init = 3 : i8, sym_name = "ext_of_cons_prod_lock"} -// CHECK: %[[EXT_OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 1) {init = 0 : i8, sym_name = "ext_of_cons_cons_lock"} -// CHECK: %[[EXT_OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_0]], 0) {init = 0 : i8, sym_name = "ext_of_prod_lock"} -// CHECK: %[[EXT_OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_0]], 1) {init = 0 : i8, sym_name = "ext_of_cons_lock"} +// CHECK: %[[EXT_OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_2]]) {init = 3 : i8, sym_name = "ext_of_cons_prod_lock"} +// CHECK: %[[EXT_OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_2]]) {init = 0 : i8, sym_name = "ext_of_cons_cons_lock"} +// CHECK: %[[EXT_OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_0]]) {init = 0 : i8, sym_name = "ext_of_prod_lock"} +// CHECK: %[[EXT_OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_0]]) {init = 0 : i8, sym_name = "ext_of_cons_lock"} // CHECK: aie.flow(%[[TILE_3_0]], DMA : 0, %[[TILE_3_2]], DMA : 0) // CHECK: %[[EXT_BUFFER_IN:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: memref<16xi32>) { diff --git a/compiler/plugins/target/AMD-AIE/aie/test/same_core_producer_consumer_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/same_core_producer_consumer_test.mlir index a68be25a4..5d25c3487 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/same_core_producer_consumer_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/same_core_producer_consumer_test.mlir @@ -7,8 +7,8 @@ // CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> // CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_1"} : memref<16xi32> // CHECK: %[[OF_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_2"} : memref<16xi32> -// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 3 : i8, sym_name = "of_prod_lock"} -// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of_cons_lock"} +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 3 : i8, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of_cons_lock"} // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/shimRow_mem_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/shimRow_mem_test.mlir index 0be4546c0..4cce02d77 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/shimRow_mem_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/shimRow_mem_test.mlir @@ -9,10 +9,10 @@ // CHECK: %[[OBJFIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> // CHECK: %[[OBJFIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> // CHECK: %[[OBJFIFO_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "objfifo_cons_buff_2"} : memref<16xi32> -// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 0) {init = 3 : i8, sym_name = "objfifo_cons_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_2]], 1) {init = 0 : i8, sym_name = "objfifo_cons_cons_lock"} -// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_0]], 0) {init = 0 : i8, sym_name = "objfifo_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_0]], 1) {init = 0 : i8, sym_name = "objfifo_cons_lock"} +// CHECK: %[[OBJFIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_2]]) {init = 3 : i8, sym_name = "objfifo_cons_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_2]]) {init = 0 : i8, sym_name = "objfifo_cons_cons_lock"} +// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_0]]) {init = 0 : i8, sym_name = "objfifo_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_0]]) {init = 0 : i8, sym_name = "objfifo_cons_lock"} // CHECK: aie.flow(%[[TILE_3_0]], DMA : 0, %[[TILE_3_2]], DMA : 0) // CHECK: %[[EXT_BUFFER_IN:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: memref<16xi32>) { diff --git a/compiler/plugins/target/AMD-AIE/aie/test/shim_AIE2_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/shim_AIE2_test.mlir index c98359584..cd48a2674 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/shim_AIE2_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/shim_AIE2_test.mlir @@ -8,18 +8,18 @@ // CHECK: memref.global "public" @of_in : memref<16xi32> // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[OF_OUT_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 2) {init = 0 : i8, sym_name = "of_out_cons_prod_lock"} -// CHECK: %[[OF_OUT_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 3) {init = 0 : i8, sym_name = "of_out_cons_cons_lock"} +// CHECK: %[[OF_OUT_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_out_cons_prod_lock"} +// CHECK: %[[OF_OUT_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_out_cons_cons_lock"} // CHECK: %[[OF_OUT_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_buff_0"} : memref<16xi32> // CHECK: %[[OF_OUT_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_buff_1"} : memref<16xi32> -// CHECK: %[[OF_OUT_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i8, sym_name = "of_out_prod_lock"} -// CHECK: %[[OF_OUT_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i8, sym_name = "of_out_cons_lock"} +// CHECK: %[[OF_OUT_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "of_out_prod_lock"} +// CHECK: %[[OF_OUT_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "of_out_cons_lock"} // CHECK: %[[OF_IN_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF_IN_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF_IN_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of_in_cons_prod_lock"} -// CHECK: %[[OF_IN_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of_in_cons_cons_lock"} -// CHECK: %[[OF_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "of_in_prod_lock"} -// CHECK: %[[OF_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "of_in_cons_lock"} +// CHECK: %[[OF_IN_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "of_in_cons_prod_lock"} +// CHECK: %[[OF_IN_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "of_in_cons_cons_lock"} +// CHECK: %[[OF_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_in_prod_lock"} +// CHECK: %[[OF_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_in_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_2]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_0]], DMA : 0) // CHECK: %[[EXT_BUFFER_IN:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/test/shim_broadcast_test.mlir b/compiler/plugins/target/AMD-AIE/aie/test/shim_broadcast_test.mlir index 93293aa57..7a0889d6d 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/shim_broadcast_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/shim_broadcast_test.mlir @@ -12,18 +12,18 @@ // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[OF_IN_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF_IN_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i8, sym_name = "of_in_0_cons_prod_lock"} -// CHECK: %[[OF_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i8, sym_name = "of_in_0_cons_cons_lock"} +// CHECK: %[[OF_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 2 : i8, sym_name = "of_in_0_cons_prod_lock"} +// CHECK: %[[OF_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]]) {init = 0 : i8, sym_name = "of_in_0_cons_cons_lock"} // CHECK: %[[OF_IN_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF_IN_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i8, sym_name = "of_in_1_cons_prod_lock"} -// CHECK: %[[OF_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i8, sym_name = "of_in_1_cons_cons_lock"} +// CHECK: %[[OF_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 2 : i8, sym_name = "of_in_1_cons_prod_lock"} +// CHECK: %[[OF_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]]) {init = 0 : i8, sym_name = "of_in_1_cons_cons_lock"} // CHECK: %[[OF_IN_2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of_in_2_cons_buff_0"} : memref<16xi32> // CHECK: %[[OF_IN_2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of_in_2_cons_buff_1"} : memref<16xi32> -// CHECK: %[[OF_IN_2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i8, sym_name = "of_in_2_cons_prod_lock"} -// CHECK: %[[OF_IN_2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i8, sym_name = "of_in_2_cons_cons_lock"} -// CHECK: %[[OF_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i8, sym_name = "of_in_prod_lock"} -// CHECK: %[[OF_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i8, sym_name = "of_in_cons_lock"} +// CHECK: %[[OF_IN_2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 2 : i8, sym_name = "of_in_2_cons_prod_lock"} +// CHECK: %[[OF_IN_2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]]) {init = 0 : i8, sym_name = "of_in_2_cons_cons_lock"} +// CHECK: %[[OF_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_in_prod_lock"} +// CHECK: %[[OF_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]]) {init = 0 : i8, sym_name = "of_in_cons_lock"} // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_3]], DMA : 0) // CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_2]], DMA : 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/test/subview_test_1.mlir b/compiler/plugins/target/AMD-AIE/aie/test/subview_test_1.mlir index fc3db0d5b..766e9da9b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/subview_test_1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/subview_test_1.mlir @@ -9,8 +9,8 @@ // CHECK: %[[OBJFIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> // CHECK: %[[OBJFIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_2"} : memref<16xi32> // CHECK: %[[OBJFIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_3"} : memref<16xi32> -// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "objfifo_prod_lock"} -// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "objfifo_cons_lock"} +// CHECK: %[[OBJFIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 4 : i8, sym_name = "objfifo_prod_lock"} +// CHECK: %[[OBJFIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "objfifo_cons_lock"} // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/subview_test_2.mlir b/compiler/plugins/target/AMD-AIE/aie/test/subview_test_2.mlir index 8054e3ada..6a91f6a80 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/subview_test_2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/subview_test_2.mlir @@ -9,14 +9,14 @@ // CHECK: %[[OF2_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of2_buff_0"} : memref<16xi32> // CHECK: %[[OF2_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of2_buff_1"} : memref<16xi32> // CHECK: %[[OF2_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of2_buff_2"} : memref<16xi32> -// CHECK: %[[OF2_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 3 : i8, sym_name = "of2_prod_lock"} -// CHECK: %[[OF2_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i8, sym_name = "of2_cons_lock"} +// CHECK: %[[OF2_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 3 : i8, sym_name = "of2_prod_lock"} +// CHECK: %[[OF2_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of2_cons_lock"} // CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> // CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_1"} : memref<16xi32> // CHECK: %[[OF_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_2"} : memref<16xi32> // CHECK: %[[OF_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_3"} : memref<16xi32> -// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "of_prod_lock"} -// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of_cons_lock"} +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 4 : i8, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of_cons_lock"} // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } diff --git a/compiler/plugins/target/AMD-AIE/aie/test/subview_test_3.mlir b/compiler/plugins/target/AMD-AIE/aie/test/subview_test_3.mlir index ced67e903..1df427fbd 100644 --- a/compiler/plugins/target/AMD-AIE/aie/test/subview_test_3.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/test/subview_test_3.mlir @@ -9,14 +9,14 @@ // CHECK: %[[OF2_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of2_buff_0"} : memref<16xi32> // CHECK: %[[OF2_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of2_buff_1"} : memref<16xi32> // CHECK: %[[OF2_BUFF_2:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of2_buff_2"} : memref<16xi32> -// CHECK: %[[OF2_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 3 : i8, sym_name = "of2_prod_lock"} -// CHECK: %[[OF2_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i8, sym_name = "of2_cons_lock"} +// CHECK: %[[OF2_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]]) {init = 3 : i8, sym_name = "of2_prod_lock"} +// CHECK: %[[OF2_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]]) {init = 0 : i8, sym_name = "of2_cons_lock"} // CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> // CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_1"} : memref<16xi32> // CHECK: %[[OF_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_2"} : memref<16xi32> // CHECK: %[[OF_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_3"} : memref<16xi32> -// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i8, sym_name = "of_prod_lock"} -// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i8, sym_name = "of_cons_lock"} +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 4 : i8, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]]) {init = 0 : i8, sym_name = "of_cons_lock"} // CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: }