From 3a3382d0a4877a63d1e5f20121de04fcd5096bc8 Mon Sep 17 00:00:00 2001 From: emb4fun Date: Sun, 7 Nov 2021 21:25:26 +0100 Subject: [PATCH 1/3] Added data mask support --- sdram.vhd | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/sdram.vhd b/sdram.vhd index a4d7162..f1d6b36 100644 --- a/sdram.vhd +++ b/sdram.vhd @@ -92,6 +92,9 @@ entity sdram is -- input data bus data : in std_logic_vector(DATA_WIDTH-1 downto 0); + -- input data mask + mask : in std_logic_vector(3 downto 0); + -- When the write enable signal is asserted, a write operation will be performed. we : in std_logic; @@ -216,6 +219,7 @@ architecture arch of sdram is signal addr_reg : unsigned(SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH+SDRAM_BANK_WIDTH-1 downto 0); signal data_reg : std_logic_vector(DATA_WIDTH-1 downto 0); signal we_reg : std_logic; + signal mask_reg : std_logic_vector(3 downto 0); signal q_reg : std_logic_vector(DATA_WIDTH-1 downto 0); -- aliases to decode the address register @@ -367,6 +371,7 @@ begin addr_reg <= shift_left(resize(addr, addr_reg'length), 1); data_reg <= data; we_reg <= we; + mask_reg <= not mask; end if; end if; end process; @@ -440,6 +445,6 @@ begin sdram_dq <= data_reg((BURST_LENGTH-wait_counter)*SDRAM_DATA_WIDTH-1 downto (BURST_LENGTH-wait_counter-1)*SDRAM_DATA_WIDTH) when state = WRITE else (others => 'Z'); -- set SDRAM data mask - sdram_dqmh <= '0'; - sdram_dqml <= '0'; + sdram_dqmh <= mask_reg(3) when (wait_counter = 0) else mask_reg(1); + sdram_dqml <= mask_reg(2) when (wait_counter = 0) else mask_reg(0); end architecture arch; From 26f6c212ff197402ee3e1d700bfc22dec5a81531 Mon Sep 17 00:00:00 2001 From: emb4fun Date: Fri, 12 Nov 2021 19:59:55 +0100 Subject: [PATCH 2/3] Reworked signals for sdram_dqmh and sdram_dqml --- sdram.vhd | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/sdram.vhd b/sdram.vhd index f1d6b36..23eb8fc 100644 --- a/sdram.vhd +++ b/sdram.vhd @@ -445,6 +445,24 @@ begin sdram_dq <= data_reg((BURST_LENGTH-wait_counter)*SDRAM_DATA_WIDTH-1 downto (BURST_LENGTH-wait_counter-1)*SDRAM_DATA_WIDTH) when state = WRITE else (others => 'Z'); -- set SDRAM data mask - sdram_dqmh <= mask_reg(3) when (wait_counter = 0) else mask_reg(1); - sdram_dqml <= mask_reg(2) when (wait_counter = 0) else mask_reg(0); + --sdram_dqmh <= mask_reg(3) when (wait_counter = 0) else mask_reg(1); + --sdram_dqml <= mask_reg(2) when (wait_counter = 0) else mask_reg(0); + + + process (state, wait_counter) + begin + if (state = WRITE) then + if (wait_counter = 0) then + sdram_dqmh <= mask_reg(3); + sdram_dqml <= mask_reg(2); + else + sdram_dqmh <= mask_reg(1); + sdram_dqml <= mask_reg(0); + end if; + else + sdram_dqmh <= '0'; + sdram_dqml <= '0'; + end if; + end process; + end architecture arch; From 2c09c4a3bcafdb4e54f77e8317a6846f56601ea5 Mon Sep 17 00:00:00 2001 From: emb4fun Date: Sat, 13 Nov 2021 09:41:22 +0100 Subject: [PATCH 3/3] Corrected warning "signal "mask_reg" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" --- sdram.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sdram.vhd b/sdram.vhd index 23eb8fc..25e081e 100644 --- a/sdram.vhd +++ b/sdram.vhd @@ -449,7 +449,7 @@ begin --sdram_dqml <= mask_reg(2) when (wait_counter = 0) else mask_reg(0); - process (state, wait_counter) + process (state, wait_counter, mask_reg) begin if (state = WRITE) then if (wait_counter = 0) then