From cd176e69d8ed434106756a8548246f4f7e63ade9 Mon Sep 17 00:00:00 2001 From: snori Date: Wed, 28 Mar 2018 13:48:05 -0700 Subject: [PATCH] Added pushback on the bready path of CVIF and MCIF when multi-threaded fifo output is not valid --- vmod/nvdla/nocif/NV_NVDLA_CVIF_WRITE_eg.v | 14 +++++++++++--- vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_eg.v | 13 ++++++++++--- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/vmod/nvdla/nocif/NV_NVDLA_CVIF_WRITE_eg.v b/vmod/nvdla/nocif/NV_NVDLA_CVIF_WRITE_eg.v index 255d8f1a..d0f58f90 100644 --- a/vmod/nvdla/nocif/NV_NVDLA_CVIF_WRITE_eg.v +++ b/vmod/nvdla/nocif/NV_NVDLA_CVIF_WRITE_eg.v @@ -126,20 +126,28 @@ wire dma4_vld; //assign noc2cvif_axi_b_bresp_NC = noc2cvif_axi_b_bresp; //assign noc2cvif_axi_b_buser_NC = noc2cvif_axi_b_buser; //assign noc2cvif_axi_b_bid_NC = noc2cvif_axi_b_bid; -assign noc2cvif_axi_b_bready = 1'b1; // NO pushback is needed on AXI B channel; +wire cq_vld = (!cq_rd0_pvld & cq_rd0_prdy) | +(!cq_rd1_pvld & cq_rd1_prdy) | +(!cq_rd2_pvld & cq_rd2_prdy) | +(!cq_rd3_pvld & cq_rd3_prdy) | +(!cq_rd4_pvld & cq_rd4_prdy); + +assign noc2cvif_axi_b_bready = !cq_vld; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin if (!nvdla_core_rstn) begin iflop_axi_vld <= 1'b0; end else begin - iflop_axi_vld <= noc2cvif_axi_b_bvalid; + if (noc2cvif_axi_b_bready) + iflop_axi_vld <= noc2cvif_axi_b_bvalid; end end always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin if (!nvdla_core_rstn) begin iflop_axi_axid <= {3{1'b0}}; end else begin - if ((noc2cvif_axi_b_bvalid) == 1'b1) begin + if ((noc2cvif_axi_b_bvalid & noc2cvif_axi_b_bready) == 1'b1) begin iflop_axi_axid <= noc2cvif_axi_b_bid[2:0]; // VCS coverage off end else if ((noc2cvif_axi_b_bvalid) == 1'b0) begin diff --git a/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_eg.v b/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_eg.v index a41acbae..e7149248 100644 --- a/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_eg.v +++ b/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_eg.v @@ -128,20 +128,27 @@ wire [7:0] noc2mcif_axi_b_bid_NC; //assign noc2mcif_axi_b_bresp_NC = noc2mcif_axi_b_bresp; //stepheng. //assign noc2mcif_axi_b_buser_NC = noc2mcif_axi_b_buser; assign noc2mcif_axi_b_bid_NC = noc2mcif_axi_b_bid; -assign noc2mcif_axi_b_bready = 1'b1; // NO pushback is needed on AXI B channel; +wire cq_vld = (!cq_rd0_pvld & cq_rd0_prdy) | +(!cq_rd1_pvld & cq_rd1_prdy) | +(!cq_rd2_pvld & cq_rd2_prdy) | +(!cq_rd3_pvld & cq_rd3_prdy) | +(!cq_rd4_pvld & cq_rd4_prdy); + +assign noc2mcif_axi_b_bready = !cq_vld; always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin if (!nvdla_core_rstn) begin iflop_axi_vld <= 1'b0; end else begin - iflop_axi_vld <= noc2mcif_axi_b_bvalid; + if (noc2mcif_axi_b_bready) + iflop_axi_vld <= noc2mcif_axi_b_bvalid; end end always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin if (!nvdla_core_rstn) begin iflop_axi_axid <= {3{1'b0}}; end else begin - if ((noc2mcif_axi_b_bvalid) == 1'b1) begin + if ((noc2mcif_axi_b_bvalid & noc2mcif_axi_b_bready) == 1'b1) begin iflop_axi_axid <= noc2mcif_axi_b_bid[2:0]; // VCS coverage off end else if ((noc2mcif_axi_b_bvalid) == 1'b0) begin