From a299f595102464034894fa6c0aa9652c2ca31b30 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Thu, 21 Mar 2024 03:29:27 -0400 Subject: [PATCH 1/9] Super basic gantry model and subscriber --- mercury-app/src/hw_ifc/CMakeLists.txt | 2 +- mercury-app/src/hw_ifc/src/gantry_model.rs | 102 +++++++++++++-- mercury-app/src/hw_ifc/src/gantry_sub.rs | 141 +++++++-------------- mercury-app/src/hw_srv/srv/calibrate.srv | 2 + 4 files changed, 137 insertions(+), 110 deletions(-) create mode 100644 mercury-app/src/hw_srv/srv/calibrate.srv diff --git a/mercury-app/src/hw_ifc/CMakeLists.txt b/mercury-app/src/hw_ifc/CMakeLists.txt index c045d36..297743c 100644 --- a/mercury-app/src/hw_ifc/CMakeLists.txt +++ b/mercury-app/src/hw_ifc/CMakeLists.txt @@ -151,7 +151,7 @@ include_directories( add_custom_target(hw_ifc ALL - COMMAND cargo build -p mercury --bin drive_sub #--release + COMMAND cargo build -p mercury --release WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/../src/hw_ifc #COMMAND ${CMAKE_COMMAND} -E copy ${CMAKE_BINARY_DIR}/cargo/release/my-project-binary ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/my-project-binary COMMENT "Build Mercury..." diff --git a/mercury-app/src/hw_ifc/src/gantry_model.rs b/mercury-app/src/hw_ifc/src/gantry_model.rs index 07b2539..1154ec6 100644 --- a/mercury-app/src/hw_ifc/src/gantry_model.rs +++ b/mercury-app/src/hw_ifc/src/gantry_model.rs @@ -1,22 +1,98 @@ -pub struct DriveMotorModel { - wheel_base: f64, - wheel_radius: f64, +/* Model Describing the Behavior of the Gantry */ + +use std::ops::{Index, IndexMut}; + +pub enum GantryAxes { + GantryX, + GantryY, + GantryZ, +} + +pub struct StepperCtrlCmd { + pub steps: i32, + speed: f64, +} + +pub struct StepperCtrlCmdGroup { + x: StepperCtrlCmd, + y: StepperCtrlCmd, + z: StepperCtrlCmd, +} + +impl Index for StepperCtrlCmdGroup { + type Output = StepperCtrlCmd; + + fn index(&self, side: GantryAxes) -> &Self::Output { + match side { + GantryAxes::GantryX => &self.x, + GantryAxes::GantryY => &self.y, + GantryAxes::GantryZ => &self.z, + } + } } -impl DriveMotorModel { - pub fn new(wheel_base : f64, wheel_radius : f64) -> DriveMotorModel{ - DriveMotorModel { - wheel_base, - wheel_radius +impl IndexMut for StepperCtrlCmdGroup { + fn index_mut(&mut self, side: GantryAxes) -> &mut Self::Output { + match side { + GantryAxes::GantryX => &mut self.x, + GantryAxes::GantryY => &mut self.y, + GantryAxes::GantryZ => &mut self.z, } } +} + +pub struct GantryPosition { + x: f64, + y: f64, + z: f64, +} - /* Immutable access */ - pub fn wheel_base(&self) -> &f64 { - &self.wheel_base +pub struct GantryModel { + current_position: GantryPosition, +} + +impl GantryModel { + pub fn new() -> GantryModel { + GantryModel { + current_position: GantryPosition { + x: 0.0, + y: 0.0, + z: 0.0, + } + } } - pub fn wheel_radius(&self) -> &f64 { - &self.wheel_radius + pub fn set_position(&mut self, pos: GantryPosition) { + self.current_position = pos; + } + + pub fn calc_control_signals( + &mut self, + target_position: GantryPosition, + max_speed: f64, + ) -> StepperCtrlCmdGroup { + // assuming 1 unit = 1 step for simplicity + let x_steps = (target_position.x - self.current_position.x) as i32; + let y_steps = (target_position.y - self.current_position.y) as i32; + let z_steps = (target_position.z - self.current_position.z) as i32; + + // Update current position + self.current_position = target_position; + + // For now, we'll set the same speed for all axes, but this could be adjusted based on the axis and specific requirements + StepperCtrlCmdGroup { + x: StepperCtrlCmd { + steps: x_steps, + speed: max_speed, + }, + y: StepperCtrlCmd { + steps: y_steps, + speed: max_speed, + }, + z: StepperCtrlCmd { + steps: z_steps, + speed: max_speed, + }, + } } } diff --git a/mercury-app/src/hw_ifc/src/gantry_sub.rs b/mercury-app/src/hw_ifc/src/gantry_sub.rs index 8f14a7b..04262f5 100644 --- a/mercury-app/src/hw_ifc/src/gantry_sub.rs +++ b/mercury-app/src/hw_ifc/src/gantry_sub.rs @@ -1,110 +1,59 @@ /* Subscriber for Carrying out Commands for Chassis Drive Motors */ - use rosrust; -use rosrust_msg::geometry_msgs::Twist; -use std::sync::RwLock; +pub mod gantry_model; +use self::gantry_model::{ + GantryAxes, GantryModel, GantryPosition, StepperCtrlCmd, StepperCtrlCmdGroup, +}; pub mod msg { - rosrust::rosmsg_include!(gantry/calibrate); + rosrust::rosmsg_include!(hw_srv/calibrate); } - pub struct GantryController { - model : GantryModel, - max_linear_vel: f64, /* meters per second */ - max_angular_vel: f64, /* radians per second */ - velocities: RwLock<(f64, f64)>, /* Left and right velocities */ + model: GantryModel, } impl GantryController { - pub fn new() -> Self - { - // Parameters - let wheel_base = rosrust::param("~wheel_base").unwrap().get().unwrap_or(0.2); - let wheel_radius = rosrust::param("~wheel_radius").unwrap().get().unwrap_or(0.095); - let max_velocity_meters_per_second = rosrust::param("~max_velocity_meters_per_second").unwrap().get().unwrap_or(10.0); - let max_angular_velocity_rad_per_second = rosrust::param("~max_angular_velocity_rad_per_second").unwrap().get().unwrap_or(6.0); - - GantryController { - model : GantryModel::new(wheel_base, wheel_radius), - max_linear_vel : max_velocity_meters_per_second, - max_angular_vel : max_angular_velocity_rad_per_second, - velocities: RwLock::new((0.0, 0.0)), + pub fn new() -> Self { + GantryController { + model: GantryModel::new(), } - } - - fn clamp_linear_speed(&self, speed: f64) -> f64 - { - speed.max(-self.max_linear_vel) - .min(0.0) - } - - fn clamp_angular_speed(&self, speed: f64) -> f64 - { - speed.max(-self.max_angular_vel) - .min(0.0) - } - - fn send_motor_commands(&self) - { - let velocities = self.velocities.read().unwrap(); - - // TODO Make hardware call - - rosrust::ros_info!("Left Vel/Command: {}, Right Vel/Command: {}", velocities.0, velocities.1); - } - - pub fn command_callback(&self, data: Twist) - { - let linear_velocity = self.clamp_linear_speed(data.linear.x); - let angular_velocity = self.clamp_angular_speed(data.angular.z); + } - let left_velocity = linear_velocity - (angular_velocity * self.model.wheel_base() / 2.0); - let right_velocity = linear_velocity + (angular_velocity * self.model.wheel_base() / 2.0); - - // Store the velocities safely - let mut velocities = self.velocities.write().unwrap(); - *velocities = (left_velocity, right_velocity); - self.send_motor_commands(); - } + pub fn command_callback(&self, data: rosrust_msg::hw_srv::calibrate) {} } -fn main() -{ - /* Initialize ROS node */ - rosrust::init("gantry_sub"); - - let gantry_ctrl = GantryController::new(); - - /* - * Create subscriber - */ - let _subscriber_info = rosrust::subscribe_with_ids( - "/gantry/pose/goal", - 2, - move |v: Twist, _caller_id: &str| { - gantry_ctrl.command_callback(v); - } - ) - .unwrap(); - - /** - * Create service - */ - let _service_raii = rosrust::service::("/services/gantry/calibrate", move |req| { - gantry_ctrl.command_callback(req); - - Ok(msg::gantry::calibrate { sum }) - }) - .unwrap(); - - let log_names = rosrust::param("~log_names").unwrap() - .get() - .unwrap_or(false); - if log_names { - while rosrust::is_ok() { - /* Spin forever, we only execute things on callbacks from here */ - rosrust::spin(); - } - } -} \ No newline at end of file +fn main() { + /* Initialize ROS node */ + rosrust::init("gantry_sub"); + + let gantry_ctrl = GantryController::new(); + + /* + * Create subscriber + */ + //let _subscriber_info = rosrust::subscribe_with_ids( + // "/gantry/pose/goal", + // 2, + // move |v: rosrust_msg::hw_srv::calibrate, _caller_id: &str| { + // gantry_ctrl.command_callback(v); + // }, + //) + //.unwrap(); + + /** + * Create service + */ + //let _service_raii = + // rosrust::service::("/services/gantry/calibrate", move |req| { + // gantry_ctrl.command_callback(req); +// + // Ok(rosrust_msg::hw_srv::calibrate { }) + // }) + // .unwrap(); + + while rosrust::is_ok() { + /* Spin forever, we only execute things on callbacks from here */ + rosrust::spin(); + } +} diff --git a/mercury-app/src/hw_srv/srv/calibrate.srv b/mercury-app/src/hw_srv/srv/calibrate.srv new file mode 100644 index 0000000..57fcf58 --- /dev/null +++ b/mercury-app/src/hw_srv/srv/calibrate.srv @@ -0,0 +1,2 @@ +bool status +--- \ No newline at end of file From bd436fa828b0473ddbbe0980c95a2371a7ed8a86 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Thu, 21 Mar 2024 13:31:15 -0400 Subject: [PATCH 2/9] Attempting to get stepper pulsing working in hdl --- mercury-hdl/mercury_bd.tcl | 610 ++++++++----------------- mercury-hdl/mercury_proj.tcl | 858 ++++++++++++----------------------- mercury-hdl/stepper_pulse.v | 68 +++ 3 files changed, 563 insertions(+), 973 deletions(-) create mode 100644 mercury-hdl/stepper_pulse.v diff --git a/mercury-hdl/mercury_bd.tcl b/mercury-hdl/mercury_bd.tcl index 642354b..ce72e07 100644 --- a/mercury-hdl/mercury_bd.tcl +++ b/mercury-hdl/mercury_bd.tcl @@ -37,6 +37,13 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { # To test this script, run the following commands from Vivado Tcl console: # source mercury_script.tcl + +# The design that will be created by this Tcl script contains the following +# module references: +# stepper_pulse, stepper_pulse, stepper_pulse + +# Please add the sources of those modules before sourcing this Tcl script. + # If there is no project opened, this script will create a # project, but make sure you do not have an existing project # <./myproj/project_1.xpr> in the current working folder. @@ -126,9 +133,9 @@ if { $bCheckIPs == 1 } { set list_check_ips "\ xilinx.com:ip:processing_system7:5.5\ xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:axi_timer:2.0\ xilinx.com:ip:axi_gpio:2.0\ xilinx.com:ip:xlslice:1.0\ -xilinx.com:ip:axi_timer:2.0\ " set list_ips_missing "" @@ -148,6 +155,33 @@ xilinx.com:ip:axi_timer:2.0\ } +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +stepper_pulse\ +stepper_pulse\ +stepper_pulse\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + if { $bCheckIPsPassed != 1 } { common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 @@ -158,13 +192,13 @@ if { $bCheckIPsPassed != 1 } { ################################################################## -# Hierarchical cell: drive -proc create_hier_cell_drive { parentCell nameHier } { +# Hierarchical cell: gantry +proc create_hier_cell_gantry { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_drive() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_gantry() - Empty argument(s)!"} return } @@ -201,77 +235,114 @@ proc create_hier_cell_drive { parentCell nameHier } { create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI3 - create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI4 - # Create pins create_bd_pin -dir I -type clk s_axi_aclk create_bd_pin -dir I -type rst s_axi_aresetn - create_bd_pin -dir O DAC_1_INA - create_bd_pin -dir O DAC_1_INB - create_bd_pin -dir O DAC_2_INA - create_bd_pin -dir O DAC_2_INB - create_bd_pin -dir O -from 0 -to 0 Drive_DIR_1 - create_bd_pin -dir O -from 0 -to 0 Drive_DIR_3 + create_bd_pin -dir I step_clk - # Create instance: axi_timer_0, and set properties - set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO2_WIDTH {1} \ + CONFIG.C_IS_DUAL {1} \ + ] $axi_gpio_0 - # Create instance: axi_timer_1, and set properties - set axi_timer_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_1 ] - # Create instance: axi_timer_2, and set properties - set axi_timer_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_2 ] + # Create instance: axi_gpio_1, and set properties + set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ] + set_property -dict [list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO2_WIDTH {1} \ + CONFIG.C_IS_DUAL {1} \ + ] $axi_gpio_1 - # Create instance: axi_timer_3, and set properties - set axi_timer_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_3 ] # Create instance: axi_gpio_2, and set properties set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] set_property -dict [list \ + CONFIG.C_ALL_INPUTS_2 {1} \ CONFIG.C_ALL_OUTPUTS {1} \ - CONFIG.C_ALL_OUTPUTS_2 {1} \ - CONFIG.C_DOUT_DEFAULT {0xFFFFFFFF} \ + CONFIG.C_GPIO2_WIDTH {1} \ CONFIG.C_IS_DUAL {1} \ ] $axi_gpio_2 - # Create instance: xlslice_0, and set properties - set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] - - # Create instance: xlslice_1, and set properties - set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] - + # Create instance: axi_gpio_3, and set properties + set axi_gpio_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_3 ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT {0x00000001} \ + CONFIG.C_GPIO_WIDTH {1} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_3 + + + # Create instance: stepper_pulse_0, and set properties + set block_name stepper_pulse + set block_cell_name stepper_pulse_0 + if { [catch {set stepper_pulse_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $stepper_pulse_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: stepper_pulse_1, and set properties + set block_name stepper_pulse + set block_cell_name stepper_pulse_1 + if { [catch {set stepper_pulse_1 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $stepper_pulse_1 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: stepper_pulse_2, and set properties + set block_name stepper_pulse + set block_cell_name stepper_pulse_2 + if { [catch {set stepper_pulse_2 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $stepper_pulse_2 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + # Create interface connections - connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axi_timer_1/S_AXI] [get_bd_intf_pins S_AXI] - connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_timer_2/S_AXI] [get_bd_intf_pins S_AXI1] - connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins axi_timer_3/S_AXI] [get_bd_intf_pins S_AXI2] - connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins S_AXI3] - connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins S_AXI4] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins S_AXI1] [get_bd_intf_pins axi_gpio_1/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins S_AXI2] [get_bd_intf_pins axi_gpio_2/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins S_AXI3] [get_bd_intf_pins axi_gpio_3/S_AXI] # Create port connections - connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins axi_gpio_2/gpio2_io_o] [get_bd_pins xlslice_1/Din] - connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_2/gpio_io_o] [get_bd_pins xlslice_0/Din] - connect_bd_net -net axi_timer_0_pwm0 [get_bd_pins axi_timer_0/pwm0] [get_bd_pins DAC_1_INA] - connect_bd_net -net axi_timer_1_pwm0 [get_bd_pins axi_timer_1/pwm0] [get_bd_pins DAC_1_INB] - connect_bd_net -net axi_timer_2_pwm0 [get_bd_pins axi_timer_2/pwm0] [get_bd_pins DAC_2_INA] - connect_bd_net -net axi_timer_3_pwm0 [get_bd_pins axi_timer_3/pwm0] [get_bd_pins DAC_2_INB] - connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_timer_1/s_axi_aclk] [get_bd_pins axi_timer_2/s_axi_aclk] [get_bd_pins axi_timer_3/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] - connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins axi_timer_1/s_axi_aresetn] [get_bd_pins axi_timer_3/s_axi_aresetn] [get_bd_pins axi_timer_2/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] - connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins Drive_DIR_1] - connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins Drive_DIR_3] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins stepper_pulse_0/pulse_count] + connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins stepper_pulse_1/pulse_count] + connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_2/gpio_io_o] [get_bd_pins stepper_pulse_2/pulse_count] + connect_bd_net -net axi_gpio_3_gpio_io_o [get_bd_pins axi_gpio_3/gpio_io_o] [get_bd_pins stepper_pulse_0/rst_n] [get_bd_pins stepper_pulse_1/rst_n] [get_bd_pins stepper_pulse_2/rst_n] + connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] + connect_bd_net -net step_clk_1 [get_bd_pins step_clk] [get_bd_pins stepper_pulse_0/clk] [get_bd_pins stepper_pulse_1/clk] [get_bd_pins stepper_pulse_2/clk] + connect_bd_net -net stepper_pulse_0_done [get_bd_pins stepper_pulse_0/done] [get_bd_pins axi_gpio_0/gpio2_io_i] + connect_bd_net -net stepper_pulse_1_done [get_bd_pins stepper_pulse_1/done] [get_bd_pins axi_gpio_1/gpio2_io_i] + connect_bd_net -net stepper_pulse_2_done [get_bd_pins stepper_pulse_2/done] [get_bd_pins axi_gpio_2/gpio2_io_i] # Restore current instance current_bd_instance $oldCurInst } -# Hierarchical cell: GPIO_Slicer -proc create_hier_cell_GPIO_Slicer { parentCell nameHier } { +# Hierarchical cell: drive +proc create_hier_cell_drive { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_GPIO_Slicer() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_drive() - Empty argument(s)!"} return } @@ -300,324 +371,73 @@ proc create_hier_cell_GPIO_Slicer { parentCell nameHier } { current_bd_instance $hier_obj # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI - # Create pins - create_bd_pin -dir I -from 31 -to 0 GPIO_buf - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_1 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_2 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_3 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_4 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_5 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_6 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_7 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_8 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_9 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_10 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_11 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_12 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_13 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_14 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_15 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_16 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_17 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_18 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_19 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_20 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_21 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_22 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_23 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_24 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_25 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_26 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_27 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_28 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_29 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_30 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_31 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_0 - - # Create instance: xlslice_0, and set properties - set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] - - # Create instance: xlslice_1, and set properties - set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] - set_property CONFIG.DIN_TO {1} $xlslice_1 - - - # Create instance: xlslice_2, and set properties - set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] - set_property -dict [list \ - CONFIG.DIN_FROM {2} \ - CONFIG.DIN_TO {2} \ - ] $xlslice_2 - - - # Create instance: xlslice_3, and set properties - set xlslice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 ] - set_property -dict [list \ - CONFIG.DIN_FROM {3} \ - CONFIG.DIN_TO {3} \ - ] $xlslice_3 - - - # Create instance: xlslice_4, and set properties - set xlslice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_4 ] - set_property -dict [list \ - CONFIG.DIN_FROM {4} \ - CONFIG.DIN_TO {4} \ - ] $xlslice_4 - - - # Create instance: xlslice_5, and set properties - set xlslice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_5 ] - set_property -dict [list \ - CONFIG.DIN_FROM {5} \ - CONFIG.DIN_TO {5} \ - ] $xlslice_5 - - - # Create instance: xlslice_6, and set properties - set xlslice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_6 ] - set_property -dict [list \ - CONFIG.DIN_FROM {6} \ - CONFIG.DIN_TO {6} \ - ] $xlslice_6 - - - # Create instance: xlslice_7, and set properties - set xlslice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_7 ] - set_property -dict [list \ - CONFIG.DIN_FROM {7} \ - CONFIG.DIN_TO {7} \ - ] $xlslice_7 - - - # Create instance: xlslice_8, and set properties - set xlslice_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_8 ] - set_property -dict [list \ - CONFIG.DIN_FROM {8} \ - CONFIG.DIN_TO {8} \ - ] $xlslice_8 - - - # Create instance: xlslice_9, and set properties - set xlslice_9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_9 ] - set_property -dict [list \ - CONFIG.DIN_FROM {9} \ - CONFIG.DIN_TO {9} \ - ] $xlslice_9 - - - # Create instance: xlslice_10, and set properties - set xlslice_10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_10 ] - set_property -dict [list \ - CONFIG.DIN_FROM {10} \ - CONFIG.DIN_TO {10} \ - ] $xlslice_10 - - - # Create instance: xlslice_11, and set properties - set xlslice_11 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_11 ] - set_property -dict [list \ - CONFIG.DIN_FROM {11} \ - CONFIG.DIN_TO {11} \ - ] $xlslice_11 - - - # Create instance: xlslice_12, and set properties - set xlslice_12 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_12 ] - set_property -dict [list \ - CONFIG.DIN_FROM {12} \ - CONFIG.DIN_TO {12} \ - ] $xlslice_12 - - - # Create instance: xlslice_13, and set properties - set xlslice_13 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_13 ] - set_property -dict [list \ - CONFIG.DIN_FROM {13} \ - CONFIG.DIN_TO {13} \ - ] $xlslice_13 - - - # Create instance: xlslice_14, and set properties - set xlslice_14 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_14 ] - set_property -dict [list \ - CONFIG.DIN_FROM {14} \ - CONFIG.DIN_TO {14} \ - ] $xlslice_14 - - - # Create instance: xlslice_15, and set properties - set xlslice_15 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_15 ] - set_property -dict [list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DIN_TO {15} \ - ] $xlslice_15 - - - # Create instance: xlslice_16, and set properties - set xlslice_16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_16 ] - set_property -dict [list \ - CONFIG.DIN_FROM {16} \ - CONFIG.DIN_TO {16} \ - ] $xlslice_16 - - - # Create instance: xlslice_17, and set properties - set xlslice_17 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_17 ] - set_property -dict [list \ - CONFIG.DIN_FROM {17} \ - CONFIG.DIN_TO {17} \ - ] $xlslice_17 - - - # Create instance: xlslice_18, and set properties - set xlslice_18 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_18 ] - set_property -dict [list \ - CONFIG.DIN_FROM {18} \ - CONFIG.DIN_TO {18} \ - ] $xlslice_18 - - - # Create instance: xlslice_19, and set properties - set xlslice_19 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_19 ] - set_property -dict [list \ - CONFIG.DIN_FROM {19} \ - CONFIG.DIN_TO {19} \ - ] $xlslice_19 - - - # Create instance: xlslice_20, and set properties - set xlslice_20 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_20 ] - set_property -dict [list \ - CONFIG.DIN_FROM {20} \ - CONFIG.DIN_TO {20} \ - ] $xlslice_20 - - - # Create instance: xlslice_21, and set properties - set xlslice_21 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_21 ] - set_property -dict [list \ - CONFIG.DIN_FROM {21} \ - CONFIG.DIN_TO {21} \ - ] $xlslice_21 - - - # Create instance: xlslice_22, and set properties - set xlslice_22 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_22 ] - set_property -dict [list \ - CONFIG.DIN_FROM {22} \ - CONFIG.DIN_TO {22} \ - ] $xlslice_22 - - - # Create instance: xlslice_23, and set properties - set xlslice_23 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_23 ] - set_property -dict [list \ - CONFIG.DIN_FROM {23} \ - CONFIG.DIN_TO {23} \ - ] $xlslice_23 - - - # Create instance: xlslice_24, and set properties - set xlslice_24 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_24 ] - set_property -dict [list \ - CONFIG.DIN_FROM {24} \ - CONFIG.DIN_TO {24} \ - ] $xlslice_24 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI1 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI2 - # Create instance: xlslice_25, and set properties - set xlslice_25 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_25 ] - set_property -dict [list \ - CONFIG.DIN_FROM {25} \ - CONFIG.DIN_TO {25} \ - ] $xlslice_25 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI3 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI4 - # Create instance: xlslice_26, and set properties - set xlslice_26 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_26 ] - set_property -dict [list \ - CONFIG.DIN_FROM {26} \ - CONFIG.DIN_TO {26} \ - ] $xlslice_26 + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O DAC_1_INA + create_bd_pin -dir O DAC_1_INB + create_bd_pin -dir O DAC_2_INA + create_bd_pin -dir O DAC_2_INB + create_bd_pin -dir O -from 0 -to 0 Drive_DIR_1 + create_bd_pin -dir O -from 0 -to 0 Drive_DIR_3 - # Create instance: xlslice_27, and set properties - set xlslice_27 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_27 ] - set_property -dict [list \ - CONFIG.DIN_FROM {27} \ - CONFIG.DIN_TO {27} \ - ] $xlslice_27 + # Create instance: axi_timer_0, and set properties + set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] + # Create instance: axi_timer_1, and set properties + set axi_timer_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_1 ] - # Create instance: xlslice_28, and set properties - set xlslice_28 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_28 ] - set_property -dict [list \ - CONFIG.DIN_FROM {28} \ - CONFIG.DIN_TO {28} \ - ] $xlslice_28 + # Create instance: axi_timer_2, and set properties + set axi_timer_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_2 ] + # Create instance: axi_timer_3, and set properties + set axi_timer_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_3 ] - # Create instance: xlslice_29, and set properties - set xlslice_29 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_29 ] + # Create instance: axi_gpio_2, and set properties + set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] set_property -dict [list \ - CONFIG.DIN_FROM {29} \ - CONFIG.DIN_TO {29} \ - ] $xlslice_29 + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_ALL_OUTPUTS_2 {1} \ + CONFIG.C_DOUT_DEFAULT {0xFFFFFFFF} \ + CONFIG.C_IS_DUAL {1} \ + ] $axi_gpio_2 - # Create instance: xlslice_30, and set properties - set xlslice_30 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_30 ] - set_property -dict [list \ - CONFIG.DIN_FROM {30} \ - CONFIG.DIN_TO {30} \ - ] $xlslice_30 - + # Create instance: xlslice_0, and set properties + set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] - # Create instance: xlslice_31, and set properties - set xlslice_31 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_31 ] - set_property -dict [list \ - CONFIG.DIN_FROM {31} \ - CONFIG.DIN_TO {31} \ - ] $xlslice_31 + # Create instance: xlslice_1, and set properties + set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axi_timer_1/S_AXI] [get_bd_intf_pins S_AXI] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_timer_2/S_AXI] [get_bd_intf_pins S_AXI1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins axi_timer_3/S_AXI] [get_bd_intf_pins S_AXI2] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins S_AXI3] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins S_AXI4] # Create port connections - connect_bd_net -net GPIO_buf_1 [get_bd_pins GPIO_buf] [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_3/Din] [get_bd_pins xlslice_4/Din] [get_bd_pins xlslice_5/Din] [get_bd_pins xlslice_6/Din] [get_bd_pins xlslice_2/Din] [get_bd_pins xlslice_7/Din] [get_bd_pins xlslice_8/Din] [get_bd_pins xlslice_9/Din] [get_bd_pins xlslice_10/Din] [get_bd_pins xlslice_11/Din] [get_bd_pins xlslice_12/Din] [get_bd_pins xlslice_13/Din] [get_bd_pins xlslice_14/Din] [get_bd_pins xlslice_15/Din] [get_bd_pins xlslice_16/Din] [get_bd_pins xlslice_17/Din] [get_bd_pins xlslice_18/Din] [get_bd_pins xlslice_19/Din] [get_bd_pins xlslice_20/Din] [get_bd_pins xlslice_21/Din] [get_bd_pins xlslice_22/Din] [get_bd_pins xlslice_23/Din] [get_bd_pins xlslice_24/Din] [get_bd_pins xlslice_31/Din] [get_bd_pins xlslice_30/Din] [get_bd_pins xlslice_29/Din] [get_bd_pins xlslice_28/Din] [get_bd_pins xlslice_27/Din] [get_bd_pins xlslice_26/Din] [get_bd_pins xlslice_25/Din] - connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins GPIO_buf_0] - connect_bd_net -net xlslice_10_Dout [get_bd_pins xlslice_10/Dout] [get_bd_pins GPIO_buf_10] - connect_bd_net -net xlslice_11_Dout [get_bd_pins xlslice_11/Dout] [get_bd_pins GPIO_buf_11] - connect_bd_net -net xlslice_12_Dout [get_bd_pins xlslice_12/Dout] [get_bd_pins GPIO_buf_12] - connect_bd_net -net xlslice_13_Dout [get_bd_pins xlslice_13/Dout] [get_bd_pins GPIO_buf_13] - connect_bd_net -net xlslice_14_Dout [get_bd_pins xlslice_14/Dout] [get_bd_pins GPIO_buf_14] - connect_bd_net -net xlslice_15_Dout [get_bd_pins xlslice_15/Dout] [get_bd_pins GPIO_buf_15] - connect_bd_net -net xlslice_16_Dout [get_bd_pins xlslice_16/Dout] [get_bd_pins GPIO_buf_16] - connect_bd_net -net xlslice_17_Dout [get_bd_pins xlslice_17/Dout] [get_bd_pins GPIO_buf_17] - connect_bd_net -net xlslice_18_Dout [get_bd_pins xlslice_18/Dout] [get_bd_pins GPIO_buf_18] - connect_bd_net -net xlslice_19_Dout [get_bd_pins xlslice_19/Dout] [get_bd_pins GPIO_buf_19] - connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins GPIO_buf_1] - connect_bd_net -net xlslice_20_Dout [get_bd_pins xlslice_20/Dout] [get_bd_pins GPIO_buf_20] - connect_bd_net -net xlslice_21_Dout [get_bd_pins xlslice_21/Dout] [get_bd_pins GPIO_buf_21] - connect_bd_net -net xlslice_22_Dout [get_bd_pins xlslice_22/Dout] [get_bd_pins GPIO_buf_22] - connect_bd_net -net xlslice_23_Dout [get_bd_pins xlslice_23/Dout] [get_bd_pins GPIO_buf_23] - connect_bd_net -net xlslice_24_Dout [get_bd_pins xlslice_24/Dout] [get_bd_pins GPIO_buf_24] - connect_bd_net -net xlslice_25_Dout [get_bd_pins xlslice_25/Dout] [get_bd_pins GPIO_buf_25] - connect_bd_net -net xlslice_26_Dout [get_bd_pins xlslice_26/Dout] [get_bd_pins GPIO_buf_26] - connect_bd_net -net xlslice_27_Dout [get_bd_pins xlslice_27/Dout] [get_bd_pins GPIO_buf_27] - connect_bd_net -net xlslice_28_Dout [get_bd_pins xlslice_28/Dout] [get_bd_pins GPIO_buf_28] - connect_bd_net -net xlslice_29_Dout [get_bd_pins xlslice_29/Dout] [get_bd_pins GPIO_buf_29] - connect_bd_net -net xlslice_2_Dout [get_bd_pins xlslice_2/Dout] [get_bd_pins GPIO_buf_2] - connect_bd_net -net xlslice_30_Dout [get_bd_pins xlslice_30/Dout] [get_bd_pins GPIO_buf_30] - connect_bd_net -net xlslice_31_Dout [get_bd_pins xlslice_31/Dout] [get_bd_pins GPIO_buf_31] - connect_bd_net -net xlslice_3_Dout [get_bd_pins xlslice_3/Dout] [get_bd_pins GPIO_buf_3] - connect_bd_net -net xlslice_4_Dout [get_bd_pins xlslice_4/Dout] [get_bd_pins GPIO_buf_4] - connect_bd_net -net xlslice_5_Dout [get_bd_pins xlslice_5/Dout] [get_bd_pins GPIO_buf_5] - connect_bd_net -net xlslice_6_Dout [get_bd_pins xlslice_6/Dout] [get_bd_pins GPIO_buf_6] - connect_bd_net -net xlslice_7_Dout [get_bd_pins xlslice_7/Dout] [get_bd_pins GPIO_buf_7] - connect_bd_net -net xlslice_8_Dout [get_bd_pins xlslice_8/Dout] [get_bd_pins GPIO_buf_8] - connect_bd_net -net xlslice_9_Dout [get_bd_pins xlslice_9/Dout] [get_bd_pins GPIO_buf_9] + connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins axi_gpio_2/gpio2_io_o] [get_bd_pins xlslice_1/Din] + connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_2/gpio_io_o] [get_bd_pins xlslice_0/Din] + connect_bd_net -net axi_timer_0_pwm0 [get_bd_pins axi_timer_0/pwm0] [get_bd_pins DAC_1_INA] + connect_bd_net -net axi_timer_1_pwm0 [get_bd_pins axi_timer_1/pwm0] [get_bd_pins DAC_1_INB] + connect_bd_net -net axi_timer_2_pwm0 [get_bd_pins axi_timer_2/pwm0] [get_bd_pins DAC_2_INA] + connect_bd_net -net axi_timer_3_pwm0 [get_bd_pins axi_timer_3/pwm0] [get_bd_pins DAC_2_INB] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_timer_1/s_axi_aclk] [get_bd_pins axi_timer_2/s_axi_aclk] [get_bd_pins axi_timer_3/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins axi_timer_1/s_axi_aresetn] [get_bd_pins axi_timer_3/s_axi_aresetn] [get_bd_pins axi_timer_2/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] + connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins Drive_DIR_1] + connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins Drive_DIR_3] # Restore current instance current_bd_instance $oldCurInst @@ -667,24 +487,14 @@ proc create_root_design { parentCell } { set DAC_1_INB [ create_bd_port -dir O -type data DAC_1_INB ] set DAC_2_INA [ create_bd_port -dir O -type data DAC_2_INA ] set DAC_2_INB [ create_bd_port -dir O -type data DAC_2_INB ] - set M0_1 [ create_bd_port -dir O -from 0 -to 0 M0_1 ] - set M1_1 [ create_bd_port -dir O -from 0 -to 0 M1_1 ] - set CONFIG_1 [ create_bd_port -dir O -from 0 -to 0 CONFIG_1 ] - set NENBL_1 [ create_bd_port -dir O -from 0 -to 0 NENBL_1 ] - set STEP_1 [ create_bd_port -dir O -from 0 -to 0 STEP_1 ] - set DIR_1 [ create_bd_port -dir O -from 0 -to 0 DIR_1 ] - set Breakout1_1 [ create_bd_port -dir O -from 0 -to 0 Breakout1_1 ] - set Breakout1_2 [ create_bd_port -dir O -from 0 -to 0 Breakout1_2 ] - set Breakout1_3 [ create_bd_port -dir O -from 0 -to 0 Breakout1_3 ] - set Sensor_IO_8 [ create_bd_port -dir O -from 0 -to 0 Sensor_IO_8 ] - set Sensor_IO_1 [ create_bd_port -dir O -from 0 -to 0 Sensor_IO_1 ] - set Sensor_IO_2 [ create_bd_port -dir O -from 0 -to 0 Sensor_IO_2 ] - set Sensor_IO_3 [ create_bd_port -dir O -from 0 -to 0 Sensor_IO_3 ] - set Sensor_IO_5 [ create_bd_port -dir O -from 0 -to 0 Sensor_IO_5 ] set Drive_DIR_1 [ create_bd_port -dir O -from 0 -to 0 -type data Drive_DIR_1 ] set Drive_DIR_2 [ create_bd_port -dir O -from 0 -to 0 -type data Drive_DIR_2 ] set Drive_DIR_3 [ create_bd_port -dir O -from 0 -to 0 -type data Drive_DIR_3 ] set Drive_DIR_4 [ create_bd_port -dir O -from 0 -to 0 -type data Drive_DIR_4 ] + set reset_rtl [ create_bd_port -dir I -type rst reset_rtl ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $reset_rtl # Create instance: processing_system7_0, and set properties set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] @@ -695,7 +505,7 @@ proc create_root_design { parentCell } { CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ - CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {1.000000} \ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ @@ -715,7 +525,7 @@ proc create_root_design { parentCell } { CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667} \ CONFIG.PCW_CLK0_FREQ {100000000} \ - CONFIG.PCW_CLK1_FREQ {10000000} \ + CONFIG.PCW_CLK1_FREQ {1000000} \ CONFIG.PCW_CLK2_FREQ {10000000} \ CONFIG.PCW_CLK3_FREQ {10000000} \ CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ @@ -736,7 +546,7 @@ proc create_root_design { parentCell } { CONFIG.PCW_ENET_RESET_ENABLE {1} \ CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ CONFIG.PCW_EN_CLK0_PORT {1} \ - CONFIG.PCW_EN_CLK1_PORT {0} \ + CONFIG.PCW_EN_CLK1_PORT {1} \ CONFIG.PCW_EN_CLK2_PORT {0} \ CONFIG.PCW_EN_CLK3_PORT {0} \ CONFIG.PCW_EN_DDR {1} \ @@ -757,11 +567,13 @@ proc create_root_design { parentCell } { CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ - CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {1} \ CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {33.333333} \ CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ @@ -1029,38 +841,22 @@ proc create_root_design { parentCell } { ] $axi_interconnect_0 - # Create instance: axi_gpio_0, and set properties - set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] - set_property -dict [list \ - CONFIG.C_ALL_OUTPUTS {1} \ - CONFIG.C_DOUT_DEFAULT {0xFFFFFFFF} \ - CONFIG.C_IS_DUAL {0} \ - ] $axi_gpio_0 - - - # Create instance: GPIO_Slicer - create_hier_cell_GPIO_Slicer [current_bd_instance .] GPIO_Slicer - - # Create instance: axi_gpio_1, and set properties - set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ] - set_property -dict [list \ - CONFIG.C_ALL_OUTPUTS {1} \ - CONFIG.C_DOUT_DEFAULT {0xFFFFFFFF} \ - CONFIG.C_GPIO_WIDTH {1} \ - ] $axi_gpio_1 - - # Create instance: drive create_hier_cell_drive [current_bd_instance .] drive + # Create instance: gantry + create_hier_cell_gantry [current_bd_instance .] gantry + # Create interface connections - connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins drive/S_AXI4] - connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins drive/S_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins drive/S_AXI1] - connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins drive/S_AXI2] - connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins axi_interconnect_0/M04_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins axi_interconnect_0/M06_AXI] [get_bd_intf_pins drive/S_AXI3] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins drive/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins drive/S_AXI1] + connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins drive/S_AXI2] + connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins drive/S_AXI3] + connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins axi_interconnect_0/M04_AXI] [get_bd_intf_pins drive/S_AXI4] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins axi_interconnect_0/M05_AXI] [get_bd_intf_pins gantry/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins axi_interconnect_0/M06_AXI] [get_bd_intf_pins gantry/S_AXI1] + connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins axi_interconnect_0/M07_AXI] [get_bd_intf_pins gantry/S_AXI2] + connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_interconnect_0/M08_AXI] [get_bd_intf_pins gantry/S_AXI3] connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins axi_interconnect_0/S00_AXI] @@ -1068,44 +864,22 @@ proc create_root_design { parentCell } { # Create port connections connect_bd_net -net Drive_Dir1 [get_bd_pins drive/DAC_2_INB] [get_bd_ports DAC_2_INB] - connect_bd_net -net GPIO_Slicer_GPIO_buf_5 [get_bd_pins GPIO_Slicer/GPIO_buf_5] [get_bd_ports M0_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_6 [get_bd_pins GPIO_Slicer/GPIO_buf_6] [get_bd_ports M1_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_7 [get_bd_pins GPIO_Slicer/GPIO_buf_7] [get_bd_ports CONFIG_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_8 [get_bd_pins GPIO_Slicer/GPIO_buf_8] [get_bd_ports NENBL_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_9 [get_bd_pins GPIO_Slicer/GPIO_buf_9] [get_bd_ports DIR_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_10 [get_bd_pins GPIO_Slicer/GPIO_buf_10] [get_bd_ports STEP_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_11 [get_bd_pins GPIO_Slicer/GPIO_buf_11] [get_bd_ports Breakout1_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_12 [get_bd_pins GPIO_Slicer/GPIO_buf_12] [get_bd_ports Breakout1_2] - connect_bd_net -net GPIO_Slicer_GPIO_buf_13 [get_bd_pins GPIO_Slicer/GPIO_buf_13] [get_bd_ports Breakout1_3] - connect_bd_net -net GPIO_Slicer_GPIO_buf_14 [get_bd_pins GPIO_Slicer/GPIO_buf_14] [get_bd_ports Sensor_IO_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_15 [get_bd_pins GPIO_Slicer/GPIO_buf_15] [get_bd_ports Sensor_IO_3] - connect_bd_net -net GPIO_Slicer_GPIO_buf_16 [get_bd_pins GPIO_Slicer/GPIO_buf_16] [get_bd_ports Sensor_IO_5] - connect_bd_net -net GPIO_Slicer_GPIO_buf_17 [get_bd_pins GPIO_Slicer/GPIO_buf_17] [get_bd_ports Sensor_IO_2] - connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins GPIO_Slicer/GPIO_buf] - connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_ports Sensor_IO_8] connect_bd_net -net drive_DAC_1_INA [get_bd_pins drive/DAC_1_INA] [get_bd_ports DAC_1_INA] connect_bd_net -net drive_DAC_1_INB [get_bd_pins drive/DAC_1_INB] [get_bd_ports DAC_1_INB] connect_bd_net -net drive_DAC_2_INA [get_bd_pins drive/DAC_2_INA] [get_bd_ports DAC_2_INA] connect_bd_net -net drive_Drive_DIR_1 [get_bd_pins drive/Drive_DIR_1] [get_bd_ports Drive_DIR_1] [get_bd_ports Drive_DIR_2] connect_bd_net -net drive_Drive_DIR_3 [get_bd_pins drive/Drive_DIR_3] [get_bd_ports Drive_DIR_3] [get_bd_ports Drive_DIR_4] - connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins drive/s_axi_aclk] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins drive/s_axi_aclk] [get_bd_pins gantry/s_axi_aclk] connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in] - connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins drive/s_axi_aresetn] + connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins drive/s_axi_aresetn] [get_bd_pins gantry/s_axi_aresetn] + connect_bd_net -net step_clk_1 [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins gantry/step_clk] # Create address segments - assign_bd_address -dict [list offset 0x7FFF8000 range 0x00008000 offset 0x80000000 range 0x00008000] -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force - assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_1/S_AXI/Reg] -force - assign_bd_address -offset 0x41210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_gpio_2/S_AXI/Reg] -force - assign_bd_address -offset 0x42800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_0/S_AXI/Reg] -force - assign_bd_address -offset 0x42810000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_1/S_AXI/Reg] -force - assign_bd_address -offset 0x42820000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_2/S_AXI/Reg] -force - assign_bd_address -offset 0x42830000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_3/S_AXI/Reg] -force # Restore current instance current_bd_instance $oldCurInst - validate_bd_design save_bd_design } # End of create_root_design() @@ -1118,3 +892,5 @@ proc create_root_design { parentCell } { create_root_design "" +common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." + diff --git a/mercury-hdl/mercury_proj.tcl b/mercury-hdl/mercury_proj.tcl index 0a0e9e9..dc0c5cb 100644 --- a/mercury-hdl/mercury_proj.tcl +++ b/mercury-hdl/mercury_proj.tcl @@ -3,7 +3,7 @@ # # mercury_proj.tcl: Tcl script for re-creating project 'mercury' # -# Generated by Vivado on Wed Mar 20 15:24:05 EDT 2024 +# Generated by Vivado on Thu Mar 21 13:29:40 EDT 2024 # IP Build 3864474 on Sun May 7 20:36:21 MDT 2023 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -23,7 +23,7 @@ # 2. The following source(s) files that were local or imported into the original project. # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) # -# "/media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/mercury/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp" +# "/media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/mercury/mercury.srcs/sources_1/new/stepper_pulse.v" # # 3. The following remote source files that were added to the original project:- # @@ -35,7 +35,7 @@ proc checkRequiredFiles { origin_dir} { set status true set files [list \ - "[file normalize "$origin_dir/mercury/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp"]"\ + "[file normalize "$origin_dir/mercury/mercury.srcs/sources_1/new/stepper_pulse.v"]"\ ] foreach ifile $files { if { ![file isfile $ifile] } { @@ -201,7 +201,7 @@ set_property -name "simulator.xcelium_gcc_install_dir" -value "" -objects $obj set_property -name "simulator.xcelium_install_dir" -value "" -objects $obj set_property -name "simulator_language" -value "Mixed" -objects $obj set_property -name "sim_compile_state" -value "1" -objects $obj -set_property -name "source_mgmt_mode" -value "DisplayOnly" -objects $obj +set_property -name "source_mgmt_mode" -value "All" -objects $obj set_property -name "target_language" -value "Verilog" -objects $obj set_property -name "target_simulator" -value "XSim" -objects $obj set_property -name "tool_flow" -value "Vivado" -objects $obj @@ -218,11 +218,28 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { # Set 'sources_1' fileset object set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/mercury/mercury.srcs/sources_1/new/stepper_pulse.v" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + # Set 'sources_1' fileset file properties for remote files # None # Set 'sources_1' fileset file properties for local files -# None +set file "new/stepper_pulse.v" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "Verilog" -objects $file_obj +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj +set_property -name "used_in_implementation" -value "1" -objects $file_obj +set_property -name "used_in_simulation" -value "1" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + # Set 'sources_1' fileset properties set obj [get_filesets sources_1] @@ -307,7 +324,8 @@ set_property -name "simmodel_value_check" -value "1" -objects $obj set_property -name "simulator_launch_mode" -value "off" -objects $obj set_property -name "source_set" -value "sources_1" -objects $obj set_property -name "systemc_include_dirs" -value "" -objects $obj -set_property -name "top" -value "" -objects $obj +set_property -name "top" -value "mercury_wrapper" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj set_property -name "transport_int_delay" -value "0" -objects $obj set_property -name "transport_path_delay" -value "0" -objects $obj set_property -name "unifast" -value "0" -objects $obj @@ -353,28 +371,7 @@ set_property -name "xsim.simulate.xsim.more_options" -value "" -objects $obj # Set 'utils_1' fileset object set obj [get_filesets utils_1] -# Import local files from the original project -set files [list \ - [file normalize "${origin_dir}/mercury/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp" ]\ -] -set imported_files [import_files -fileset utils_1 $files] - -# Set 'utils_1' fileset file properties for remote files -# None - -# Set 'utils_1' fileset file properties for local files -set file "synth_1/mercury_wrapper.dcp" -set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]] -set_property -name "is_enabled" -value "1" -objects $file_obj -set_property -name "is_global_include" -value "0" -objects $file_obj -set_property -name "library" -value "xil_defaultlib" -objects $file_obj -set_property -name "netlist_only" -value "0" -objects $file_obj -set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj -set_property -name "scoped_to_cells" -value "" -objects $file_obj -set_property -name "used_in" -value "synthesis implementation" -objects $file_obj -set_property -name "used_in_implementation" -value "1" -objects $file_obj -set_property -name "used_in_synthesis" -value "1" -objects $file_obj - +# Empty (no sources present) # Set 'utils_1' fileset properties set obj [get_filesets utils_1] @@ -382,10 +379,24 @@ set_property -name "name" -value "utils_1" -objects $obj # Adding sources referenced in BDs, if not already added +if { [get_files stepper_pulse.v] == "" } { + import_files -quiet -fileset sources_1 /media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/mercury/mercury.srcs/sources_1/new/stepper_pulse.v +} +if { [get_files stepper_pulse.v] == "" } { + import_files -quiet -fileset sources_1 /media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/mercury/mercury.srcs/sources_1/new/stepper_pulse.v +} +if { [get_files stepper_pulse.v] == "" } { + import_files -quiet -fileset sources_1 /media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/mercury/mercury.srcs/sources_1/new/stepper_pulse.v +} # Proc to create BD mercury proc cr_bd_mercury { parentCell } { +# The design that will be created by this Tcl proc contains the following +# module references: +# stepper_pulse, stepper_pulse, stepper_pulse + + # CHANGE DESIGN NAME HERE set design_name mercury @@ -403,9 +414,9 @@ proc cr_bd_mercury { parentCell } { set list_check_ips "\ xilinx.com:ip:processing_system7:5.5\ xilinx.com:ip:proc_sys_reset:5.0\ + xilinx.com:ip:axi_timer:2.0\ xilinx.com:ip:axi_gpio:2.0\ xilinx.com:ip:xlslice:1.0\ - xilinx.com:ip:axi_timer:2.0\ " set list_ips_missing "" @@ -425,19 +436,46 @@ proc cr_bd_mercury { parentCell } { } + ################################################################## + # CHECK Modules + ################################################################## + set bCheckModules 1 + if { $bCheckModules == 1 } { + set list_check_mods "\ + stepper_pulse\ + stepper_pulse\ + stepper_pulse\ + " + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + if { $bCheckIPsPassed != 1 } { common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } -# Hierarchical cell: drive -proc create_hier_cell_drive { parentCell nameHier } { +# Hierarchical cell: gantry +proc create_hier_cell_gantry { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_drive() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_gantry() - Empty argument(s)!"} return } @@ -474,111 +512,141 @@ proc create_hier_cell_drive { parentCell nameHier } { create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI3 - create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI4 - # Create pins create_bd_pin -dir I -type clk s_axi_aclk create_bd_pin -dir I -type rst s_axi_aresetn - create_bd_pin -dir O DAC_1_INA - create_bd_pin -dir O DAC_1_INB - create_bd_pin -dir O DAC_2_INA - create_bd_pin -dir O DAC_2_INB - create_bd_pin -dir O -from 0 -to 0 Drive_DIR_1 - create_bd_pin -dir O -from 0 -to 0 Drive_DIR_3 + create_bd_pin -dir I step_clk - # Create instance: axi_timer_0, and set properties - set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO2_WIDTH {1} \ + CONFIG.C_IS_DUAL {1} \ + ] $axi_gpio_0 - # Create instance: axi_timer_1, and set properties - set axi_timer_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_1 ] - # Create instance: axi_timer_2, and set properties - set axi_timer_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_2 ] + # Create instance: axi_gpio_1, and set properties + set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ] + set_property -dict [list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO2_WIDTH {1} \ + CONFIG.C_IS_DUAL {1} \ + ] $axi_gpio_1 - # Create instance: axi_timer_3, and set properties - set axi_timer_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_3 ] # Create instance: axi_gpio_2, and set properties set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] set_property -dict [list \ + CONFIG.C_ALL_INPUTS_2 {1} \ CONFIG.C_ALL_OUTPUTS {1} \ - CONFIG.C_ALL_OUTPUTS_2 {1} \ - CONFIG.C_DOUT_DEFAULT {0xFFFFFFFF} \ + CONFIG.C_GPIO2_WIDTH {1} \ CONFIG.C_IS_DUAL {1} \ ] $axi_gpio_2 - # Create instance: xlslice_0, and set properties - set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] - - # Create instance: xlslice_1, and set properties - set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] - + # Create instance: axi_gpio_3, and set properties + set axi_gpio_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_3 ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_DOUT_DEFAULT {0x00000001} \ + CONFIG.C_GPIO_WIDTH {1} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_3 + + + # Create instance: stepper_pulse_0, and set properties + set block_name stepper_pulse + set block_cell_name stepper_pulse_0 + if { [catch {set stepper_pulse_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $stepper_pulse_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: stepper_pulse_1, and set properties + set block_name stepper_pulse + set block_cell_name stepper_pulse_1 + if { [catch {set stepper_pulse_1 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $stepper_pulse_1 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: stepper_pulse_2, and set properties + set block_name stepper_pulse + set block_cell_name stepper_pulse_2 + if { [catch {set stepper_pulse_2 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $stepper_pulse_2 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + # Create interface connections - connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axi_timer_1/S_AXI] [get_bd_intf_pins S_AXI] - connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_timer_2/S_AXI] [get_bd_intf_pins S_AXI1] - connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins axi_timer_3/S_AXI] [get_bd_intf_pins S_AXI2] - connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins S_AXI3] - connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins S_AXI4] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins S_AXI1] [get_bd_intf_pins axi_gpio_1/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins S_AXI2] [get_bd_intf_pins axi_gpio_2/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins S_AXI3] [get_bd_intf_pins axi_gpio_3/S_AXI] # Create port connections - connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins axi_gpio_2/gpio2_io_o] [get_bd_pins xlslice_1/Din] - connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_2/gpio_io_o] [get_bd_pins xlslice_0/Din] - connect_bd_net -net axi_timer_0_pwm0 [get_bd_pins axi_timer_0/pwm0] [get_bd_pins DAC_1_INA] - connect_bd_net -net axi_timer_1_pwm0 [get_bd_pins axi_timer_1/pwm0] [get_bd_pins DAC_1_INB] - connect_bd_net -net axi_timer_2_pwm0 [get_bd_pins axi_timer_2/pwm0] [get_bd_pins DAC_2_INA] - connect_bd_net -net axi_timer_3_pwm0 [get_bd_pins axi_timer_3/pwm0] [get_bd_pins DAC_2_INB] - connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_timer_1/s_axi_aclk] [get_bd_pins axi_timer_2/s_axi_aclk] [get_bd_pins axi_timer_3/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] - connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins axi_timer_1/s_axi_aresetn] [get_bd_pins axi_timer_3/s_axi_aresetn] [get_bd_pins axi_timer_2/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] - connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins Drive_DIR_1] - connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins Drive_DIR_3] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins stepper_pulse_0/pulse_count] + connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins stepper_pulse_1/pulse_count] + connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_2/gpio_io_o] [get_bd_pins stepper_pulse_2/pulse_count] + connect_bd_net -net axi_gpio_3_gpio_io_o [get_bd_pins axi_gpio_3/gpio_io_o] [get_bd_pins stepper_pulse_0/rst_n] [get_bd_pins stepper_pulse_1/rst_n] [get_bd_pins stepper_pulse_2/rst_n] + connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] + connect_bd_net -net step_clk_1 [get_bd_pins step_clk] [get_bd_pins stepper_pulse_0/clk] [get_bd_pins stepper_pulse_1/clk] [get_bd_pins stepper_pulse_2/clk] + connect_bd_net -net stepper_pulse_0_done [get_bd_pins stepper_pulse_0/done] [get_bd_pins axi_gpio_0/gpio2_io_i] + connect_bd_net -net stepper_pulse_1_done [get_bd_pins stepper_pulse_1/done] [get_bd_pins axi_gpio_1/gpio2_io_i] + connect_bd_net -net stepper_pulse_2_done [get_bd_pins stepper_pulse_2/done] [get_bd_pins axi_gpio_2/gpio2_io_i] # Perform GUI Layout - regenerate_bd_layout -hierarchy [get_bd_cells /drive] -layout_string { + regenerate_bd_layout -hierarchy [get_bd_cells /gantry] -layout_string { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"1.29744", - "Default View_TopLeft":"-146,-22", + "Default View_ScaleFactor":"0.808605", + "Default View_TopLeft":"-481,1", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS # -string -flagsOSRD -preplace port S_AXI -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD -preplace port S_AXI1 -pg 1 -lvl 0 -x 0 -y 460 -defaultsOSRD -preplace port S_AXI2 -pg 1 -lvl 0 -x 0 -y 660 -defaultsOSRD -preplace port S_AXI3 -pg 1 -lvl 0 -x 0 -y 850 -defaultsOSRD -preplace port S_AXI4 -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD -preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y 870 -defaultsOSRD -preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y 890 -defaultsOSRD -preplace port port-id_DAC_1_INA -pg 1 -lvl 3 -x 620 -y 320 -defaultsOSRD -preplace port port-id_DAC_1_INB -pg 1 -lvl 3 -x 620 -y 120 -defaultsOSRD -preplace port port-id_DAC_2_INA -pg 1 -lvl 3 -x 620 -y 520 -defaultsOSRD -preplace port port-id_DAC_2_INB -pg 1 -lvl 3 -x 620 -y 720 -defaultsOSRD -preplace portBus Drive_DIR_1 -pg 1 -lvl 3 -x 620 -y 860 -defaultsOSRD -preplace portBus Drive_DIR_3 -pg 1 -lvl 3 -x 620 -y 960 -defaultsOSRD -preplace inst axi_timer_0 -pg 1 -lvl 2 -x 470 -y 310 -defaultsOSRD -preplace inst axi_timer_1 -pg 1 -lvl 2 -x 470 -y 110 -defaultsOSRD -preplace inst axi_timer_2 -pg 1 -lvl 2 -x 470 -y 510 -defaultsOSRD -preplace inst axi_timer_3 -pg 1 -lvl 2 -x 470 -y 710 -defaultsOSRD -preplace inst axi_gpio_2 -pg 1 -lvl 1 -x 180 -y 870 -defaultsOSRD -preplace inst xlslice_0 -pg 1 -lvl 2 -x 470 -y 860 -defaultsOSRD -preplace inst xlslice_1 -pg 1 -lvl 2 -x 470 -y 960 -defaultsOSRD -preplace netloc axi_timer_0_pwm0 1 2 1 NJ 320 -preplace netloc axi_timer_1_pwm0 1 2 1 NJ 120 -preplace netloc axi_timer_2_pwm0 1 2 1 NJ 520 -preplace netloc axi_timer_3_pwm0 1 2 1 NJ 720 -preplace netloc s_axi_aclk_1 1 0 2 20 740 330 -preplace netloc s_axi_aresetn_1 1 0 2 30 760 340 -preplace netloc axi_gpio_2_gpio_io_o 1 1 1 NJ 860 -preplace netloc axi_gpio_2_gpio2_io_o 1 1 1 330J 900n -preplace netloc xlslice_0_Dout 1 2 1 NJ 860 -preplace netloc xlslice_1_Dout 1 2 1 NJ 960 -preplace netloc Conn1 1 0 2 NJ 60 NJ -preplace netloc Conn2 1 0 2 NJ 460 NJ -preplace netloc Conn3 1 0 2 NJ 660 NJ -preplace netloc Conn4 1 0 1 NJ 850 -preplace netloc Conn5 1 0 2 NJ 260 NJ -levelinfo -pg 1 0 180 470 620 -pagesize -pg 1 -db -bbox -sgen -150 0 800 1020 +preplace port S_AXI -pg 1 -lvl 0 -x 0 -y 90 -defaultsOSRD +preplace port S_AXI1 -pg 1 -lvl 0 -x 0 -y 250 -defaultsOSRD +preplace port S_AXI2 -pg 1 -lvl 0 -x 0 -y 410 -defaultsOSRD +preplace port S_AXI3 -pg 1 -lvl 0 -x 0 -y 580 -defaultsOSRD +preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y 430 -defaultsOSRD +preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y 450 -defaultsOSRD +preplace port port-id_step_clk -pg 1 -lvl 0 -x 0 -y 520 -defaultsOSRD +preplace inst axi_gpio_0 -pg 1 -lvl 1 -x 180 -y 110 -defaultsOSRD +preplace inst axi_gpio_1 -pg 1 -lvl 1 -x 180 -y 270 -defaultsOSRD +preplace inst axi_gpio_2 -pg 1 -lvl 1 -x 180 -y 430 -defaultsOSRD +preplace inst axi_gpio_3 -pg 1 -lvl 1 -x 180 -y 600 -defaultsOSRD +preplace inst stepper_pulse_0 -pg 1 -lvl 2 -x 510 -y 80 -defaultsOSRD +preplace inst stepper_pulse_1 -pg 1 -lvl 2 -x 510 -y 240 -defaultsOSRD +preplace inst stepper_pulse_2 -pg 1 -lvl 2 -x 510 -y 400 -defaultsOSRD +preplace netloc axi_gpio_0_gpio_io_o 1 1 1 N 100 +preplace netloc axi_gpio_1_gpio_io_o 1 1 1 N 260 +preplace netloc axi_gpio_2_gpio_io_o 1 1 1 N 420 +preplace netloc axi_gpio_3_gpio_io_o 1 1 1 360 80n +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 1 30 130n +preplace netloc stepper_pulse_0_done 1 1 2 370 160 650 +preplace netloc stepper_pulse_1_done 1 1 2 350 320 650 +preplace netloc stepper_pulse_2_done 1 1 2 330 480 650 +preplace netloc s_axi_aclk_1 1 0 1 20 110n +preplace netloc step_clk_1 1 0 2 NJ 520 340 +preplace netloc axi_interconnect_0_M05_AXI 1 0 1 NJ 90 +preplace netloc axi_interconnect_0_M06_AXI 1 0 1 NJ 250 +preplace netloc axi_interconnect_0_M07_AXI 1 0 1 NJ 410 +preplace netloc axi_interconnect_0_M08_AXI 1 0 1 NJ 580 +levelinfo -pg 1 0 180 510 670 +pagesize -pg 1 -db -bbox -sgen -150 0 670 680 " } @@ -586,13 +654,13 @@ pagesize -pg 1 -db -bbox -sgen -150 0 800 1020 current_bd_instance $oldCurInst } -# Hierarchical cell: GPIO_Slicer -proc create_hier_cell_GPIO_Slicer { parentCell nameHier } { +# Hierarchical cell: drive +proc create_hier_cell_drive { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_GPIO_Slicer() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_drive() - Empty argument(s)!"} return } @@ -621,324 +689,73 @@ proc create_hier_cell_GPIO_Slicer { parentCell nameHier } { current_bd_instance $hier_obj # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI - # Create pins - create_bd_pin -dir I -from 31 -to 0 GPIO_buf - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_1 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_2 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_3 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_4 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_5 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_6 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_7 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_8 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_9 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_10 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_11 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_12 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_13 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_14 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_15 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_16 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_17 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_18 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_19 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_20 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_21 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_22 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_23 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_24 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_25 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_26 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_27 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_28 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_29 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_30 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_31 - create_bd_pin -dir O -from 0 -to 0 GPIO_buf_0 - - # Create instance: xlslice_0, and set properties - set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] - - # Create instance: xlslice_1, and set properties - set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] - set_property CONFIG.DIN_TO {1} $xlslice_1 - - - # Create instance: xlslice_2, and set properties - set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] - set_property -dict [list \ - CONFIG.DIN_FROM {2} \ - CONFIG.DIN_TO {2} \ - ] $xlslice_2 - - - # Create instance: xlslice_3, and set properties - set xlslice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 ] - set_property -dict [list \ - CONFIG.DIN_FROM {3} \ - CONFIG.DIN_TO {3} \ - ] $xlslice_3 - - - # Create instance: xlslice_4, and set properties - set xlslice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_4 ] - set_property -dict [list \ - CONFIG.DIN_FROM {4} \ - CONFIG.DIN_TO {4} \ - ] $xlslice_4 - - - # Create instance: xlslice_5, and set properties - set xlslice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_5 ] - set_property -dict [list \ - CONFIG.DIN_FROM {5} \ - CONFIG.DIN_TO {5} \ - ] $xlslice_5 - - - # Create instance: xlslice_6, and set properties - set xlslice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_6 ] - set_property -dict [list \ - CONFIG.DIN_FROM {6} \ - CONFIG.DIN_TO {6} \ - ] $xlslice_6 - - - # Create instance: xlslice_7, and set properties - set xlslice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_7 ] - set_property -dict [list \ - CONFIG.DIN_FROM {7} \ - CONFIG.DIN_TO {7} \ - ] $xlslice_7 - - - # Create instance: xlslice_8, and set properties - set xlslice_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_8 ] - set_property -dict [list \ - CONFIG.DIN_FROM {8} \ - CONFIG.DIN_TO {8} \ - ] $xlslice_8 - - - # Create instance: xlslice_9, and set properties - set xlslice_9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_9 ] - set_property -dict [list \ - CONFIG.DIN_FROM {9} \ - CONFIG.DIN_TO {9} \ - ] $xlslice_9 - - - # Create instance: xlslice_10, and set properties - set xlslice_10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_10 ] - set_property -dict [list \ - CONFIG.DIN_FROM {10} \ - CONFIG.DIN_TO {10} \ - ] $xlslice_10 - - - # Create instance: xlslice_11, and set properties - set xlslice_11 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_11 ] - set_property -dict [list \ - CONFIG.DIN_FROM {11} \ - CONFIG.DIN_TO {11} \ - ] $xlslice_11 - - - # Create instance: xlslice_12, and set properties - set xlslice_12 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_12 ] - set_property -dict [list \ - CONFIG.DIN_FROM {12} \ - CONFIG.DIN_TO {12} \ - ] $xlslice_12 - - - # Create instance: xlslice_13, and set properties - set xlslice_13 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_13 ] - set_property -dict [list \ - CONFIG.DIN_FROM {13} \ - CONFIG.DIN_TO {13} \ - ] $xlslice_13 - - - # Create instance: xlslice_14, and set properties - set xlslice_14 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_14 ] - set_property -dict [list \ - CONFIG.DIN_FROM {14} \ - CONFIG.DIN_TO {14} \ - ] $xlslice_14 - - - # Create instance: xlslice_15, and set properties - set xlslice_15 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_15 ] - set_property -dict [list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DIN_TO {15} \ - ] $xlslice_15 - - - # Create instance: xlslice_16, and set properties - set xlslice_16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_16 ] - set_property -dict [list \ - CONFIG.DIN_FROM {16} \ - CONFIG.DIN_TO {16} \ - ] $xlslice_16 - - - # Create instance: xlslice_17, and set properties - set xlslice_17 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_17 ] - set_property -dict [list \ - CONFIG.DIN_FROM {17} \ - CONFIG.DIN_TO {17} \ - ] $xlslice_17 - - - # Create instance: xlslice_18, and set properties - set xlslice_18 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_18 ] - set_property -dict [list \ - CONFIG.DIN_FROM {18} \ - CONFIG.DIN_TO {18} \ - ] $xlslice_18 - - - # Create instance: xlslice_19, and set properties - set xlslice_19 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_19 ] - set_property -dict [list \ - CONFIG.DIN_FROM {19} \ - CONFIG.DIN_TO {19} \ - ] $xlslice_19 - - - # Create instance: xlslice_20, and set properties - set xlslice_20 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_20 ] - set_property -dict [list \ - CONFIG.DIN_FROM {20} \ - CONFIG.DIN_TO {20} \ - ] $xlslice_20 - - - # Create instance: xlslice_21, and set properties - set xlslice_21 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_21 ] - set_property -dict [list \ - CONFIG.DIN_FROM {21} \ - CONFIG.DIN_TO {21} \ - ] $xlslice_21 - - - # Create instance: xlslice_22, and set properties - set xlslice_22 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_22 ] - set_property -dict [list \ - CONFIG.DIN_FROM {22} \ - CONFIG.DIN_TO {22} \ - ] $xlslice_22 - - - # Create instance: xlslice_23, and set properties - set xlslice_23 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_23 ] - set_property -dict [list \ - CONFIG.DIN_FROM {23} \ - CONFIG.DIN_TO {23} \ - ] $xlslice_23 - - - # Create instance: xlslice_24, and set properties - set xlslice_24 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_24 ] - set_property -dict [list \ - CONFIG.DIN_FROM {24} \ - CONFIG.DIN_TO {24} \ - ] $xlslice_24 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI1 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI2 - # Create instance: xlslice_25, and set properties - set xlslice_25 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_25 ] - set_property -dict [list \ - CONFIG.DIN_FROM {25} \ - CONFIG.DIN_TO {25} \ - ] $xlslice_25 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI3 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI4 - # Create instance: xlslice_26, and set properties - set xlslice_26 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_26 ] - set_property -dict [list \ - CONFIG.DIN_FROM {26} \ - CONFIG.DIN_TO {26} \ - ] $xlslice_26 + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir O DAC_1_INA + create_bd_pin -dir O DAC_1_INB + create_bd_pin -dir O DAC_2_INA + create_bd_pin -dir O DAC_2_INB + create_bd_pin -dir O -from 0 -to 0 Drive_DIR_1 + create_bd_pin -dir O -from 0 -to 0 Drive_DIR_3 - # Create instance: xlslice_27, and set properties - set xlslice_27 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_27 ] - set_property -dict [list \ - CONFIG.DIN_FROM {27} \ - CONFIG.DIN_TO {27} \ - ] $xlslice_27 + # Create instance: axi_timer_0, and set properties + set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] + # Create instance: axi_timer_1, and set properties + set axi_timer_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_1 ] - # Create instance: xlslice_28, and set properties - set xlslice_28 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_28 ] - set_property -dict [list \ - CONFIG.DIN_FROM {28} \ - CONFIG.DIN_TO {28} \ - ] $xlslice_28 + # Create instance: axi_timer_2, and set properties + set axi_timer_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_2 ] + # Create instance: axi_timer_3, and set properties + set axi_timer_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_3 ] - # Create instance: xlslice_29, and set properties - set xlslice_29 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_29 ] + # Create instance: axi_gpio_2, and set properties + set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] set_property -dict [list \ - CONFIG.DIN_FROM {29} \ - CONFIG.DIN_TO {29} \ - ] $xlslice_29 - + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_ALL_OUTPUTS_2 {1} \ + CONFIG.C_DOUT_DEFAULT {0xFFFFFFFF} \ + CONFIG.C_IS_DUAL {1} \ + ] $axi_gpio_2 - # Create instance: xlslice_30, and set properties - set xlslice_30 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_30 ] - set_property -dict [list \ - CONFIG.DIN_FROM {30} \ - CONFIG.DIN_TO {30} \ - ] $xlslice_30 + # Create instance: xlslice_0, and set properties + set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] - # Create instance: xlslice_31, and set properties - set xlslice_31 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_31 ] - set_property -dict [list \ - CONFIG.DIN_FROM {31} \ - CONFIG.DIN_TO {31} \ - ] $xlslice_31 + # Create instance: xlslice_1, and set properties + set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axi_timer_1/S_AXI] [get_bd_intf_pins S_AXI] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_timer_2/S_AXI] [get_bd_intf_pins S_AXI1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins axi_timer_3/S_AXI] [get_bd_intf_pins S_AXI2] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins S_AXI3] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins S_AXI4] # Create port connections - connect_bd_net -net GPIO_buf_1 [get_bd_pins GPIO_buf] [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_3/Din] [get_bd_pins xlslice_4/Din] [get_bd_pins xlslice_5/Din] [get_bd_pins xlslice_6/Din] [get_bd_pins xlslice_2/Din] [get_bd_pins xlslice_7/Din] [get_bd_pins xlslice_8/Din] [get_bd_pins xlslice_9/Din] [get_bd_pins xlslice_10/Din] [get_bd_pins xlslice_11/Din] [get_bd_pins xlslice_12/Din] [get_bd_pins xlslice_13/Din] [get_bd_pins xlslice_14/Din] [get_bd_pins xlslice_15/Din] [get_bd_pins xlslice_16/Din] [get_bd_pins xlslice_17/Din] [get_bd_pins xlslice_18/Din] [get_bd_pins xlslice_19/Din] [get_bd_pins xlslice_20/Din] [get_bd_pins xlslice_21/Din] [get_bd_pins xlslice_22/Din] [get_bd_pins xlslice_23/Din] [get_bd_pins xlslice_24/Din] [get_bd_pins xlslice_31/Din] [get_bd_pins xlslice_30/Din] [get_bd_pins xlslice_29/Din] [get_bd_pins xlslice_28/Din] [get_bd_pins xlslice_27/Din] [get_bd_pins xlslice_26/Din] [get_bd_pins xlslice_25/Din] - connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins GPIO_buf_0] - connect_bd_net -net xlslice_10_Dout [get_bd_pins xlslice_10/Dout] [get_bd_pins GPIO_buf_10] - connect_bd_net -net xlslice_11_Dout [get_bd_pins xlslice_11/Dout] [get_bd_pins GPIO_buf_11] - connect_bd_net -net xlslice_12_Dout [get_bd_pins xlslice_12/Dout] [get_bd_pins GPIO_buf_12] - connect_bd_net -net xlslice_13_Dout [get_bd_pins xlslice_13/Dout] [get_bd_pins GPIO_buf_13] - connect_bd_net -net xlslice_14_Dout [get_bd_pins xlslice_14/Dout] [get_bd_pins GPIO_buf_14] - connect_bd_net -net xlslice_15_Dout [get_bd_pins xlslice_15/Dout] [get_bd_pins GPIO_buf_15] - connect_bd_net -net xlslice_16_Dout [get_bd_pins xlslice_16/Dout] [get_bd_pins GPIO_buf_16] - connect_bd_net -net xlslice_17_Dout [get_bd_pins xlslice_17/Dout] [get_bd_pins GPIO_buf_17] - connect_bd_net -net xlslice_18_Dout [get_bd_pins xlslice_18/Dout] [get_bd_pins GPIO_buf_18] - connect_bd_net -net xlslice_19_Dout [get_bd_pins xlslice_19/Dout] [get_bd_pins GPIO_buf_19] - connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins GPIO_buf_1] - connect_bd_net -net xlslice_20_Dout [get_bd_pins xlslice_20/Dout] [get_bd_pins GPIO_buf_20] - connect_bd_net -net xlslice_21_Dout [get_bd_pins xlslice_21/Dout] [get_bd_pins GPIO_buf_21] - connect_bd_net -net xlslice_22_Dout [get_bd_pins xlslice_22/Dout] [get_bd_pins GPIO_buf_22] - connect_bd_net -net xlslice_23_Dout [get_bd_pins xlslice_23/Dout] [get_bd_pins GPIO_buf_23] - connect_bd_net -net xlslice_24_Dout [get_bd_pins xlslice_24/Dout] [get_bd_pins GPIO_buf_24] - connect_bd_net -net xlslice_25_Dout [get_bd_pins xlslice_25/Dout] [get_bd_pins GPIO_buf_25] - connect_bd_net -net xlslice_26_Dout [get_bd_pins xlslice_26/Dout] [get_bd_pins GPIO_buf_26] - connect_bd_net -net xlslice_27_Dout [get_bd_pins xlslice_27/Dout] [get_bd_pins GPIO_buf_27] - connect_bd_net -net xlslice_28_Dout [get_bd_pins xlslice_28/Dout] [get_bd_pins GPIO_buf_28] - connect_bd_net -net xlslice_29_Dout [get_bd_pins xlslice_29/Dout] [get_bd_pins GPIO_buf_29] - connect_bd_net -net xlslice_2_Dout [get_bd_pins xlslice_2/Dout] [get_bd_pins GPIO_buf_2] - connect_bd_net -net xlslice_30_Dout [get_bd_pins xlslice_30/Dout] [get_bd_pins GPIO_buf_30] - connect_bd_net -net xlslice_31_Dout [get_bd_pins xlslice_31/Dout] [get_bd_pins GPIO_buf_31] - connect_bd_net -net xlslice_3_Dout [get_bd_pins xlslice_3/Dout] [get_bd_pins GPIO_buf_3] - connect_bd_net -net xlslice_4_Dout [get_bd_pins xlslice_4/Dout] [get_bd_pins GPIO_buf_4] - connect_bd_net -net xlslice_5_Dout [get_bd_pins xlslice_5/Dout] [get_bd_pins GPIO_buf_5] - connect_bd_net -net xlslice_6_Dout [get_bd_pins xlslice_6/Dout] [get_bd_pins GPIO_buf_6] - connect_bd_net -net xlslice_7_Dout [get_bd_pins xlslice_7/Dout] [get_bd_pins GPIO_buf_7] - connect_bd_net -net xlslice_8_Dout [get_bd_pins xlslice_8/Dout] [get_bd_pins GPIO_buf_8] - connect_bd_net -net xlslice_9_Dout [get_bd_pins xlslice_9/Dout] [get_bd_pins GPIO_buf_9] + connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins axi_gpio_2/gpio2_io_o] [get_bd_pins xlslice_1/Din] + connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_2/gpio_io_o] [get_bd_pins xlslice_0/Din] + connect_bd_net -net axi_timer_0_pwm0 [get_bd_pins axi_timer_0/pwm0] [get_bd_pins DAC_1_INA] + connect_bd_net -net axi_timer_1_pwm0 [get_bd_pins axi_timer_1/pwm0] [get_bd_pins DAC_1_INB] + connect_bd_net -net axi_timer_2_pwm0 [get_bd_pins axi_timer_2/pwm0] [get_bd_pins DAC_2_INA] + connect_bd_net -net axi_timer_3_pwm0 [get_bd_pins axi_timer_3/pwm0] [get_bd_pins DAC_2_INB] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_timer_1/s_axi_aclk] [get_bd_pins axi_timer_2/s_axi_aclk] [get_bd_pins axi_timer_3/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins axi_timer_1/s_axi_aresetn] [get_bd_pins axi_timer_3/s_axi_aresetn] [get_bd_pins axi_timer_2/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] + connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins Drive_DIR_1] + connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins Drive_DIR_3] # Restore current instance current_bd_instance $oldCurInst @@ -981,24 +798,14 @@ proc create_hier_cell_GPIO_Slicer { parentCell nameHier } { set DAC_1_INB [ create_bd_port -dir O -type data DAC_1_INB ] set DAC_2_INA [ create_bd_port -dir O -type data DAC_2_INA ] set DAC_2_INB [ create_bd_port -dir O -type data DAC_2_INB ] - set M0_1 [ create_bd_port -dir O -from 0 -to 0 M0_1 ] - set M1_1 [ create_bd_port -dir O -from 0 -to 0 M1_1 ] - set CONFIG_1 [ create_bd_port -dir O -from 0 -to 0 CONFIG_1 ] - set NENBL_1 [ create_bd_port -dir O -from 0 -to 0 NENBL_1 ] - set STEP_1 [ create_bd_port -dir O -from 0 -to 0 STEP_1 ] - set DIR_1 [ create_bd_port -dir O -from 0 -to 0 DIR_1 ] - set Breakout1_1 [ create_bd_port -dir O -from 0 -to 0 Breakout1_1 ] - set Breakout1_2 [ create_bd_port -dir O -from 0 -to 0 Breakout1_2 ] - set Breakout1_3 [ create_bd_port -dir O -from 0 -to 0 Breakout1_3 ] - set Sensor_IO_8 [ create_bd_port -dir O -from 0 -to 0 Sensor_IO_8 ] - set Sensor_IO_1 [ create_bd_port -dir O -from 0 -to 0 Sensor_IO_1 ] - set Sensor_IO_2 [ create_bd_port -dir O -from 0 -to 0 Sensor_IO_2 ] - set Sensor_IO_3 [ create_bd_port -dir O -from 0 -to 0 Sensor_IO_3 ] - set Sensor_IO_5 [ create_bd_port -dir O -from 0 -to 0 Sensor_IO_5 ] set Drive_DIR_1 [ create_bd_port -dir O -from 0 -to 0 -type data Drive_DIR_1 ] set Drive_DIR_2 [ create_bd_port -dir O -from 0 -to 0 -type data Drive_DIR_2 ] set Drive_DIR_3 [ create_bd_port -dir O -from 0 -to 0 -type data Drive_DIR_3 ] set Drive_DIR_4 [ create_bd_port -dir O -from 0 -to 0 -type data Drive_DIR_4 ] + set reset_rtl [ create_bd_port -dir I -type rst reset_rtl ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $reset_rtl # Create instance: processing_system7_0, and set properties set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] @@ -1009,7 +816,7 @@ proc create_hier_cell_GPIO_Slicer { parentCell nameHier } { CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ - CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {1.000000} \ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ @@ -1029,7 +836,7 @@ proc create_hier_cell_GPIO_Slicer { parentCell nameHier } { CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {667} \ CONFIG.PCW_CLK0_FREQ {100000000} \ - CONFIG.PCW_CLK1_FREQ {10000000} \ + CONFIG.PCW_CLK1_FREQ {1000000} \ CONFIG.PCW_CLK2_FREQ {10000000} \ CONFIG.PCW_CLK3_FREQ {10000000} \ CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ @@ -1050,7 +857,7 @@ proc create_hier_cell_GPIO_Slicer { parentCell nameHier } { CONFIG.PCW_ENET_RESET_ENABLE {1} \ CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ CONFIG.PCW_EN_CLK0_PORT {1} \ - CONFIG.PCW_EN_CLK1_PORT {0} \ + CONFIG.PCW_EN_CLK1_PORT {1} \ CONFIG.PCW_EN_CLK2_PORT {0} \ CONFIG.PCW_EN_CLK3_PORT {0} \ CONFIG.PCW_EN_DDR {1} \ @@ -1071,11 +878,13 @@ proc create_hier_cell_GPIO_Slicer { parentCell nameHier } { CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ - CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {1} \ CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {33.333333} \ CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ @@ -1343,38 +1152,22 @@ proc create_hier_cell_GPIO_Slicer { parentCell nameHier } { ] $axi_interconnect_0 - # Create instance: axi_gpio_0, and set properties - set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] - set_property -dict [list \ - CONFIG.C_ALL_OUTPUTS {1} \ - CONFIG.C_DOUT_DEFAULT {0xFFFFFFFF} \ - CONFIG.C_IS_DUAL {0} \ - ] $axi_gpio_0 - - - # Create instance: GPIO_Slicer - create_hier_cell_GPIO_Slicer [current_bd_instance .] GPIO_Slicer - - # Create instance: axi_gpio_1, and set properties - set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ] - set_property -dict [list \ - CONFIG.C_ALL_OUTPUTS {1} \ - CONFIG.C_DOUT_DEFAULT {0xFFFFFFFF} \ - CONFIG.C_GPIO_WIDTH {1} \ - ] $axi_gpio_1 - - # Create instance: drive create_hier_cell_drive [current_bd_instance .] drive + # Create instance: gantry + create_hier_cell_gantry [current_bd_instance .] gantry + # Create interface connections - connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins drive/S_AXI4] - connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins drive/S_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins drive/S_AXI1] - connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins drive/S_AXI2] - connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins axi_interconnect_0/M04_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins axi_interconnect_0/M05_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins axi_interconnect_0/M06_AXI] [get_bd_intf_pins drive/S_AXI3] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins drive/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins axi_interconnect_0/M01_AXI] [get_bd_intf_pins drive/S_AXI1] + connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins drive/S_AXI2] + connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins drive/S_AXI3] + connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins axi_interconnect_0/M04_AXI] [get_bd_intf_pins drive/S_AXI4] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins axi_interconnect_0/M05_AXI] [get_bd_intf_pins gantry/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins axi_interconnect_0/M06_AXI] [get_bd_intf_pins gantry/S_AXI1] + connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins axi_interconnect_0/M07_AXI] [get_bd_intf_pins gantry/S_AXI2] + connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_interconnect_0/M08_AXI] [get_bd_intf_pins gantry/S_AXI3] connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins axi_interconnect_0/S00_AXI] @@ -1382,123 +1175,76 @@ proc create_hier_cell_GPIO_Slicer { parentCell nameHier } { # Create port connections connect_bd_net -net Drive_Dir1 [get_bd_pins drive/DAC_2_INB] [get_bd_ports DAC_2_INB] - connect_bd_net -net GPIO_Slicer_GPIO_buf_5 [get_bd_pins GPIO_Slicer/GPIO_buf_5] [get_bd_ports M0_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_6 [get_bd_pins GPIO_Slicer/GPIO_buf_6] [get_bd_ports M1_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_7 [get_bd_pins GPIO_Slicer/GPIO_buf_7] [get_bd_ports CONFIG_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_8 [get_bd_pins GPIO_Slicer/GPIO_buf_8] [get_bd_ports NENBL_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_9 [get_bd_pins GPIO_Slicer/GPIO_buf_9] [get_bd_ports DIR_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_10 [get_bd_pins GPIO_Slicer/GPIO_buf_10] [get_bd_ports STEP_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_11 [get_bd_pins GPIO_Slicer/GPIO_buf_11] [get_bd_ports Breakout1_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_12 [get_bd_pins GPIO_Slicer/GPIO_buf_12] [get_bd_ports Breakout1_2] - connect_bd_net -net GPIO_Slicer_GPIO_buf_13 [get_bd_pins GPIO_Slicer/GPIO_buf_13] [get_bd_ports Breakout1_3] - connect_bd_net -net GPIO_Slicer_GPIO_buf_14 [get_bd_pins GPIO_Slicer/GPIO_buf_14] [get_bd_ports Sensor_IO_1] - connect_bd_net -net GPIO_Slicer_GPIO_buf_15 [get_bd_pins GPIO_Slicer/GPIO_buf_15] [get_bd_ports Sensor_IO_3] - connect_bd_net -net GPIO_Slicer_GPIO_buf_16 [get_bd_pins GPIO_Slicer/GPIO_buf_16] [get_bd_ports Sensor_IO_5] - connect_bd_net -net GPIO_Slicer_GPIO_buf_17 [get_bd_pins GPIO_Slicer/GPIO_buf_17] [get_bd_ports Sensor_IO_2] - connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins GPIO_Slicer/GPIO_buf] - connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_ports Sensor_IO_8] connect_bd_net -net drive_DAC_1_INA [get_bd_pins drive/DAC_1_INA] [get_bd_ports DAC_1_INA] connect_bd_net -net drive_DAC_1_INB [get_bd_pins drive/DAC_1_INB] [get_bd_ports DAC_1_INB] connect_bd_net -net drive_DAC_2_INA [get_bd_pins drive/DAC_2_INA] [get_bd_ports DAC_2_INA] connect_bd_net -net drive_Drive_DIR_1 [get_bd_pins drive/Drive_DIR_1] [get_bd_ports Drive_DIR_1] [get_bd_ports Drive_DIR_2] connect_bd_net -net drive_Drive_DIR_3 [get_bd_pins drive/Drive_DIR_3] [get_bd_ports Drive_DIR_3] [get_bd_ports Drive_DIR_4] - connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins drive/s_axi_aclk] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins drive/s_axi_aclk] [get_bd_pins gantry/s_axi_aclk] connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in] - connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins drive/s_axi_aresetn] + connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins drive/s_axi_aresetn] [get_bd_pins gantry/s_axi_aresetn] + connect_bd_net -net step_clk_1 [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins gantry/step_clk] # Create address segments - assign_bd_address -dict [list offset 0x7FFF8000 range 0x00008000 offset 0x80000000 range 0x00008000] -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] -force - assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_1/S_AXI/Reg] -force - assign_bd_address -offset 0x41210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_gpio_2/S_AXI/Reg] -force - assign_bd_address -offset 0x42800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_0/S_AXI/Reg] -force - assign_bd_address -offset 0x42810000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_1/S_AXI/Reg] -force - assign_bd_address -offset 0x42820000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_2/S_AXI/Reg] -force - assign_bd_address -offset 0x42830000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_3/S_AXI/Reg] -force # Perform GUI Layout regenerate_bd_layout -layout_string { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"1.89465", - "Default View_TopLeft":"1295,-10", + "Default View_ScaleFactor":"0.718997", + "Default View_TopLeft":"-213,1", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS # -string -flagsOSRD -preplace port DDR -pg 1 -lvl 5 -x 1530 -y 60 -defaultsOSRD -preplace port FIXED_IO -pg 1 -lvl 5 -x 1530 -y 80 -defaultsOSRD -preplace port port-id_DAC_1_INA -pg 1 -lvl 5 -x 1530 -y 360 -defaultsOSRD -preplace port port-id_DAC_1_INB -pg 1 -lvl 5 -x 1530 -y 380 -defaultsOSRD -preplace port port-id_DAC_2_INA -pg 1 -lvl 5 -x 1530 -y 400 -defaultsOSRD -preplace port port-id_DAC_2_INB -pg 1 -lvl 5 -x 1530 -y 420 -defaultsOSRD -preplace portBus M0_1 -pg 1 -lvl 5 -x 1530 -y 800 -defaultsOSRD -preplace portBus M1_1 -pg 1 -lvl 5 -x 1530 -y 820 -defaultsOSRD -preplace portBus CONFIG_1 -pg 1 -lvl 5 -x 1530 -y 840 -defaultsOSRD -preplace portBus NENBL_1 -pg 1 -lvl 5 -x 1530 -y 860 -defaultsOSRD -preplace portBus STEP_1 -pg 1 -lvl 5 -x 1530 -y 900 -defaultsOSRD -preplace portBus DIR_1 -pg 1 -lvl 5 -x 1530 -y 880 -defaultsOSRD -preplace portBus Breakout1_1 -pg 1 -lvl 5 -x 1530 -y 920 -defaultsOSRD -preplace portBus Breakout1_2 -pg 1 -lvl 5 -x 1530 -y 940 -defaultsOSRD -preplace portBus Breakout1_3 -pg 1 -lvl 5 -x 1530 -y 960 -defaultsOSRD -preplace portBus Sensor_IO_8 -pg 1 -lvl 5 -x 1530 -y 610 -defaultsOSRD -preplace portBus Sensor_IO_1 -pg 1 -lvl 5 -x 1530 -y 980 -defaultsOSRD -preplace portBus Sensor_IO_2 -pg 1 -lvl 5 -x 1530 -y 1040 -defaultsOSRD -preplace portBus Sensor_IO_3 -pg 1 -lvl 5 -x 1530 -y 1000 -defaultsOSRD -preplace portBus Sensor_IO_5 -pg 1 -lvl 5 -x 1530 -y 1020 -defaultsOSRD -preplace portBus Drive_DIR_1 -pg 1 -lvl 5 -x 1530 -y 440 -defaultsOSRD -preplace portBus Drive_DIR_2 -pg 1 -lvl 5 -x 1530 -y 460 -defaultsOSRD -preplace portBus Drive_DIR_3 -pg 1 -lvl 5 -x 1530 -y 480 -defaultsOSRD -preplace portBus Drive_DIR_4 -pg 1 -lvl 5 -x 1530 -y 500 -defaultsOSRD -preplace inst processing_system7_0 -pg 1 -lvl 2 -x 600 -y 150 -defaultsOSRD -preplace inst rst_ps7_0_100M -pg 1 -lvl 1 -x 210 -y 410 -defaultsOSRD -preplace inst axi_interconnect_0 -pg 1 -lvl 3 -x 990 -y 420 -defaultsOSRD -preplace inst axi_gpio_0 -pg 1 -lvl 4 -x 1350 -y 230 -defaultsOSRD -preplace inst GPIO_Slicer -pg 1 -lvl 4 -x 1350 -y 1030 -defaultsOSRD -preplace inst axi_gpio_1 -pg 1 -lvl 4 -x 1350 -y 600 -defaultsOSRD -preplace inst drive -pg 1 -lvl 4 -x 1350 -y 410 -defaultsOSRD -preplace netloc GPIO_Slicer_GPIO_buf_5 1 4 1 NJ 800 -preplace netloc GPIO_Slicer_GPIO_buf_6 1 4 1 NJ 820 -preplace netloc GPIO_Slicer_GPIO_buf_7 1 4 1 NJ 840 -preplace netloc GPIO_Slicer_GPIO_buf_8 1 4 1 NJ 860 -preplace netloc GPIO_Slicer_GPIO_buf_9 1 4 1 NJ 880 -preplace netloc GPIO_Slicer_GPIO_buf_10 1 4 1 NJ 900 -preplace netloc GPIO_Slicer_GPIO_buf_11 1 4 1 NJ 920 -preplace netloc GPIO_Slicer_GPIO_buf_12 1 4 1 NJ 940 -preplace netloc GPIO_Slicer_GPIO_buf_13 1 4 1 NJ 960 -preplace netloc GPIO_Slicer_GPIO_buf_14 1 4 1 NJ 980 -preplace netloc GPIO_Slicer_GPIO_buf_15 1 4 1 NJ 1000 -preplace netloc GPIO_Slicer_GPIO_buf_16 1 4 1 NJ 1020 -preplace netloc GPIO_Slicer_GPIO_buf_17 1 4 1 NJ 1040 -preplace netloc axi_gpio_0_gpio_io_o 1 3 2 1200 150 1500 -preplace netloc axi_gpio_1_gpio_io_o 1 4 1 NJ 610 -preplace netloc drive_DAC_1_INA 1 4 1 NJ 360 -preplace netloc drive_DAC_1_INB 1 4 1 NJ 380 -preplace netloc drive_DAC_2_INA 1 4 1 NJ 400 -preplace netloc Drive_Dir1 1 4 1 N 420 -preplace netloc processing_system7_0_FCLK_CLK0 1 0 4 20 160 390 0 820 70 1190 -preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 3 30 300 NJ 300 810 -preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 3 NJ 450 830 90 1150 -preplace netloc drive_Drive_DIR_1 1 4 1 1510 440n -preplace netloc drive_Drive_DIR_3 1 4 1 1500 460n -preplace netloc axi_interconnect_0_M00_AXI 1 3 1 1170 330n -preplace netloc axi_interconnect_0_M01_AXI 1 3 1 N 350 -preplace netloc axi_interconnect_0_M02_AXI 1 3 1 N 370 -preplace netloc axi_interconnect_0_M03_AXI 1 3 1 N 390 -preplace netloc axi_interconnect_0_M04_AXI 1 3 1 1160 210n -preplace netloc axi_interconnect_0_M05_AXI 1 3 1 1140 430n -preplace netloc axi_interconnect_0_M06_AXI 1 3 1 1180 410n -preplace netloc processing_system7_0_DDR 1 2 3 NJ 60 NJ 60 NJ -preplace netloc processing_system7_0_FIXED_IO 1 2 3 NJ 80 NJ 80 NJ -preplace netloc processing_system7_0_M_AXI_GP0 1 2 1 840 120n -preplace netloc processing_system7_0_M_AXI_GP1 1 2 1 810 140n -levelinfo -pg 1 0 210 600 990 1350 1530 -pagesize -pg 1 -db -bbox -sgen -130 -20 1710 1390 +preplace port DDR -pg 1 -lvl 4 -x 1170 -y 60 -defaultsOSRD +preplace port FIXED_IO -pg 1 -lvl 4 -x 1170 -y 80 -defaultsOSRD +preplace port port-id_DAC_1_INA -pg 1 -lvl 4 -x 1170 -y 330 -defaultsOSRD +preplace port port-id_DAC_1_INB -pg 1 -lvl 4 -x 1170 -y 350 -defaultsOSRD +preplace port port-id_DAC_2_INA -pg 1 -lvl 4 -x 1170 -y 370 -defaultsOSRD +preplace port port-id_DAC_2_INB -pg 1 -lvl 4 -x 1170 -y 390 -defaultsOSRD +preplace port port-id_reset_rtl -pg 1 -lvl 0 -x 0 -y 20 -defaultsOSRD +preplace portBus Drive_DIR_1 -pg 1 -lvl 4 -x 1170 -y 410 -defaultsOSRD +preplace portBus Drive_DIR_2 -pg 1 -lvl 4 -x 1170 -y 430 -defaultsOSRD +preplace portBus Drive_DIR_3 -pg 1 -lvl 4 -x 1170 -y 450 -defaultsOSRD +preplace portBus Drive_DIR_4 -pg 1 -lvl 4 -x 1170 -y 470 -defaultsOSRD +preplace inst processing_system7_0 -pg 1 -lvl 1 -x 240 -y 160 -defaultsOSRD +preplace inst rst_ps7_0_100M -pg 1 -lvl 1 -x 240 -y 430 -defaultsOSRD +preplace inst axi_interconnect_0 -pg 1 -lvl 2 -x 630 -y 410 -defaultsOSRD -resize 260 616 +preplace inst drive -pg 1 -lvl 3 -x 990 -y 380 -defaultsOSRD +preplace inst gantry -pg 1 -lvl 3 -x 990 -y 610 -defaultsOSRD -resize 247 226 +preplace netloc Drive_Dir1 1 3 1 NJ 390 +preplace netloc drive_DAC_1_INA 1 3 1 NJ 330 +preplace netloc drive_DAC_1_INB 1 3 1 NJ 350 +preplace netloc drive_DAC_2_INA 1 3 1 NJ 370 +preplace netloc drive_Drive_DIR_1 1 3 1 1150 410n +preplace netloc drive_Drive_DIR_3 1 3 1 1140 430n +preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 20 320 470 740 810 +preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 2 30 330 450 +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 2 480 750 840 +preplace netloc step_clk_1 1 1 2 450 70 820J +preplace netloc axi_interconnect_0_M00_AXI 1 2 1 N 320 +preplace netloc axi_interconnect_0_M01_AXI 1 2 1 N 340 +preplace netloc axi_interconnect_0_M02_AXI 1 2 1 N 360 +preplace netloc axi_interconnect_0_M03_AXI 1 2 1 N 380 +preplace netloc axi_interconnect_0_M04_AXI 1 2 1 N 400 +preplace netloc axi_interconnect_0_M05_AXI 1 2 1 790 420n +preplace netloc axi_interconnect_0_M06_AXI 1 2 1 830 440n +preplace netloc axi_interconnect_0_M07_AXI 1 2 1 800 460n +preplace netloc axi_interconnect_0_M08_AXI 1 2 1 780 480n +preplace netloc processing_system7_0_DDR 1 1 3 NJ 60 NJ 60 NJ +preplace netloc processing_system7_0_FIXED_IO 1 1 3 NJ 80 NJ 80 NJ +preplace netloc processing_system7_0_M_AXI_GP0 1 1 1 470 120n +preplace netloc processing_system7_0_M_AXI_GP1 1 1 1 460 140n +levelinfo -pg 1 0 240 630 990 1170 +pagesize -pg 1 -db -bbox -sgen -110 0 1340 770 " } # Restore current instance current_bd_instance $oldCurInst - validate_bd_design save_bd_design +common::send_gid_msg -ssname BD::TCL -id 2050 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." + close_bd_design $design_name } # End of cr_bd_mercury() @@ -1568,7 +1314,7 @@ set_property -name "flow" -value "Vivado Synthesis 2023" -objects $obj set_property -name "name" -value "synth_1" -objects $obj set_property -name "needs_refresh" -value "0" -objects $obj set_property -name "srcset" -value "sources_1" -objects $obj -set_property -name "incremental_checkpoint" -value "$proj_dir/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp" -objects $obj +set_property -name "incremental_checkpoint" -value "" -objects $obj set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj set_property -name "rqs_files" -value "" -objects $obj set_property -name "auto_rqs.suggestion_run" -value "" -objects $obj diff --git a/mercury-hdl/stepper_pulse.v b/mercury-hdl/stepper_pulse.v new file mode 100644 index 0000000..e709380 --- /dev/null +++ b/mercury-hdl/stepper_pulse.v @@ -0,0 +1,68 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 03/21/2024 11:49:41 AM +// Design Name: +// Module Name: stepper_pulse +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module stepper_pulse( + input wire clk, // System clock + input wire rst_n, // Active low reset + input wire [31:0] pulse_count, // Number of pulses to generate from AXI GPIO + output reg pulse, // Pulse output to stepper motor + output reg done // Signal to indicate when pulsing is complete +); + +localparam DIVIDE_BY = 2000; // 1000KHz / 2000 = 0.5KHz toggle rate, 1KHz pulse rate + +// Internal signals +reg [31:0] pulse_counter; // Counter for pulses generated +reg generating; // Flag to indicate if pulse generation is active + +// Pulse generation control +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + // Reset condition + pulse_counter <= 32'd0; + pulse <= 1'b0; + generating <= 1'b0; + done <= 1'b0; + end else if (pulse_counter < pulse_count && generating) begin + // Generate pulse + pulse <= !pulse; // Toggle the pulse + done <= 1'b0; // Not done yet + if (pulse) // Count on one edge to avoid double counting + pulse_counter <= pulse_counter + 1; + end else if (generating) begin + // Finished generating pulses + generating <= 1'b0; + pulse <= 1'b0; // Ensure pulse is low when not generating + done <= 1'b1; // Signal that pulsing is complete + end else if (pulse_count > 0 && !generating && pulse_counter == 0) begin + generating <= 1'b1; + pulse_counter <= 32'd0; // Reset counter + done <= 1'b0; // Ensure done is low at the start + end + + if (!generating) begin + done <= 1'b0; // Ensure 'done' is low when we are not in generating state + end +end + +endmodule + From 1c0dcfcfedc50e2c766421c66328dfc46966355b Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Sat, 23 Mar 2024 18:19:02 -0400 Subject: [PATCH 3/9] Adding in services --- mercury-app/src/hw_ifc/src/gantry_model.rs | 21 ++++--- mercury-app/src/hw_ifc/src/gantry_sub.rs | 60 ++++++++++--------- mercury-app/src/hw_srv/srv/calibrate.srv | 2 - .../src/hw_srv/srv/calibrategantry.srv | 2 + mercury-app/src/hw_srv/srv/movegantry.srv | 5 ++ 5 files changed, 49 insertions(+), 41 deletions(-) delete mode 100644 mercury-app/src/hw_srv/srv/calibrate.srv create mode 100644 mercury-app/src/hw_srv/srv/calibrategantry.srv create mode 100644 mercury-app/src/hw_srv/srv/movegantry.srv diff --git a/mercury-app/src/hw_ifc/src/gantry_model.rs b/mercury-app/src/hw_ifc/src/gantry_model.rs index 1154ec6..64ec978 100644 --- a/mercury-app/src/hw_ifc/src/gantry_model.rs +++ b/mercury-app/src/hw_ifc/src/gantry_model.rs @@ -3,9 +3,9 @@ use std::ops::{Index, IndexMut}; pub enum GantryAxes { - GantryX, - GantryY, - GantryZ, + X, + Y, + Z, } pub struct StepperCtrlCmd { @@ -24,9 +24,9 @@ impl Index for StepperCtrlCmdGroup { fn index(&self, side: GantryAxes) -> &Self::Output { match side { - GantryAxes::GantryX => &self.x, - GantryAxes::GantryY => &self.y, - GantryAxes::GantryZ => &self.z, + GantryAxes::X => &self.x, + GantryAxes::Y => &self.y, + GantryAxes::Z => &self.z, } } } @@ -34,9 +34,9 @@ impl Index for StepperCtrlCmdGroup { impl IndexMut for StepperCtrlCmdGroup { fn index_mut(&mut self, side: GantryAxes) -> &mut Self::Output { match side { - GantryAxes::GantryX => &mut self.x, - GantryAxes::GantryY => &mut self.y, - GantryAxes::GantryZ => &mut self.z, + GantryAxes::X => &mut self.x, + GantryAxes::Y => &mut self.y, + GantryAxes::Z => &mut self.z, } } } @@ -58,7 +58,7 @@ impl GantryModel { x: 0.0, y: 0.0, z: 0.0, - } + }, } } @@ -79,7 +79,6 @@ impl GantryModel { // Update current position self.current_position = target_position; - // For now, we'll set the same speed for all axes, but this could be adjusted based on the axis and specific requirements StepperCtrlCmdGroup { x: StepperCtrlCmd { steps: x_steps, diff --git a/mercury-app/src/hw_ifc/src/gantry_sub.rs b/mercury-app/src/hw_ifc/src/gantry_sub.rs index 04262f5..c4f8bbc 100644 --- a/mercury-app/src/hw_ifc/src/gantry_sub.rs +++ b/mercury-app/src/hw_ifc/src/gantry_sub.rs @@ -4,9 +4,10 @@ pub mod gantry_model; use self::gantry_model::{ GantryAxes, GantryModel, GantryPosition, StepperCtrlCmd, StepperCtrlCmdGroup, }; +use std::sync::Arc; pub mod msg { - rosrust::rosmsg_include!(hw_srv/calibrate); + rosrust::rosmsg_include!(hw_srv / movegantry, hw_srv / calibrategantry); } pub struct GantryController { @@ -16,41 +17,44 @@ pub struct GantryController { impl GantryController { pub fn new() -> Self { GantryController { - model: GantryModel::new(), - } + model: GantryModel::new(), + } } - pub fn command_callback(&self, data: rosrust_msg::hw_srv::calibrate) {} + pub fn move_callback(&self, data: rosrust_msg::hw_srv::movegantryReq) {} + + pub fn calibrate_callback(&self) {} } fn main() { /* Initialize ROS node */ rosrust::init("gantry_sub"); - let gantry_ctrl = GantryController::new(); - - /* - * Create subscriber - */ - //let _subscriber_info = rosrust::subscribe_with_ids( - // "/gantry/pose/goal", - // 2, - // move |v: rosrust_msg::hw_srv::calibrate, _caller_id: &str| { - // gantry_ctrl.command_callback(v); - // }, - //) - //.unwrap(); - - /** - * Create service - */ - //let _service_raii = - // rosrust::service::("/services/gantry/calibrate", move |req| { - // gantry_ctrl.command_callback(req); -// - // Ok(rosrust_msg::hw_srv::calibrate { }) - // }) - // .unwrap(); + let gantry_ctrl = Arc::new(GantryController::new()); + + /* Create subscriber */ + let gantry_ctrl_clone = gantry_ctrl.clone(); + let service_move = rosrust::service::( + "/gantry/pose/goal", + move |coords: rosrust_msg::hw_srv::movegantryReq| { + gantry_ctrl_clone.move_callback(coords); + + Ok(rosrust_msg::hw_srv::movegantryRes { status: true }) + }, + ) + .unwrap(); + + /* Create service */ + let gantry_ctrl_clone = gantry_ctrl.clone(); + let service_calibrate = rosrust::service::( + "/services/gantry/calibrate", + move |_| { + gantry_ctrl_clone.calibrate_callback(); + + Ok(rosrust_msg::hw_srv::calibrategantryRes { status: true }) + }, + ) + .unwrap(); while rosrust::is_ok() { /* Spin forever, we only execute things on callbacks from here */ diff --git a/mercury-app/src/hw_srv/srv/calibrate.srv b/mercury-app/src/hw_srv/srv/calibrate.srv deleted file mode 100644 index 57fcf58..0000000 --- a/mercury-app/src/hw_srv/srv/calibrate.srv +++ /dev/null @@ -1,2 +0,0 @@ -bool status ---- \ No newline at end of file diff --git a/mercury-app/src/hw_srv/srv/calibrategantry.srv b/mercury-app/src/hw_srv/srv/calibrategantry.srv new file mode 100644 index 0000000..e637707 --- /dev/null +++ b/mercury-app/src/hw_srv/srv/calibrategantry.srv @@ -0,0 +1,2 @@ +--- +bool status \ No newline at end of file diff --git a/mercury-app/src/hw_srv/srv/movegantry.srv b/mercury-app/src/hw_srv/srv/movegantry.srv new file mode 100644 index 0000000..ac9cf60 --- /dev/null +++ b/mercury-app/src/hw_srv/srv/movegantry.srv @@ -0,0 +1,5 @@ +float64 x +float64 y +float64 z +--- +bool status \ No newline at end of file From 33ecfe161a54c12b0765890599a72540006285b3 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Sat, 23 Mar 2024 22:52:18 -0400 Subject: [PATCH 4/9] Adding in model calls in callback --- mercury-app/src/hw_ifc/src/gantry_model.rs | 61 ++++++++++++++++------ mercury-app/src/hw_ifc/src/gantry_sub.rs | 33 ++++++++---- 2 files changed, 69 insertions(+), 25 deletions(-) diff --git a/mercury-app/src/hw_ifc/src/gantry_model.rs b/mercury-app/src/hw_ifc/src/gantry_model.rs index 64ec978..1483832 100644 --- a/mercury-app/src/hw_ifc/src/gantry_model.rs +++ b/mercury-app/src/hw_ifc/src/gantry_model.rs @@ -22,8 +22,8 @@ pub struct StepperCtrlCmdGroup { impl Index for StepperCtrlCmdGroup { type Output = StepperCtrlCmd; - fn index(&self, side: GantryAxes) -> &Self::Output { - match side { + fn index(&self, axis: GantryAxes) -> &Self::Output { + match axis { GantryAxes::X => &self.x, GantryAxes::Y => &self.y, GantryAxes::Z => &self.z, @@ -32,8 +32,8 @@ impl Index for StepperCtrlCmdGroup { } impl IndexMut for StepperCtrlCmdGroup { - fn index_mut(&mut self, side: GantryAxes) -> &mut Self::Output { - match side { + fn index_mut(&mut self, axis: GantryAxes) -> &mut Self::Output { + match axis { GantryAxes::X => &mut self.x, GantryAxes::Y => &mut self.y, GantryAxes::Z => &mut self.z, @@ -47,18 +47,48 @@ pub struct GantryPosition { z: f64, } +impl Index for GantryPosition { + type Output = f64; + + fn index(&self, axis: GantryAxes) -> &Self::Output { + match axis { + GantryAxes::X => &self.x, + GantryAxes::Y => &self.y, + GantryAxes::Z => &self.z, + } + } +} + +impl IndexMut for GantryPosition { + fn index_mut(&mut self, axis: GantryAxes) -> &mut Self::Output { + match axis { + GantryAxes::X => &mut self.x, + GantryAxes::Y => &mut self.y, + GantryAxes::Z => &mut self.z, + } + } +} + +impl GantryPosition { + pub fn new(x: f64, y: f64, z: f64) -> GantryPosition { + GantryPosition { x: x, y: y, z: z } + } +} + pub struct GantryModel { current_position: GantryPosition, + max_speed: f64, } impl GantryModel { - pub fn new() -> GantryModel { + pub fn new(max_speed: f64) -> GantryModel { GantryModel { current_position: GantryPosition { x: 0.0, y: 0.0, z: 0.0, }, + max_speed: max_speed, } } @@ -66,15 +96,14 @@ impl GantryModel { self.current_position = pos; } - pub fn calc_control_signals( - &mut self, - target_position: GantryPosition, - max_speed: f64, - ) -> StepperCtrlCmdGroup { + pub fn calc_control_signals(&mut self, target_position: GantryPosition) -> StepperCtrlCmdGroup { // assuming 1 unit = 1 step for simplicity - let x_steps = (target_position.x - self.current_position.x) as i32; - let y_steps = (target_position.y - self.current_position.y) as i32; - let z_steps = (target_position.z - self.current_position.z) as i32; + let x_steps = + (target_position[GantryAxes::X] - self.current_position[GantryAxes::X]) as i32; + let y_steps = + (target_position[GantryAxes::Y] - self.current_position[GantryAxes::Y]) as i32; + let z_steps = + (target_position[GantryAxes::Z] - self.current_position[GantryAxes::Z]) as i32; // Update current position self.current_position = target_position; @@ -82,15 +111,15 @@ impl GantryModel { StepperCtrlCmdGroup { x: StepperCtrlCmd { steps: x_steps, - speed: max_speed, + speed: self.max_speed, }, y: StepperCtrlCmd { steps: y_steps, - speed: max_speed, + speed: self.max_speed, }, z: StepperCtrlCmd { steps: z_steps, - speed: max_speed, + speed: self.max_speed, }, } } diff --git a/mercury-app/src/hw_ifc/src/gantry_sub.rs b/mercury-app/src/hw_ifc/src/gantry_sub.rs index c4f8bbc..62033b1 100644 --- a/mercury-app/src/hw_ifc/src/gantry_sub.rs +++ b/mercury-app/src/hw_ifc/src/gantry_sub.rs @@ -4,12 +4,14 @@ pub mod gantry_model; use self::gantry_model::{ GantryAxes, GantryModel, GantryPosition, StepperCtrlCmd, StepperCtrlCmdGroup, }; -use std::sync::Arc; +use std::sync::{Arc, Mutex}; pub mod msg { rosrust::rosmsg_include!(hw_srv / movegantry, hw_srv / calibrategantry); } +const MAX_SPEED: f64 = 10.0; /* meters/second */ + pub struct GantryController { model: GantryModel, } @@ -17,27 +19,39 @@ pub struct GantryController { impl GantryController { pub fn new() -> Self { GantryController { - model: GantryModel::new(), + model: GantryModel::new(MAX_SPEED), } } - pub fn move_callback(&self, data: rosrust_msg::hw_srv::movegantryReq) {} + pub fn move_callback(&mut self, data: rosrust_msg::hw_srv::movegantryReq) { + let stepper_cmds = self + .model + .calc_control_signals(GantryPosition::new(data.x, data.y, data.z)); + //stepper_cmds[GantryAxes::X]; + //stepper_cmds[GantryAxes::Y]; + //stepper_cmds[GantryAxes::Z]; + } - pub fn calibrate_callback(&self) {} + pub fn calibrate_callback(&mut self) { + let stepper_cmds = self + .model + .calc_control_signals(GantryPosition::new(0.0, 0.0, 0.0)); + } } fn main() { /* Initialize ROS node */ rosrust::init("gantry_sub"); - let gantry_ctrl = Arc::new(GantryController::new()); + let gantry_ctrl = Arc::new(Mutex::new(GantryController::new())); /* Create subscriber */ let gantry_ctrl_clone = gantry_ctrl.clone(); - let service_move = rosrust::service::( + let _service_move = rosrust::service::( "/gantry/pose/goal", move |coords: rosrust_msg::hw_srv::movegantryReq| { - gantry_ctrl_clone.move_callback(coords); + let mut gantry_ctrl = gantry_ctrl_clone.lock().unwrap(); + gantry_ctrl.move_callback(coords); Ok(rosrust_msg::hw_srv::movegantryRes { status: true }) }, @@ -46,10 +60,11 @@ fn main() { /* Create service */ let gantry_ctrl_clone = gantry_ctrl.clone(); - let service_calibrate = rosrust::service::( + let _service_calibrate = rosrust::service::( "/services/gantry/calibrate", move |_| { - gantry_ctrl_clone.calibrate_callback(); + let mut gantry_ctrl = gantry_ctrl_clone.lock().unwrap(); + gantry_ctrl.calibrate_callback(); Ok(rosrust_msg::hw_srv::calibrategantryRes { status: true }) }, From 0d0ed2fcb916a433d237ce7fb378dc453fe2ab78 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Sun, 24 Mar 2024 12:40:44 -0400 Subject: [PATCH 5/9] Finalizing HDL for steppers --- mercury-hdl/mercury_bd.tcl | 250 ++++++++++++---- mercury-hdl/mercury_proj.tcl | 499 +++++++++++++++++++++---------- mercury-hdl/stepper_pulse.v | 23 +- mercury-hdl/stepper_pulse_test.v | 64 ++++ 4 files changed, 612 insertions(+), 224 deletions(-) create mode 100644 mercury-hdl/stepper_pulse_test.v diff --git a/mercury-hdl/mercury_bd.tcl b/mercury-hdl/mercury_bd.tcl index ce72e07..d61a514 100644 --- a/mercury-hdl/mercury_bd.tcl +++ b/mercury-hdl/mercury_bd.tcl @@ -136,6 +136,7 @@ xilinx.com:ip:proc_sys_reset:5.0\ xilinx.com:ip:axi_timer:2.0\ xilinx.com:ip:axi_gpio:2.0\ xilinx.com:ip:xlslice:1.0\ +xilinx.com:ip:xlconstant:1.1\ " set list_ips_missing "" @@ -235,50 +236,114 @@ proc create_hier_cell_gantry { parentCell nameHier } { create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI3 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI4 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI5 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI6 + # Create pins create_bd_pin -dir I -type clk s_axi_aclk create_bd_pin -dir I -type rst s_axi_aresetn create_bd_pin -dir I step_clk - - # Create instance: axi_gpio_0, and set properties - set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + create_bd_pin -dir O -from 0 -to 0 -type data CONFIG_1 + create_bd_pin -dir O -from 0 -to 0 -type data DIR_1 + create_bd_pin -dir O -from 0 -to 0 -type data M0_1 + create_bd_pin -dir O -from 0 -to 0 -type data M1_1 + create_bd_pin -dir O -from 0 -to 0 -type data NENBL_1 + create_bd_pin -dir O -from 0 -to 0 -type data NSLEEP_1 + create_bd_pin -dir O -type data STEP_1 + create_bd_pin -dir O -from 0 -to 0 -type data CONFIG_2 + create_bd_pin -dir O -from 0 -to 0 -type data DIR_2 + create_bd_pin -dir O -from 0 -to 0 -type data M0_2 + create_bd_pin -dir O -from 0 -to 0 -type data M1_2 + create_bd_pin -dir O -from 0 -to 0 -type data NENBL_2 + create_bd_pin -dir O -from 0 -to 0 -type data NSLEEP_2 + create_bd_pin -dir O -type data STEP_2 + create_bd_pin -dir O -from 0 -to 0 -type data CONFIG_3 + create_bd_pin -dir O -from 0 -to 0 -type data DIR_3 + create_bd_pin -dir O -from 0 -to 0 -type data M0_3 + create_bd_pin -dir O -from 0 -to 0 -type data M1_3 + create_bd_pin -dir O -from 0 -to 0 -type data NENBL_3 + create_bd_pin -dir O -from 0 -to 0 -type data NSLEEP_3 + create_bd_pin -dir O -type data STEP_3 + + # Create instance: axi_gpio_step1, and set properties + set axi_gpio_step1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_step1 ] set_property -dict [list \ CONFIG.C_ALL_INPUTS_2 {1} \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_GPIO2_WIDTH {1} \ CONFIG.C_IS_DUAL {1} \ - ] $axi_gpio_0 + ] $axi_gpio_step1 - # Create instance: axi_gpio_1, and set properties - set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ] + # Create instance: axi_gpio_step2, and set properties + set axi_gpio_step2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_step2 ] set_property -dict [list \ CONFIG.C_ALL_INPUTS_2 {1} \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_GPIO2_WIDTH {1} \ CONFIG.C_IS_DUAL {1} \ - ] $axi_gpio_1 + ] $axi_gpio_step2 - # Create instance: axi_gpio_2, and set properties - set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] + # Create instance: axi_gpio_step3, and set properties + set axi_gpio_step3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_step3 ] set_property -dict [list \ CONFIG.C_ALL_INPUTS_2 {1} \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_GPIO2_WIDTH {1} \ CONFIG.C_IS_DUAL {1} \ - ] $axi_gpio_2 + ] $axi_gpio_step3 - # Create instance: axi_gpio_3, and set properties - set axi_gpio_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_3 ] + # Create instance: axi_gpio_rst, and set properties + set axi_gpio_rst [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_rst ] set_property -dict [list \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_DOUT_DEFAULT {0x00000001} \ CONFIG.C_GPIO_WIDTH {1} \ CONFIG.C_IS_DUAL {0} \ - ] $axi_gpio_3 + ] $axi_gpio_rst + + + # Create instance: xlconstant_gnd, and set properties + set xlconstant_gnd [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_gnd ] + set_property CONFIG.CONST_VAL {0} $xlconstant_gnd + + + # Create instance: xlconstant_vcc, and set properties + set xlconstant_vcc [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_vcc ] + set_property CONFIG.CONST_VAL {1} $xlconstant_vcc + + + # Create instance: axi_gpio_dir1, and set properties + set axi_gpio_dir1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_dir1 ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {1} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_dir1 + + + # Create instance: axi_gpio_dir2, and set properties + set axi_gpio_dir2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_dir2 ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {1} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_dir2 + + + # Create instance: axi_gpio_dir3, and set properties + set axi_gpio_dir3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_dir3 ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {1} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_dir3 # Create instance: stepper_pulse_0, and set properties @@ -315,22 +380,33 @@ proc create_hier_cell_gantry { parentCell nameHier } { } # Create interface connections - connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins S_AXI1] [get_bd_intf_pins axi_gpio_1/S_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins S_AXI2] [get_bd_intf_pins axi_gpio_2/S_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins S_AXI3] [get_bd_intf_pins axi_gpio_3/S_AXI] + connect_bd_intf_net -intf_net S_AXI4_1 [get_bd_intf_pins S_AXI4] [get_bd_intf_pins axi_gpio_dir1/S_AXI] + connect_bd_intf_net -intf_net S_AXI5_1 [get_bd_intf_pins S_AXI5] [get_bd_intf_pins axi_gpio_dir3/S_AXI] + connect_bd_intf_net -intf_net S_AXI6_1 [get_bd_intf_pins S_AXI6] [get_bd_intf_pins axi_gpio_dir2/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_gpio_step1/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins S_AXI1] [get_bd_intf_pins axi_gpio_step2/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins S_AXI2] [get_bd_intf_pins axi_gpio_step3/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins S_AXI3] [get_bd_intf_pins axi_gpio_rst/S_AXI] # Create port connections - connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins stepper_pulse_0/pulse_count] - connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins stepper_pulse_1/pulse_count] - connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_2/gpio_io_o] [get_bd_pins stepper_pulse_2/pulse_count] - connect_bd_net -net axi_gpio_3_gpio_io_o [get_bd_pins axi_gpio_3/gpio_io_o] [get_bd_pins stepper_pulse_0/rst_n] [get_bd_pins stepper_pulse_1/rst_n] [get_bd_pins stepper_pulse_2/rst_n] - connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] - connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_step1/gpio_io_o] [get_bd_pins stepper_pulse_0/pulse_count] + connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_step2/gpio_io_o] [get_bd_pins stepper_pulse_1/pulse_count] + connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_step3/gpio_io_o] [get_bd_pins stepper_pulse_2/pulse_count] + connect_bd_net -net axi_gpio_3_gpio_io_o [get_bd_pins axi_gpio_rst/gpio_io_o] [get_bd_pins stepper_pulse_0/rst_n] [get_bd_pins stepper_pulse_1/rst_n] [get_bd_pins stepper_pulse_2/rst_n] + connect_bd_net -net axi_gpio_4_gpio_io_o [get_bd_pins axi_gpio_dir1/gpio_io_o] [get_bd_pins DIR_1] + connect_bd_net -net axi_gpio_5_gpio_io_o [get_bd_pins axi_gpio_dir2/gpio_io_o] [get_bd_pins DIR_3] + connect_bd_net -net axi_gpio_6_gpio_io_o [get_bd_pins axi_gpio_dir3/gpio_io_o] [get_bd_pins DIR_2] + connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins s_axi_aresetn] [get_bd_pins axi_gpio_step2/s_axi_aresetn] [get_bd_pins axi_gpio_step3/s_axi_aresetn] [get_bd_pins axi_gpio_rst/s_axi_aresetn] [get_bd_pins axi_gpio_step1/s_axi_aresetn] [get_bd_pins axi_gpio_dir1/s_axi_aresetn] [get_bd_pins axi_gpio_dir2/s_axi_aresetn] [get_bd_pins axi_gpio_dir3/s_axi_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_gpio_rst/s_axi_aclk] [get_bd_pins axi_gpio_step3/s_axi_aclk] [get_bd_pins axi_gpio_step2/s_axi_aclk] [get_bd_pins axi_gpio_step1/s_axi_aclk] [get_bd_pins axi_gpio_dir1/s_axi_aclk] [get_bd_pins axi_gpio_dir2/s_axi_aclk] [get_bd_pins axi_gpio_dir3/s_axi_aclk] connect_bd_net -net step_clk_1 [get_bd_pins step_clk] [get_bd_pins stepper_pulse_0/clk] [get_bd_pins stepper_pulse_1/clk] [get_bd_pins stepper_pulse_2/clk] - connect_bd_net -net stepper_pulse_0_done [get_bd_pins stepper_pulse_0/done] [get_bd_pins axi_gpio_0/gpio2_io_i] - connect_bd_net -net stepper_pulse_1_done [get_bd_pins stepper_pulse_1/done] [get_bd_pins axi_gpio_1/gpio2_io_i] - connect_bd_net -net stepper_pulse_2_done [get_bd_pins stepper_pulse_2/done] [get_bd_pins axi_gpio_2/gpio2_io_i] + connect_bd_net -net stepper_pulse_0_done [get_bd_pins stepper_pulse_0/done] [get_bd_pins axi_gpio_step1/gpio2_io_i] + connect_bd_net -net stepper_pulse_0_pulse [get_bd_pins stepper_pulse_0/pulse] [get_bd_pins STEP_1] + connect_bd_net -net stepper_pulse_1_done [get_bd_pins stepper_pulse_1/done] [get_bd_pins axi_gpio_step2/gpio2_io_i] + connect_bd_net -net stepper_pulse_1_pulse [get_bd_pins stepper_pulse_1/pulse] [get_bd_pins STEP_2] + connect_bd_net -net stepper_pulse_2_done [get_bd_pins stepper_pulse_2/done] [get_bd_pins axi_gpio_step3/gpio2_io_i] + connect_bd_net -net stepper_pulse_2_pulse [get_bd_pins stepper_pulse_2/pulse] [get_bd_pins STEP_3] + connect_bd_net -net xlconstant_1_dout [get_bd_pins xlconstant_vcc/dout] [get_bd_pins NSLEEP_1] [get_bd_pins NSLEEP_2] [get_bd_pins NSLEEP_3] [get_bd_pins CONFIG_1] [get_bd_pins CONFIG_2] [get_bd_pins CONFIG_3] + connect_bd_net -net xlconstant_gnd_dout [get_bd_pins xlconstant_gnd/dout] [get_bd_pins M0_1] [get_bd_pins M0_3] [get_bd_pins M0_2] [get_bd_pins M1_1] [get_bd_pins M1_2] [get_bd_pins M1_3] [get_bd_pins NENBL_1] [get_bd_pins NENBL_2] [get_bd_pins NENBL_3] # Restore current instance current_bd_instance $oldCurInst @@ -392,50 +468,52 @@ proc create_hier_cell_drive { parentCell nameHier } { create_bd_pin -dir O -from 0 -to 0 Drive_DIR_1 create_bd_pin -dir O -from 0 -to 0 Drive_DIR_3 - # Create instance: axi_timer_0, and set properties - set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] + # Create instance: axi_timer_drv2, and set properties + set axi_timer_drv2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_drv2 ] - # Create instance: axi_timer_1, and set properties - set axi_timer_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_1 ] + # Create instance: axi_timer_drv1, and set properties + set axi_timer_drv1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_drv1 ] - # Create instance: axi_timer_2, and set properties - set axi_timer_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_2 ] + # Create instance: axi_timer_drv3, and set properties + set axi_timer_drv3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_drv3 ] - # Create instance: axi_timer_3, and set properties - set axi_timer_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_3 ] + # Create instance: axi_timer_drv4, and set properties + set axi_timer_drv4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_drv4 ] - # Create instance: axi_gpio_2, and set properties - set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] + # Create instance: axi_gpio_dir, and set properties + set axi_gpio_dir [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_dir ] set_property -dict [list \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_ALL_OUTPUTS_2 {1} \ CONFIG.C_DOUT_DEFAULT {0xFFFFFFFF} \ + CONFIG.C_GPIO2_WIDTH {1} \ + CONFIG.C_GPIO_WIDTH {1} \ CONFIG.C_IS_DUAL {1} \ - ] $axi_gpio_2 - + ] $axi_gpio_dir - # Create instance: xlslice_0, and set properties - set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] # Create instance: xlslice_1, and set properties set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] + # Create instance: xlslice_0, and set properties + set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] + # Create interface connections - connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axi_timer_1/S_AXI] [get_bd_intf_pins S_AXI] - connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_timer_2/S_AXI] [get_bd_intf_pins S_AXI1] - connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins axi_timer_3/S_AXI] [get_bd_intf_pins S_AXI2] - connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins S_AXI3] - connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins S_AXI4] + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axi_timer_drv1/S_AXI] [get_bd_intf_pins S_AXI] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_timer_drv3/S_AXI] [get_bd_intf_pins S_AXI1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins axi_timer_drv4/S_AXI] [get_bd_intf_pins S_AXI2] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins axi_gpio_dir/S_AXI] [get_bd_intf_pins S_AXI3] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins axi_timer_drv2/S_AXI] [get_bd_intf_pins S_AXI4] # Create port connections - connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins axi_gpio_2/gpio2_io_o] [get_bd_pins xlslice_1/Din] - connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_2/gpio_io_o] [get_bd_pins xlslice_0/Din] - connect_bd_net -net axi_timer_0_pwm0 [get_bd_pins axi_timer_0/pwm0] [get_bd_pins DAC_1_INA] - connect_bd_net -net axi_timer_1_pwm0 [get_bd_pins axi_timer_1/pwm0] [get_bd_pins DAC_1_INB] - connect_bd_net -net axi_timer_2_pwm0 [get_bd_pins axi_timer_2/pwm0] [get_bd_pins DAC_2_INA] - connect_bd_net -net axi_timer_3_pwm0 [get_bd_pins axi_timer_3/pwm0] [get_bd_pins DAC_2_INB] - connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_timer_1/s_axi_aclk] [get_bd_pins axi_timer_2/s_axi_aclk] [get_bd_pins axi_timer_3/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] - connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins axi_timer_1/s_axi_aresetn] [get_bd_pins axi_timer_3/s_axi_aresetn] [get_bd_pins axi_timer_2/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] + connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins axi_gpio_dir/gpio2_io_o] [get_bd_pins xlslice_1/Din] + connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_dir/gpio_io_o] [get_bd_pins xlslice_0/Din] + connect_bd_net -net axi_timer_0_pwm0 [get_bd_pins axi_timer_drv2/pwm0] [get_bd_pins DAC_1_INA] + connect_bd_net -net axi_timer_1_pwm0 [get_bd_pins axi_timer_drv1/pwm0] [get_bd_pins DAC_1_INB] + connect_bd_net -net axi_timer_2_pwm0 [get_bd_pins axi_timer_drv3/pwm0] [get_bd_pins DAC_2_INA] + connect_bd_net -net axi_timer_3_pwm0 [get_bd_pins axi_timer_drv4/pwm0] [get_bd_pins DAC_2_INB] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_timer_drv1/s_axi_aclk] [get_bd_pins axi_timer_drv3/s_axi_aclk] [get_bd_pins axi_timer_drv4/s_axi_aclk] [get_bd_pins axi_gpio_dir/s_axi_aclk] [get_bd_pins axi_timer_drv2/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins axi_timer_drv1/s_axi_aresetn] [get_bd_pins axi_timer_drv4/s_axi_aresetn] [get_bd_pins axi_timer_drv3/s_axi_aresetn] [get_bd_pins axi_gpio_dir/s_axi_aresetn] [get_bd_pins axi_timer_drv2/s_axi_aresetn] connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins Drive_DIR_1] connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins Drive_DIR_3] @@ -495,6 +573,27 @@ proc create_root_design { parentCell } { set_property -dict [ list \ CONFIG.POLARITY {ACTIVE_HIGH} \ ] $reset_rtl + set NENBL_1 [ create_bd_port -dir O -from 0 -to 0 -type data NENBL_1 ] + set STEP_1 [ create_bd_port -dir O -type data STEP_1 ] + set DIR_1 [ create_bd_port -dir O -from 0 -to 0 -type data DIR_1 ] + set M0_1 [ create_bd_port -dir O -from 0 -to 0 -type data M0_1 ] + set M1_1 [ create_bd_port -dir O -from 0 -to 0 -type data M1_1 ] + set CONFIG_1 [ create_bd_port -dir O -from 0 -to 0 -type data CONFIG_1 ] + set NSLEEP_1 [ create_bd_port -dir O -from 0 -to 0 -type data NSLEEP_1 ] + set CONFIG_2 [ create_bd_port -dir O -from 0 -to 0 -type data CONFIG_2 ] + set DIR_2 [ create_bd_port -dir O -from 0 -to 0 -type data DIR_2 ] + set M0_2 [ create_bd_port -dir O -from 0 -to 0 -type data M0_2 ] + set M1_2 [ create_bd_port -dir O -from 0 -to 0 -type data M1_2 ] + set NENBL_2 [ create_bd_port -dir O -from 0 -to 0 -type data NENBL_2 ] + set NSLEEP_2 [ create_bd_port -dir O -from 0 -to 0 -type data NSLEEP_2 ] + set STEP_2 [ create_bd_port -dir O -type data STEP_2 ] + set CONFIG_3 [ create_bd_port -dir O -from 0 -to 0 -type data CONFIG_3 ] + set DIR_3 [ create_bd_port -dir O -from 0 -to 0 -type data DIR_3 ] + set M0_3 [ create_bd_port -dir O -from 0 -to 0 -type data M0_3 ] + set M1_3 [ create_bd_port -dir O -from 0 -to 0 -type data M1_3 ] + set NENBL_3 [ create_bd_port -dir O -from 0 -to 0 -type data NENBL_3 ] + set NSLEEP_3 [ create_bd_port -dir O -from 0 -to 0 -type data NSLEEP_3 ] + set STEP_3 [ create_bd_port -dir O -type data STEP_3 ] # Create instance: processing_system7_0, and set properties set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] @@ -836,7 +935,7 @@ proc create_root_design { parentCell } { # Create instance: axi_interconnect_0, and set properties set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] set_property -dict [list \ - CONFIG.NUM_MI {10} \ + CONFIG.NUM_MI {12} \ CONFIG.NUM_SI {2} \ ] $axi_interconnect_0 @@ -857,6 +956,9 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins axi_interconnect_0/M06_AXI] [get_bd_intf_pins gantry/S_AXI1] connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins axi_interconnect_0/M07_AXI] [get_bd_intf_pins gantry/S_AXI2] connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_interconnect_0/M08_AXI] [get_bd_intf_pins gantry/S_AXI3] + connect_bd_intf_net -intf_net axi_interconnect_0_M09_AXI [get_bd_intf_pins axi_interconnect_0/M09_AXI] [get_bd_intf_pins gantry/S_AXI4] + connect_bd_intf_net -intf_net axi_interconnect_0_M10_AXI [get_bd_intf_pins axi_interconnect_0/M10_AXI] [get_bd_intf_pins gantry/S_AXI6] + connect_bd_intf_net -intf_net axi_interconnect_0_M11_AXI [get_bd_intf_pins axi_interconnect_0/M11_AXI] [get_bd_intf_pins gantry/S_AXI5] connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins axi_interconnect_0/S00_AXI] @@ -869,17 +971,51 @@ proc create_root_design { parentCell } { connect_bd_net -net drive_DAC_2_INA [get_bd_pins drive/DAC_2_INA] [get_bd_ports DAC_2_INA] connect_bd_net -net drive_Drive_DIR_1 [get_bd_pins drive/Drive_DIR_1] [get_bd_ports Drive_DIR_1] [get_bd_ports Drive_DIR_2] connect_bd_net -net drive_Drive_DIR_3 [get_bd_pins drive/Drive_DIR_3] [get_bd_ports Drive_DIR_3] [get_bd_ports Drive_DIR_4] - connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins drive/s_axi_aclk] [get_bd_pins gantry/s_axi_aclk] + connect_bd_net -net gantry_CONFIG_1 [get_bd_pins gantry/CONFIG_1] [get_bd_ports CONFIG_1] + connect_bd_net -net gantry_CONFIG_2 [get_bd_pins gantry/CONFIG_2] [get_bd_ports CONFIG_2] + connect_bd_net -net gantry_CONFIG_3 [get_bd_pins gantry/CONFIG_3] [get_bd_ports CONFIG_3] + connect_bd_net -net gantry_DIR_1 [get_bd_pins gantry/DIR_1] [get_bd_ports DIR_1] + connect_bd_net -net gantry_DIR_2 [get_bd_pins gantry/DIR_2] [get_bd_ports DIR_2] + connect_bd_net -net gantry_DIR_3 [get_bd_pins gantry/DIR_3] [get_bd_ports DIR_3] + connect_bd_net -net gantry_M0_1 [get_bd_pins gantry/M0_1] [get_bd_ports M0_1] + connect_bd_net -net gantry_M0_2 [get_bd_pins gantry/M0_2] [get_bd_ports M0_2] + connect_bd_net -net gantry_M0_3 [get_bd_pins gantry/M0_3] [get_bd_ports M0_3] + connect_bd_net -net gantry_M1_1 [get_bd_pins gantry/M1_1] [get_bd_ports M1_1] + connect_bd_net -net gantry_M1_2 [get_bd_pins gantry/M1_2] [get_bd_ports M1_2] + connect_bd_net -net gantry_M1_3 [get_bd_pins gantry/M1_3] [get_bd_ports M1_3] + connect_bd_net -net gantry_NENBL_1 [get_bd_pins gantry/NENBL_1] [get_bd_ports NENBL_1] + connect_bd_net -net gantry_NENBL_2 [get_bd_pins gantry/NENBL_2] [get_bd_ports NENBL_2] + connect_bd_net -net gantry_NENBL_3 [get_bd_pins gantry/NENBL_3] [get_bd_ports NENBL_3] + connect_bd_net -net gantry_NSLEEP_1 [get_bd_pins gantry/NSLEEP_1] [get_bd_ports NSLEEP_1] + connect_bd_net -net gantry_NSLEEP_2 [get_bd_pins gantry/NSLEEP_2] [get_bd_ports NSLEEP_2] + connect_bd_net -net gantry_NSLEEP_3 [get_bd_pins gantry/NSLEEP_3] [get_bd_ports NSLEEP_3] + connect_bd_net -net gantry_STEP_1 [get_bd_pins gantry/STEP_1] [get_bd_ports STEP_1] + connect_bd_net -net gantry_STEP_2 [get_bd_pins gantry/STEP_2] [get_bd_ports STEP_2] + connect_bd_net -net gantry_STEP_3 [get_bd_pins gantry/STEP_3] [get_bd_ports STEP_3] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins drive/s_axi_aclk] [get_bd_pins gantry/s_axi_aclk] [get_bd_pins axi_interconnect_0/M10_ACLK] [get_bd_pins axi_interconnect_0/M11_ACLK] connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in] - connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins drive/s_axi_aresetn] [get_bd_pins gantry/s_axi_aresetn] + connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins drive/s_axi_aresetn] [get_bd_pins gantry/s_axi_aresetn] [get_bd_pins axi_interconnect_0/M10_ARESETN] [get_bd_pins axi_interconnect_0/M11_ARESETN] connect_bd_net -net step_clk_1 [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins gantry/step_clk] # Create address segments + assign_bd_address -offset 0x41230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_step1/S_AXI/Reg] -force + assign_bd_address -offset 0x41240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_step2/S_AXI/Reg] -force + assign_bd_address -offset 0x41220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_gpio_dir/S_AXI/Reg] -force + assign_bd_address -offset 0x41250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_step3/S_AXI/Reg] -force + assign_bd_address -offset 0x41260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_rst/S_AXI/Reg] -force + assign_bd_address -dict [list offset 0x7FFF8000 range 0x00008000 offset 0x80000000 range 0x00008000] -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_dir1/S_AXI/Reg] -force + assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_dir2/S_AXI/Reg] -force + assign_bd_address -offset 0x41210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_dir3/S_AXI/Reg] -force + assign_bd_address -offset 0x42800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv2/S_AXI/Reg] -force + assign_bd_address -offset 0x42810000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv1/S_AXI/Reg] -force + assign_bd_address -offset 0x42820000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv3/S_AXI/Reg] -force + assign_bd_address -offset 0x42830000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv4/S_AXI/Reg] -force # Restore current instance current_bd_instance $oldCurInst + validate_bd_design save_bd_design } # End of create_root_design() @@ -892,5 +1028,3 @@ proc create_root_design { parentCell } { create_root_design "" -common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." - diff --git a/mercury-hdl/mercury_proj.tcl b/mercury-hdl/mercury_proj.tcl index dc0c5cb..86d1c0b 100644 --- a/mercury-hdl/mercury_proj.tcl +++ b/mercury-hdl/mercury_proj.tcl @@ -3,7 +3,7 @@ # # mercury_proj.tcl: Tcl script for re-creating project 'mercury' # -# Generated by Vivado on Thu Mar 21 13:29:40 EDT 2024 +# Generated by Vivado on Sun Mar 24 12:40:01 EDT 2024 # IP Build 3864474 on Sun May 7 20:36:21 MDT 2023 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -23,11 +23,13 @@ # 2. The following source(s) files that were local or imported into the original project. # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) # -# "/media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/mercury/mercury.srcs/sources_1/new/stepper_pulse.v" +# "/home/nwdepatie/mercury/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp" # # 3. The following remote source files that were added to the original project:- # +# "/media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/stepper_pulse.v" # "/media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/ZoM_Carrier_Constraints.xdc" +# "/media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/stepper_pulse_test.v" # #***************************************************************************************** @@ -35,7 +37,7 @@ proc checkRequiredFiles { origin_dir} { set status true set files [list \ - "[file normalize "$origin_dir/mercury/mercury.srcs/sources_1/new/stepper_pulse.v"]"\ + "[file normalize "$origin_dir/../../../../../../../home/nwdepatie/mercury/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp"]"\ ] foreach ifile $files { if { ![file isfile $ifile] } { @@ -45,7 +47,9 @@ proc checkRequiredFiles { origin_dir} { } set files [list \ + "[file normalize "$origin_dir/stepper_pulse.v"]"\ "[file normalize "$origin_dir/ZoM_Carrier_Constraints.xdc"]"\ + "[file normalize "$origin_dir/stepper_pulse_test.v"]"\ ] foreach ifile $files { if { ![file isfile $ifile] } { @@ -121,7 +125,7 @@ if { $::argc > 0 } { } # Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/mercury"]" +set orig_proj_dir "[file normalize "$origin_dir/../../../../../../../home/nwdepatie/mercury"]" # Check for paths and files needed for project creation set validate_required 0 @@ -205,6 +209,7 @@ set_property -name "source_mgmt_mode" -value "All" -objects $obj set_property -name "target_language" -value "Verilog" -objects $obj set_property -name "target_simulator" -value "XSim" -objects $obj set_property -name "tool_flow" -value "Vivado" -objects $obj +set_property -name "webtalk.xsim_launch_sim" -value "7" -objects $obj set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj set_property -name "xsim.array_display_limit" -value "1024" -objects $obj set_property -name "xsim.radix" -value "hex" -objects $obj @@ -218,17 +223,14 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { # Set 'sources_1' fileset object set obj [get_filesets sources_1] -# Import local files from the original project set files [list \ - [file normalize "${origin_dir}/mercury/mercury.srcs/sources_1/new/stepper_pulse.v" ]\ + [file normalize "${origin_dir}/stepper_pulse.v"] \ ] -set imported_files [import_files -fileset sources_1 $files] +add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files -# None - -# Set 'sources_1' fileset file properties for local files -set file "new/stepper_pulse.v" +set file "$origin_dir/stepper_pulse.v" +set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "file_type" -value "Verilog" -objects $file_obj set_property -name "is_enabled" -value "1" -objects $file_obj @@ -241,6 +243,9 @@ set_property -name "used_in_simulation" -value "1" -objects $file_obj set_property -name "used_in_synthesis" -value "1" -objects $file_obj +# Set 'sources_1' fileset file properties for local files +# None + # Set 'sources_1' fileset properties set obj [get_filesets sources_1] set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj @@ -299,7 +304,28 @@ if {[string equal [get_filesets -quiet sim_1] ""]} { # Set 'sim_1' fileset object set obj [get_filesets sim_1] -# Empty (no sources present) +set files [list \ + [file normalize "${origin_dir}/stepper_pulse_test.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sim_1' fileset file properties for remote files +set file "$origin_dir/stepper_pulse_test.v" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] +set_property -name "file_type" -value "Verilog" -objects $file_obj +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj +set_property -name "used_in_implementation" -value "1" -objects $file_obj +set_property -name "used_in_simulation" -value "1" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + + +# Set 'sim_1' fileset file properties for local files +# None # Set 'sim_1' fileset properties set obj [get_filesets sim_1] @@ -324,7 +350,7 @@ set_property -name "simmodel_value_check" -value "1" -objects $obj set_property -name "simulator_launch_mode" -value "off" -objects $obj set_property -name "source_set" -value "sources_1" -objects $obj set_property -name "systemc_include_dirs" -value "" -objects $obj -set_property -name "top" -value "mercury_wrapper" -objects $obj +set_property -name "top" -value "stepper_pulse_tb" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj set_property -name "transport_int_delay" -value "0" -objects $obj set_property -name "transport_path_delay" -value "0" -objects $obj @@ -371,7 +397,28 @@ set_property -name "xsim.simulate.xsim.more_options" -value "" -objects $obj # Set 'utils_1' fileset object set obj [get_filesets utils_1] -# Empty (no sources present) +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/../../../../../../../home/nwdepatie/mercury/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp" ]\ +] +set imported_files [import_files -fileset utils_1 $files] + +# Set 'utils_1' fileset file properties for remote files +# None + +# Set 'utils_1' fileset file properties for local files +set file "synth_1/mercury_wrapper.dcp" +set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]] +set_property -name "is_enabled" -value "1" -objects $file_obj +set_property -name "is_global_include" -value "0" -objects $file_obj +set_property -name "library" -value "xil_defaultlib" -objects $file_obj +set_property -name "netlist_only" -value "0" -objects $file_obj +set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj +set_property -name "scoped_to_cells" -value "" -objects $file_obj +set_property -name "used_in" -value "synthesis implementation" -objects $file_obj +set_property -name "used_in_implementation" -value "1" -objects $file_obj +set_property -name "used_in_synthesis" -value "1" -objects $file_obj + # Set 'utils_1' fileset properties set obj [get_filesets utils_1] @@ -380,13 +427,13 @@ set_property -name "name" -value "utils_1" -objects $obj # Adding sources referenced in BDs, if not already added if { [get_files stepper_pulse.v] == "" } { - import_files -quiet -fileset sources_1 /media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/mercury/mercury.srcs/sources_1/new/stepper_pulse.v + import_files -quiet -fileset sources_1 /media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/stepper_pulse.v } if { [get_files stepper_pulse.v] == "" } { - import_files -quiet -fileset sources_1 /media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/mercury/mercury.srcs/sources_1/new/stepper_pulse.v + import_files -quiet -fileset sources_1 /media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/stepper_pulse.v } if { [get_files stepper_pulse.v] == "" } { - import_files -quiet -fileset sources_1 /media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/mercury/mercury.srcs/sources_1/new/stepper_pulse.v + import_files -quiet -fileset sources_1 /media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/stepper_pulse.v } @@ -417,6 +464,7 @@ proc cr_bd_mercury { parentCell } { xilinx.com:ip:axi_timer:2.0\ xilinx.com:ip:axi_gpio:2.0\ xilinx.com:ip:xlslice:1.0\ + xilinx.com:ip:xlconstant:1.1\ " set list_ips_missing "" @@ -512,50 +560,114 @@ proc create_hier_cell_gantry { parentCell nameHier } { create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI3 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI4 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI5 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI6 + # Create pins create_bd_pin -dir I -type clk s_axi_aclk create_bd_pin -dir I -type rst s_axi_aresetn create_bd_pin -dir I step_clk - - # Create instance: axi_gpio_0, and set properties - set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + create_bd_pin -dir O -from 0 -to 0 -type data CONFIG_1 + create_bd_pin -dir O -from 0 -to 0 -type data DIR_1 + create_bd_pin -dir O -from 0 -to 0 -type data M0_1 + create_bd_pin -dir O -from 0 -to 0 -type data M1_1 + create_bd_pin -dir O -from 0 -to 0 -type data NENBL_1 + create_bd_pin -dir O -from 0 -to 0 -type data NSLEEP_1 + create_bd_pin -dir O -type data STEP_1 + create_bd_pin -dir O -from 0 -to 0 -type data CONFIG_2 + create_bd_pin -dir O -from 0 -to 0 -type data DIR_2 + create_bd_pin -dir O -from 0 -to 0 -type data M0_2 + create_bd_pin -dir O -from 0 -to 0 -type data M1_2 + create_bd_pin -dir O -from 0 -to 0 -type data NENBL_2 + create_bd_pin -dir O -from 0 -to 0 -type data NSLEEP_2 + create_bd_pin -dir O -type data STEP_2 + create_bd_pin -dir O -from 0 -to 0 -type data CONFIG_3 + create_bd_pin -dir O -from 0 -to 0 -type data DIR_3 + create_bd_pin -dir O -from 0 -to 0 -type data M0_3 + create_bd_pin -dir O -from 0 -to 0 -type data M1_3 + create_bd_pin -dir O -from 0 -to 0 -type data NENBL_3 + create_bd_pin -dir O -from 0 -to 0 -type data NSLEEP_3 + create_bd_pin -dir O -type data STEP_3 + + # Create instance: axi_gpio_step1, and set properties + set axi_gpio_step1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_step1 ] set_property -dict [list \ CONFIG.C_ALL_INPUTS_2 {1} \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_GPIO2_WIDTH {1} \ CONFIG.C_IS_DUAL {1} \ - ] $axi_gpio_0 + ] $axi_gpio_step1 - # Create instance: axi_gpio_1, and set properties - set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ] + # Create instance: axi_gpio_step2, and set properties + set axi_gpio_step2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_step2 ] set_property -dict [list \ CONFIG.C_ALL_INPUTS_2 {1} \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_GPIO2_WIDTH {1} \ CONFIG.C_IS_DUAL {1} \ - ] $axi_gpio_1 + ] $axi_gpio_step2 - # Create instance: axi_gpio_2, and set properties - set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] + # Create instance: axi_gpio_step3, and set properties + set axi_gpio_step3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_step3 ] set_property -dict [list \ CONFIG.C_ALL_INPUTS_2 {1} \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_GPIO2_WIDTH {1} \ CONFIG.C_IS_DUAL {1} \ - ] $axi_gpio_2 + ] $axi_gpio_step3 - # Create instance: axi_gpio_3, and set properties - set axi_gpio_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_3 ] + # Create instance: axi_gpio_rst, and set properties + set axi_gpio_rst [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_rst ] set_property -dict [list \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_DOUT_DEFAULT {0x00000001} \ CONFIG.C_GPIO_WIDTH {1} \ CONFIG.C_IS_DUAL {0} \ - ] $axi_gpio_3 + ] $axi_gpio_rst + + + # Create instance: xlconstant_gnd, and set properties + set xlconstant_gnd [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_gnd ] + set_property CONFIG.CONST_VAL {0} $xlconstant_gnd + + + # Create instance: xlconstant_vcc, and set properties + set xlconstant_vcc [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_vcc ] + set_property CONFIG.CONST_VAL {1} $xlconstant_vcc + + + # Create instance: axi_gpio_dir1, and set properties + set axi_gpio_dir1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_dir1 ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {1} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_dir1 + + + # Create instance: axi_gpio_dir2, and set properties + set axi_gpio_dir2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_dir2 ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {1} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_dir2 + + + # Create instance: axi_gpio_dir3, and set properties + set axi_gpio_dir3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_dir3 ] + set_property -dict [list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {1} \ + CONFIG.C_IS_DUAL {0} \ + ] $axi_gpio_dir3 # Create instance: stepper_pulse_0, and set properties @@ -592,63 +704,33 @@ proc create_hier_cell_gantry { parentCell nameHier } { } # Create interface connections - connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins S_AXI1] [get_bd_intf_pins axi_gpio_1/S_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins S_AXI2] [get_bd_intf_pins axi_gpio_2/S_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins S_AXI3] [get_bd_intf_pins axi_gpio_3/S_AXI] + connect_bd_intf_net -intf_net S_AXI4_1 [get_bd_intf_pins S_AXI4] [get_bd_intf_pins axi_gpio_dir1/S_AXI] + connect_bd_intf_net -intf_net S_AXI5_1 [get_bd_intf_pins S_AXI5] [get_bd_intf_pins axi_gpio_dir3/S_AXI] + connect_bd_intf_net -intf_net S_AXI6_1 [get_bd_intf_pins S_AXI6] [get_bd_intf_pins axi_gpio_dir2/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_gpio_step1/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins S_AXI1] [get_bd_intf_pins axi_gpio_step2/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins S_AXI2] [get_bd_intf_pins axi_gpio_step3/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins S_AXI3] [get_bd_intf_pins axi_gpio_rst/S_AXI] # Create port connections - connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins stepper_pulse_0/pulse_count] - connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins stepper_pulse_1/pulse_count] - connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_2/gpio_io_o] [get_bd_pins stepper_pulse_2/pulse_count] - connect_bd_net -net axi_gpio_3_gpio_io_o [get_bd_pins axi_gpio_3/gpio_io_o] [get_bd_pins stepper_pulse_0/rst_n] [get_bd_pins stepper_pulse_1/rst_n] [get_bd_pins stepper_pulse_2/rst_n] - connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_gpio_3/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] - connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_gpio_3/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_step1/gpio_io_o] [get_bd_pins stepper_pulse_0/pulse_count] + connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_step2/gpio_io_o] [get_bd_pins stepper_pulse_1/pulse_count] + connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_step3/gpio_io_o] [get_bd_pins stepper_pulse_2/pulse_count] + connect_bd_net -net axi_gpio_3_gpio_io_o [get_bd_pins axi_gpio_rst/gpio_io_o] [get_bd_pins stepper_pulse_0/rst_n] [get_bd_pins stepper_pulse_1/rst_n] [get_bd_pins stepper_pulse_2/rst_n] + connect_bd_net -net axi_gpio_4_gpio_io_o [get_bd_pins axi_gpio_dir1/gpio_io_o] [get_bd_pins DIR_1] + connect_bd_net -net axi_gpio_5_gpio_io_o [get_bd_pins axi_gpio_dir2/gpio_io_o] [get_bd_pins DIR_3] + connect_bd_net -net axi_gpio_6_gpio_io_o [get_bd_pins axi_gpio_dir3/gpio_io_o] [get_bd_pins DIR_2] + connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins s_axi_aresetn] [get_bd_pins axi_gpio_step2/s_axi_aresetn] [get_bd_pins axi_gpio_step3/s_axi_aresetn] [get_bd_pins axi_gpio_rst/s_axi_aresetn] [get_bd_pins axi_gpio_step1/s_axi_aresetn] [get_bd_pins axi_gpio_dir1/s_axi_aresetn] [get_bd_pins axi_gpio_dir2/s_axi_aresetn] [get_bd_pins axi_gpio_dir3/s_axi_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_gpio_rst/s_axi_aclk] [get_bd_pins axi_gpio_step3/s_axi_aclk] [get_bd_pins axi_gpio_step2/s_axi_aclk] [get_bd_pins axi_gpio_step1/s_axi_aclk] [get_bd_pins axi_gpio_dir1/s_axi_aclk] [get_bd_pins axi_gpio_dir2/s_axi_aclk] [get_bd_pins axi_gpio_dir3/s_axi_aclk] connect_bd_net -net step_clk_1 [get_bd_pins step_clk] [get_bd_pins stepper_pulse_0/clk] [get_bd_pins stepper_pulse_1/clk] [get_bd_pins stepper_pulse_2/clk] - connect_bd_net -net stepper_pulse_0_done [get_bd_pins stepper_pulse_0/done] [get_bd_pins axi_gpio_0/gpio2_io_i] - connect_bd_net -net stepper_pulse_1_done [get_bd_pins stepper_pulse_1/done] [get_bd_pins axi_gpio_1/gpio2_io_i] - connect_bd_net -net stepper_pulse_2_done [get_bd_pins stepper_pulse_2/done] [get_bd_pins axi_gpio_2/gpio2_io_i] - - # Perform GUI Layout - regenerate_bd_layout -hierarchy [get_bd_cells /gantry] -layout_string { - "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"0.808605", - "Default View_TopLeft":"-481,1", - "ExpandedHierarchyInLayout":"", - "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS -# -string -flagsOSRD -preplace port S_AXI -pg 1 -lvl 0 -x 0 -y 90 -defaultsOSRD -preplace port S_AXI1 -pg 1 -lvl 0 -x 0 -y 250 -defaultsOSRD -preplace port S_AXI2 -pg 1 -lvl 0 -x 0 -y 410 -defaultsOSRD -preplace port S_AXI3 -pg 1 -lvl 0 -x 0 -y 580 -defaultsOSRD -preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y 430 -defaultsOSRD -preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y 450 -defaultsOSRD -preplace port port-id_step_clk -pg 1 -lvl 0 -x 0 -y 520 -defaultsOSRD -preplace inst axi_gpio_0 -pg 1 -lvl 1 -x 180 -y 110 -defaultsOSRD -preplace inst axi_gpio_1 -pg 1 -lvl 1 -x 180 -y 270 -defaultsOSRD -preplace inst axi_gpio_2 -pg 1 -lvl 1 -x 180 -y 430 -defaultsOSRD -preplace inst axi_gpio_3 -pg 1 -lvl 1 -x 180 -y 600 -defaultsOSRD -preplace inst stepper_pulse_0 -pg 1 -lvl 2 -x 510 -y 80 -defaultsOSRD -preplace inst stepper_pulse_1 -pg 1 -lvl 2 -x 510 -y 240 -defaultsOSRD -preplace inst stepper_pulse_2 -pg 1 -lvl 2 -x 510 -y 400 -defaultsOSRD -preplace netloc axi_gpio_0_gpio_io_o 1 1 1 N 100 -preplace netloc axi_gpio_1_gpio_io_o 1 1 1 N 260 -preplace netloc axi_gpio_2_gpio_io_o 1 1 1 N 420 -preplace netloc axi_gpio_3_gpio_io_o 1 1 1 360 80n -preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 1 30 130n -preplace netloc stepper_pulse_0_done 1 1 2 370 160 650 -preplace netloc stepper_pulse_1_done 1 1 2 350 320 650 -preplace netloc stepper_pulse_2_done 1 1 2 330 480 650 -preplace netloc s_axi_aclk_1 1 0 1 20 110n -preplace netloc step_clk_1 1 0 2 NJ 520 340 -preplace netloc axi_interconnect_0_M05_AXI 1 0 1 NJ 90 -preplace netloc axi_interconnect_0_M06_AXI 1 0 1 NJ 250 -preplace netloc axi_interconnect_0_M07_AXI 1 0 1 NJ 410 -preplace netloc axi_interconnect_0_M08_AXI 1 0 1 NJ 580 -levelinfo -pg 1 0 180 510 670 -pagesize -pg 1 -db -bbox -sgen -150 0 670 680 -" -} + connect_bd_net -net stepper_pulse_0_done [get_bd_pins stepper_pulse_0/done] [get_bd_pins axi_gpio_step1/gpio2_io_i] + connect_bd_net -net stepper_pulse_0_pulse [get_bd_pins stepper_pulse_0/pulse] [get_bd_pins STEP_1] + connect_bd_net -net stepper_pulse_1_done [get_bd_pins stepper_pulse_1/done] [get_bd_pins axi_gpio_step2/gpio2_io_i] + connect_bd_net -net stepper_pulse_1_pulse [get_bd_pins stepper_pulse_1/pulse] [get_bd_pins STEP_2] + connect_bd_net -net stepper_pulse_2_done [get_bd_pins stepper_pulse_2/done] [get_bd_pins axi_gpio_step3/gpio2_io_i] + connect_bd_net -net stepper_pulse_2_pulse [get_bd_pins stepper_pulse_2/pulse] [get_bd_pins STEP_3] + connect_bd_net -net xlconstant_1_dout [get_bd_pins xlconstant_vcc/dout] [get_bd_pins NSLEEP_1] [get_bd_pins NSLEEP_2] [get_bd_pins NSLEEP_3] [get_bd_pins CONFIG_1] [get_bd_pins CONFIG_2] [get_bd_pins CONFIG_3] + connect_bd_net -net xlconstant_gnd_dout [get_bd_pins xlconstant_gnd/dout] [get_bd_pins M0_1] [get_bd_pins M0_3] [get_bd_pins M0_2] [get_bd_pins M1_1] [get_bd_pins M1_2] [get_bd_pins M1_3] [get_bd_pins NENBL_1] [get_bd_pins NENBL_2] [get_bd_pins NENBL_3] # Restore current instance current_bd_instance $oldCurInst @@ -710,50 +792,52 @@ proc create_hier_cell_drive { parentCell nameHier } { create_bd_pin -dir O -from 0 -to 0 Drive_DIR_1 create_bd_pin -dir O -from 0 -to 0 Drive_DIR_3 - # Create instance: axi_timer_0, and set properties - set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] + # Create instance: axi_timer_drv2, and set properties + set axi_timer_drv2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_drv2 ] - # Create instance: axi_timer_1, and set properties - set axi_timer_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_1 ] + # Create instance: axi_timer_drv1, and set properties + set axi_timer_drv1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_drv1 ] - # Create instance: axi_timer_2, and set properties - set axi_timer_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_2 ] + # Create instance: axi_timer_drv3, and set properties + set axi_timer_drv3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_drv3 ] - # Create instance: axi_timer_3, and set properties - set axi_timer_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_3 ] + # Create instance: axi_timer_drv4, and set properties + set axi_timer_drv4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_drv4 ] - # Create instance: axi_gpio_2, and set properties - set axi_gpio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2 ] + # Create instance: axi_gpio_dir, and set properties + set axi_gpio_dir [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_dir ] set_property -dict [list \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_ALL_OUTPUTS_2 {1} \ CONFIG.C_DOUT_DEFAULT {0xFFFFFFFF} \ + CONFIG.C_GPIO2_WIDTH {1} \ + CONFIG.C_GPIO_WIDTH {1} \ CONFIG.C_IS_DUAL {1} \ - ] $axi_gpio_2 - + ] $axi_gpio_dir - # Create instance: xlslice_0, and set properties - set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] # Create instance: xlslice_1, and set properties set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] + # Create instance: xlslice_0, and set properties + set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] + # Create interface connections - connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axi_timer_1/S_AXI] [get_bd_intf_pins S_AXI] - connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_timer_2/S_AXI] [get_bd_intf_pins S_AXI1] - connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins axi_timer_3/S_AXI] [get_bd_intf_pins S_AXI2] - connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins axi_gpio_2/S_AXI] [get_bd_intf_pins S_AXI3] - connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins S_AXI4] + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axi_timer_drv1/S_AXI] [get_bd_intf_pins S_AXI] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_timer_drv3/S_AXI] [get_bd_intf_pins S_AXI1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins axi_timer_drv4/S_AXI] [get_bd_intf_pins S_AXI2] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins axi_gpio_dir/S_AXI] [get_bd_intf_pins S_AXI3] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins axi_timer_drv2/S_AXI] [get_bd_intf_pins S_AXI4] # Create port connections - connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins axi_gpio_2/gpio2_io_o] [get_bd_pins xlslice_1/Din] - connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_2/gpio_io_o] [get_bd_pins xlslice_0/Din] - connect_bd_net -net axi_timer_0_pwm0 [get_bd_pins axi_timer_0/pwm0] [get_bd_pins DAC_1_INA] - connect_bd_net -net axi_timer_1_pwm0 [get_bd_pins axi_timer_1/pwm0] [get_bd_pins DAC_1_INB] - connect_bd_net -net axi_timer_2_pwm0 [get_bd_pins axi_timer_2/pwm0] [get_bd_pins DAC_2_INA] - connect_bd_net -net axi_timer_3_pwm0 [get_bd_pins axi_timer_3/pwm0] [get_bd_pins DAC_2_INB] - connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_timer_1/s_axi_aclk] [get_bd_pins axi_timer_2/s_axi_aclk] [get_bd_pins axi_timer_3/s_axi_aclk] [get_bd_pins axi_gpio_2/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] - connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins axi_timer_1/s_axi_aresetn] [get_bd_pins axi_timer_3/s_axi_aresetn] [get_bd_pins axi_timer_2/s_axi_aresetn] [get_bd_pins axi_gpio_2/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] + connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins axi_gpio_dir/gpio2_io_o] [get_bd_pins xlslice_1/Din] + connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_dir/gpio_io_o] [get_bd_pins xlslice_0/Din] + connect_bd_net -net axi_timer_0_pwm0 [get_bd_pins axi_timer_drv2/pwm0] [get_bd_pins DAC_1_INA] + connect_bd_net -net axi_timer_1_pwm0 [get_bd_pins axi_timer_drv1/pwm0] [get_bd_pins DAC_1_INB] + connect_bd_net -net axi_timer_2_pwm0 [get_bd_pins axi_timer_drv3/pwm0] [get_bd_pins DAC_2_INA] + connect_bd_net -net axi_timer_3_pwm0 [get_bd_pins axi_timer_drv4/pwm0] [get_bd_pins DAC_2_INB] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_timer_drv1/s_axi_aclk] [get_bd_pins axi_timer_drv3/s_axi_aclk] [get_bd_pins axi_timer_drv4/s_axi_aclk] [get_bd_pins axi_gpio_dir/s_axi_aclk] [get_bd_pins axi_timer_drv2/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins axi_timer_drv1/s_axi_aresetn] [get_bd_pins axi_timer_drv4/s_axi_aresetn] [get_bd_pins axi_timer_drv3/s_axi_aresetn] [get_bd_pins axi_gpio_dir/s_axi_aresetn] [get_bd_pins axi_timer_drv2/s_axi_aresetn] connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins Drive_DIR_1] connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins Drive_DIR_3] @@ -806,6 +890,27 @@ proc create_hier_cell_drive { parentCell nameHier } { set_property -dict [ list \ CONFIG.POLARITY {ACTIVE_HIGH} \ ] $reset_rtl + set NENBL_1 [ create_bd_port -dir O -from 0 -to 0 -type data NENBL_1 ] + set STEP_1 [ create_bd_port -dir O -type data STEP_1 ] + set DIR_1 [ create_bd_port -dir O -from 0 -to 0 -type data DIR_1 ] + set M0_1 [ create_bd_port -dir O -from 0 -to 0 -type data M0_1 ] + set M1_1 [ create_bd_port -dir O -from 0 -to 0 -type data M1_1 ] + set CONFIG_1 [ create_bd_port -dir O -from 0 -to 0 -type data CONFIG_1 ] + set NSLEEP_1 [ create_bd_port -dir O -from 0 -to 0 -type data NSLEEP_1 ] + set CONFIG_2 [ create_bd_port -dir O -from 0 -to 0 -type data CONFIG_2 ] + set DIR_2 [ create_bd_port -dir O -from 0 -to 0 -type data DIR_2 ] + set M0_2 [ create_bd_port -dir O -from 0 -to 0 -type data M0_2 ] + set M1_2 [ create_bd_port -dir O -from 0 -to 0 -type data M1_2 ] + set NENBL_2 [ create_bd_port -dir O -from 0 -to 0 -type data NENBL_2 ] + set NSLEEP_2 [ create_bd_port -dir O -from 0 -to 0 -type data NSLEEP_2 ] + set STEP_2 [ create_bd_port -dir O -type data STEP_2 ] + set CONFIG_3 [ create_bd_port -dir O -from 0 -to 0 -type data CONFIG_3 ] + set DIR_3 [ create_bd_port -dir O -from 0 -to 0 -type data DIR_3 ] + set M0_3 [ create_bd_port -dir O -from 0 -to 0 -type data M0_3 ] + set M1_3 [ create_bd_port -dir O -from 0 -to 0 -type data M1_3 ] + set NENBL_3 [ create_bd_port -dir O -from 0 -to 0 -type data NENBL_3 ] + set NSLEEP_3 [ create_bd_port -dir O -from 0 -to 0 -type data NSLEEP_3 ] + set STEP_3 [ create_bd_port -dir O -type data STEP_3 ] # Create instance: processing_system7_0, and set properties set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] @@ -1147,7 +1252,7 @@ proc create_hier_cell_drive { parentCell nameHier } { # Create instance: axi_interconnect_0, and set properties set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] set_property -dict [list \ - CONFIG.NUM_MI {10} \ + CONFIG.NUM_MI {12} \ CONFIG.NUM_SI {2} \ ] $axi_interconnect_0 @@ -1168,6 +1273,9 @@ proc create_hier_cell_drive { parentCell nameHier } { connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins axi_interconnect_0/M06_AXI] [get_bd_intf_pins gantry/S_AXI1] connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_pins axi_interconnect_0/M07_AXI] [get_bd_intf_pins gantry/S_AXI2] connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_interconnect_0/M08_AXI] [get_bd_intf_pins gantry/S_AXI3] + connect_bd_intf_net -intf_net axi_interconnect_0_M09_AXI [get_bd_intf_pins axi_interconnect_0/M09_AXI] [get_bd_intf_pins gantry/S_AXI4] + connect_bd_intf_net -intf_net axi_interconnect_0_M10_AXI [get_bd_intf_pins axi_interconnect_0/M10_AXI] [get_bd_intf_pins gantry/S_AXI6] + connect_bd_intf_net -intf_net axi_interconnect_0_M11_AXI [get_bd_intf_pins axi_interconnect_0/M11_AXI] [get_bd_intf_pins gantry/S_AXI5] connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins axi_interconnect_0/S00_AXI] @@ -1180,71 +1288,148 @@ proc create_hier_cell_drive { parentCell nameHier } { connect_bd_net -net drive_DAC_2_INA [get_bd_pins drive/DAC_2_INA] [get_bd_ports DAC_2_INA] connect_bd_net -net drive_Drive_DIR_1 [get_bd_pins drive/Drive_DIR_1] [get_bd_ports Drive_DIR_1] [get_bd_ports Drive_DIR_2] connect_bd_net -net drive_Drive_DIR_3 [get_bd_pins drive/Drive_DIR_3] [get_bd_ports Drive_DIR_3] [get_bd_ports Drive_DIR_4] - connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins drive/s_axi_aclk] [get_bd_pins gantry/s_axi_aclk] + connect_bd_net -net gantry_CONFIG_1 [get_bd_pins gantry/CONFIG_1] [get_bd_ports CONFIG_1] + connect_bd_net -net gantry_CONFIG_2 [get_bd_pins gantry/CONFIG_2] [get_bd_ports CONFIG_2] + connect_bd_net -net gantry_CONFIG_3 [get_bd_pins gantry/CONFIG_3] [get_bd_ports CONFIG_3] + connect_bd_net -net gantry_DIR_1 [get_bd_pins gantry/DIR_1] [get_bd_ports DIR_1] + connect_bd_net -net gantry_DIR_2 [get_bd_pins gantry/DIR_2] [get_bd_ports DIR_2] + connect_bd_net -net gantry_DIR_3 [get_bd_pins gantry/DIR_3] [get_bd_ports DIR_3] + connect_bd_net -net gantry_M0_1 [get_bd_pins gantry/M0_1] [get_bd_ports M0_1] + connect_bd_net -net gantry_M0_2 [get_bd_pins gantry/M0_2] [get_bd_ports M0_2] + connect_bd_net -net gantry_M0_3 [get_bd_pins gantry/M0_3] [get_bd_ports M0_3] + connect_bd_net -net gantry_M1_1 [get_bd_pins gantry/M1_1] [get_bd_ports M1_1] + connect_bd_net -net gantry_M1_2 [get_bd_pins gantry/M1_2] [get_bd_ports M1_2] + connect_bd_net -net gantry_M1_3 [get_bd_pins gantry/M1_3] [get_bd_ports M1_3] + connect_bd_net -net gantry_NENBL_1 [get_bd_pins gantry/NENBL_1] [get_bd_ports NENBL_1] + connect_bd_net -net gantry_NENBL_2 [get_bd_pins gantry/NENBL_2] [get_bd_ports NENBL_2] + connect_bd_net -net gantry_NENBL_3 [get_bd_pins gantry/NENBL_3] [get_bd_ports NENBL_3] + connect_bd_net -net gantry_NSLEEP_1 [get_bd_pins gantry/NSLEEP_1] [get_bd_ports NSLEEP_1] + connect_bd_net -net gantry_NSLEEP_2 [get_bd_pins gantry/NSLEEP_2] [get_bd_ports NSLEEP_2] + connect_bd_net -net gantry_NSLEEP_3 [get_bd_pins gantry/NSLEEP_3] [get_bd_ports NSLEEP_3] + connect_bd_net -net gantry_STEP_1 [get_bd_pins gantry/STEP_1] [get_bd_ports STEP_1] + connect_bd_net -net gantry_STEP_2 [get_bd_pins gantry/STEP_2] [get_bd_ports STEP_2] + connect_bd_net -net gantry_STEP_3 [get_bd_pins gantry/STEP_3] [get_bd_ports STEP_3] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins drive/s_axi_aclk] [get_bd_pins gantry/s_axi_aclk] [get_bd_pins axi_interconnect_0/M10_ACLK] [get_bd_pins axi_interconnect_0/M11_ACLK] connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in] - connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins drive/s_axi_aresetn] [get_bd_pins gantry/s_axi_aresetn] + connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins drive/s_axi_aresetn] [get_bd_pins gantry/s_axi_aresetn] [get_bd_pins axi_interconnect_0/M10_ARESETN] [get_bd_pins axi_interconnect_0/M11_ARESETN] connect_bd_net -net step_clk_1 [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins gantry/step_clk] # Create address segments + assign_bd_address -offset 0x41230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_step1/S_AXI/Reg] -force + assign_bd_address -offset 0x41240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_step2/S_AXI/Reg] -force + assign_bd_address -offset 0x41220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_gpio_dir/S_AXI/Reg] -force + assign_bd_address -offset 0x41250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_step3/S_AXI/Reg] -force + assign_bd_address -offset 0x41260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_rst/S_AXI/Reg] -force + assign_bd_address -dict [list offset 0x7FFF8000 range 0x00008000 offset 0x80000000 range 0x00008000] -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_dir1/S_AXI/Reg] -force + assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_dir2/S_AXI/Reg] -force + assign_bd_address -offset 0x41210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_dir3/S_AXI/Reg] -force + assign_bd_address -offset 0x42800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv2/S_AXI/Reg] -force + assign_bd_address -offset 0x42810000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv1/S_AXI/Reg] -force + assign_bd_address -offset 0x42820000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv3/S_AXI/Reg] -force + assign_bd_address -offset 0x42830000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv4/S_AXI/Reg] -force # Perform GUI Layout regenerate_bd_layout -layout_string { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"0.718997", - "Default View_TopLeft":"-213,1", + "Default View_ScaleFactor":"0.797945", + "Default View_TopLeft":"-108,-4", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS # -string -flagsOSRD -preplace port DDR -pg 1 -lvl 4 -x 1170 -y 60 -defaultsOSRD -preplace port FIXED_IO -pg 1 -lvl 4 -x 1170 -y 80 -defaultsOSRD -preplace port port-id_DAC_1_INA -pg 1 -lvl 4 -x 1170 -y 330 -defaultsOSRD -preplace port port-id_DAC_1_INB -pg 1 -lvl 4 -x 1170 -y 350 -defaultsOSRD -preplace port port-id_DAC_2_INA -pg 1 -lvl 4 -x 1170 -y 370 -defaultsOSRD -preplace port port-id_DAC_2_INB -pg 1 -lvl 4 -x 1170 -y 390 -defaultsOSRD +preplace port DDR -pg 1 -lvl 4 -x 1180 -y 60 -defaultsOSRD +preplace port FIXED_IO -pg 1 -lvl 4 -x 1180 -y 80 -defaultsOSRD +preplace port port-id_DAC_1_INA -pg 1 -lvl 4 -x 1180 -y 160 -defaultsOSRD +preplace port port-id_DAC_1_INB -pg 1 -lvl 4 -x 1180 -y 180 -defaultsOSRD +preplace port port-id_DAC_2_INA -pg 1 -lvl 4 -x 1180 -y 200 -defaultsOSRD +preplace port port-id_DAC_2_INB -pg 1 -lvl 4 -x 1180 -y 220 -defaultsOSRD preplace port port-id_reset_rtl -pg 1 -lvl 0 -x 0 -y 20 -defaultsOSRD -preplace portBus Drive_DIR_1 -pg 1 -lvl 4 -x 1170 -y 410 -defaultsOSRD -preplace portBus Drive_DIR_2 -pg 1 -lvl 4 -x 1170 -y 430 -defaultsOSRD -preplace portBus Drive_DIR_3 -pg 1 -lvl 4 -x 1170 -y 450 -defaultsOSRD -preplace portBus Drive_DIR_4 -pg 1 -lvl 4 -x 1170 -y 470 -defaultsOSRD +preplace port port-id_STEP_1 -pg 1 -lvl 4 -x 1180 -y 480 -defaultsOSRD +preplace port port-id_STEP_2 -pg 1 -lvl 4 -x 1180 -y 620 -defaultsOSRD +preplace port port-id_STEP_3 -pg 1 -lvl 4 -x 1180 -y 760 -defaultsOSRD +preplace portBus Drive_DIR_1 -pg 1 -lvl 4 -x 1180 -y 240 -defaultsOSRD +preplace portBus Drive_DIR_2 -pg 1 -lvl 4 -x 1180 -y 260 -defaultsOSRD +preplace portBus Drive_DIR_3 -pg 1 -lvl 4 -x 1180 -y 280 -defaultsOSRD +preplace portBus Drive_DIR_4 -pg 1 -lvl 4 -x 1180 -y 300 -defaultsOSRD +preplace portBus NENBL_1 -pg 1 -lvl 4 -x 1180 -y 440 -defaultsOSRD +preplace portBus DIR_1 -pg 1 -lvl 4 -x 1180 -y 380 -defaultsOSRD +preplace portBus M0_1 -pg 1 -lvl 4 -x 1180 -y 400 -defaultsOSRD +preplace portBus M1_1 -pg 1 -lvl 4 -x 1180 -y 420 -defaultsOSRD +preplace portBus CONFIG_1 -pg 1 -lvl 4 -x 1180 -y 360 -defaultsOSRD +preplace portBus NSLEEP_1 -pg 1 -lvl 4 -x 1180 -y 460 -defaultsOSRD +preplace portBus CONFIG_2 -pg 1 -lvl 4 -x 1180 -y 500 -defaultsOSRD +preplace portBus DIR_2 -pg 1 -lvl 4 -x 1180 -y 520 -defaultsOSRD +preplace portBus M0_2 -pg 1 -lvl 4 -x 1180 -y 540 -defaultsOSRD +preplace portBus M1_2 -pg 1 -lvl 4 -x 1180 -y 560 -defaultsOSRD +preplace portBus NENBL_2 -pg 1 -lvl 4 -x 1180 -y 580 -defaultsOSRD +preplace portBus NSLEEP_2 -pg 1 -lvl 4 -x 1180 -y 600 -defaultsOSRD +preplace portBus CONFIG_3 -pg 1 -lvl 4 -x 1180 -y 640 -defaultsOSRD +preplace portBus DIR_3 -pg 1 -lvl 4 -x 1180 -y 660 -defaultsOSRD +preplace portBus M0_3 -pg 1 -lvl 4 -x 1180 -y 680 -defaultsOSRD +preplace portBus M1_3 -pg 1 -lvl 4 -x 1180 -y 700 -defaultsOSRD +preplace portBus NENBL_3 -pg 1 -lvl 4 -x 1180 -y 720 -defaultsOSRD +preplace portBus NSLEEP_3 -pg 1 -lvl 4 -x 1180 -y 740 -defaultsOSRD preplace inst processing_system7_0 -pg 1 -lvl 1 -x 240 -y 160 -defaultsOSRD -preplace inst rst_ps7_0_100M -pg 1 -lvl 1 -x 240 -y 430 -defaultsOSRD -preplace inst axi_interconnect_0 -pg 1 -lvl 2 -x 630 -y 410 -defaultsOSRD -resize 260 616 -preplace inst drive -pg 1 -lvl 3 -x 990 -y 380 -defaultsOSRD -preplace inst gantry -pg 1 -lvl 3 -x 990 -y 610 -defaultsOSRD -resize 247 226 -preplace netloc Drive_Dir1 1 3 1 NJ 390 -preplace netloc drive_DAC_1_INA 1 3 1 NJ 330 -preplace netloc drive_DAC_1_INB 1 3 1 NJ 350 -preplace netloc drive_DAC_2_INA 1 3 1 NJ 370 -preplace netloc drive_Drive_DIR_1 1 3 1 1150 410n -preplace netloc drive_Drive_DIR_3 1 3 1 1140 430n -preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 20 320 470 740 810 -preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 2 30 330 450 -preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 2 480 750 840 -preplace netloc step_clk_1 1 1 2 450 70 820J -preplace netloc axi_interconnect_0_M00_AXI 1 2 1 N 320 -preplace netloc axi_interconnect_0_M01_AXI 1 2 1 N 340 -preplace netloc axi_interconnect_0_M02_AXI 1 2 1 N 360 -preplace netloc axi_interconnect_0_M03_AXI 1 2 1 N 380 -preplace netloc axi_interconnect_0_M04_AXI 1 2 1 N 400 -preplace netloc axi_interconnect_0_M05_AXI 1 2 1 790 420n -preplace netloc axi_interconnect_0_M06_AXI 1 2 1 830 440n -preplace netloc axi_interconnect_0_M07_AXI 1 2 1 800 460n -preplace netloc axi_interconnect_0_M08_AXI 1 2 1 780 480n +preplace inst rst_ps7_0_100M -pg 1 -lvl 1 -x 240 -y 420 -defaultsOSRD +preplace inst axi_interconnect_0 -pg 1 -lvl 2 -x 640 -y 460 -defaultsOSRD +preplace inst drive -pg 1 -lvl 3 -x 1010 -y 210 -defaultsOSRD +preplace inst gantry -pg 1 -lvl 3 -x 1010 -y 560 -defaultsOSRD +preplace netloc Drive_Dir1 1 3 1 NJ 220 +preplace netloc drive_DAC_1_INA 1 3 1 NJ 160 +preplace netloc drive_DAC_1_INB 1 3 1 NJ 180 +preplace netloc drive_DAC_2_INA 1 3 1 NJ 200 +preplace netloc drive_Drive_DIR_1 1 3 1 1160 240n +preplace netloc drive_Drive_DIR_3 1 3 1 1150 260n +preplace netloc gantry_CONFIG_1 1 3 1 NJ 360 +preplace netloc gantry_CONFIG_2 1 3 1 NJ 500 +preplace netloc gantry_CONFIG_3 1 3 1 NJ 640 +preplace netloc gantry_DIR_1 1 3 1 NJ 380 +preplace netloc gantry_DIR_2 1 3 1 NJ 520 +preplace netloc gantry_DIR_3 1 3 1 NJ 660 +preplace netloc gantry_M0_1 1 3 1 NJ 400 +preplace netloc gantry_M0_2 1 3 1 NJ 540 +preplace netloc gantry_M0_3 1 3 1 NJ 680 +preplace netloc gantry_M1_1 1 3 1 NJ 420 +preplace netloc gantry_M1_2 1 3 1 NJ 560 +preplace netloc gantry_M1_3 1 3 1 NJ 700 +preplace netloc gantry_NENBL_1 1 3 1 NJ 440 +preplace netloc gantry_NENBL_2 1 3 1 NJ 580 +preplace netloc gantry_NENBL_3 1 3 1 NJ 720 +preplace netloc gantry_NSLEEP_1 1 3 1 NJ 460 +preplace netloc gantry_NSLEEP_2 1 3 1 NJ 600 +preplace netloc gantry_NSLEEP_3 1 3 1 NJ 740 +preplace netloc gantry_STEP_1 1 3 1 NJ 480 +preplace netloc gantry_STEP_2 1 3 1 NJ 620 +preplace netloc gantry_STEP_3 1 3 1 NJ 760 +preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 40 520 500 830 870 +preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 2 50 320 430 +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 2 490 90 820 +preplace netloc step_clk_1 1 1 2 430J 70 830 +preplace netloc axi_interconnect_0_M00_AXI 1 2 1 780 150n +preplace netloc axi_interconnect_0_M01_AXI 1 2 1 790 170n +preplace netloc axi_interconnect_0_M02_AXI 1 2 1 800 190n +preplace netloc axi_interconnect_0_M03_AXI 1 2 1 850 210n +preplace netloc axi_interconnect_0_M04_AXI 1 2 1 860 230n +preplace netloc axi_interconnect_0_M05_AXI 1 2 1 860 450n +preplace netloc axi_interconnect_0_M06_AXI 1 2 1 850 470n +preplace netloc axi_interconnect_0_M07_AXI 1 2 1 840 490n +preplace netloc axi_interconnect_0_M08_AXI 1 2 1 800 510n +preplace netloc axi_interconnect_0_M09_AXI 1 2 1 790 530n +preplace netloc axi_interconnect_0_M10_AXI 1 2 1 780 550n +preplace netloc axi_interconnect_0_M11_AXI 1 2 1 N 570 preplace netloc processing_system7_0_DDR 1 1 3 NJ 60 NJ 60 NJ preplace netloc processing_system7_0_FIXED_IO 1 1 3 NJ 80 NJ 80 NJ -preplace netloc processing_system7_0_M_AXI_GP0 1 1 1 470 120n -preplace netloc processing_system7_0_M_AXI_GP1 1 1 1 460 140n -levelinfo -pg 1 0 240 630 990 1170 -pagesize -pg 1 -db -bbox -sgen -110 0 1340 770 +preplace netloc processing_system7_0_M_AXI_GP0 1 1 1 450 120n +preplace netloc processing_system7_0_M_AXI_GP1 1 1 1 440 140n +levelinfo -pg 1 0 240 640 1010 1180 +pagesize -pg 1 -db -bbox -sgen -120 0 1350 850 " } # Restore current instance current_bd_instance $oldCurInst + validate_bd_design save_bd_design -common::send_gid_msg -ssname BD::TCL -id 2050 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." - close_bd_design $design_name } # End of cr_bd_mercury() @@ -1265,7 +1450,7 @@ set_property USED_IN_SYNTHESIS "1" [get_files mercury.bd ] #call make_wrapper to create wrapper files if { [get_property IS_LOCKED [ get_files -norecurse mercury.bd] ] == 1 } { - import_files -fileset sources_1 [file normalize "${origin_dir}/mercury/mercury.gen/sources_1/bd/mercury/hdl/mercury_wrapper.v" ] + import_files -fileset sources_1 [file normalize "${origin_dir}/../../../../../../../home/nwdepatie/mercury/mercury.gen/sources_1/bd/mercury/hdl/mercury_wrapper.v" ] } else { set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse mercury.bd] -top] add_files -norecurse -fileset sources_1 $wrapper_path @@ -1314,7 +1499,7 @@ set_property -name "flow" -value "Vivado Synthesis 2023" -objects $obj set_property -name "name" -value "synth_1" -objects $obj set_property -name "needs_refresh" -value "0" -objects $obj set_property -name "srcset" -value "sources_1" -objects $obj -set_property -name "incremental_checkpoint" -value "" -objects $obj +set_property -name "incremental_checkpoint" -value "$proj_dir/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp" -objects $obj set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj set_property -name "rqs_files" -value "" -objects $obj set_property -name "auto_rqs.suggestion_run" -value "" -objects $obj diff --git a/mercury-hdl/stepper_pulse.v b/mercury-hdl/stepper_pulse.v index e709380..310e576 100644 --- a/mercury-hdl/stepper_pulse.v +++ b/mercury-hdl/stepper_pulse.v @@ -32,17 +32,11 @@ localparam DIVIDE_BY = 2000; // 1000KHz / 2000 = 0.5KHz toggle rate, 1KHz pulse // Internal signals reg [31:0] pulse_counter; // Counter for pulses generated -reg generating; // Flag to indicate if pulse generation is active +reg generating = 0; // Flag to indicate if pulse generation is active // Pulse generation control -always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - // Reset condition - pulse_counter <= 32'd0; - pulse <= 1'b0; - generating <= 1'b0; - done <= 1'b0; - end else if (pulse_counter < pulse_count && generating) begin +always @(posedge clk) begin + if (pulse_counter < pulse_count && generating) begin // Generate pulse pulse <= !pulse; // Toggle the pulse done <= 1'b0; // Not done yet @@ -54,6 +48,7 @@ always @(posedge clk or negedge rst_n) begin pulse <= 1'b0; // Ensure pulse is low when not generating done <= 1'b1; // Signal that pulsing is complete end else if (pulse_count > 0 && !generating && pulse_counter == 0) begin + // Start generating pulse generating <= 1'b1; pulse_counter <= 32'd0; // Reset counter done <= 1'b0; // Ensure done is low at the start @@ -64,5 +59,15 @@ always @(posedge clk or negedge rst_n) begin end end +always @(negedge rst_n) begin + if (!rst_n) begin + // Reset condition + pulse_counter <= 32'd0; + pulse <= 1'b0; + generating <= 1'b0; + done <= 1'b0; + end +end + endmodule diff --git a/mercury-hdl/stepper_pulse_test.v b/mercury-hdl/stepper_pulse_test.v new file mode 100644 index 0000000..445ea47 --- /dev/null +++ b/mercury-hdl/stepper_pulse_test.v @@ -0,0 +1,64 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 03/24/2024 11:11:54 AM +// Design Name: +// Module Name: stepper_pulse_test +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +`timescale 1ns / 1ps + +module stepper_pulse_tb; + +// Inputs +reg clk; +reg rst_n; +reg [31:0] pulse_count; + +// Outputs +wire pulse; +wire done; + +// Instantiate the Unit Under Test (UUT) +stepper_pulse uut ( + .clk(clk), + .rst_n(rst_n), + .pulse_count(pulse_count), + .pulse(pulse), + .done(done) +); + +initial begin + // Initialize Inputs + clk = 0; + rst_n = 0; + pulse_count = 20; // Example pulse count + + // Reset the design + #100; + rst_n = 1; + + // Wait 1000 ns for global reset to finish + #10000000; + +end + +// Clock generation +always #10 clk = ~clk; // Generate a clock with a period of 20ns (50MHz) + +endmodule + From 1e47fb71e3209aa374e1d5d19d13ddd4c3c21af6 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Sun, 24 Mar 2024 13:31:22 -0400 Subject: [PATCH 6/9] Integrating AXI peripherals into gantry sub --- mercury-app/src/hw_ifc/src/drive_sub.rs | 21 ++-- mercury-app/src/hw_ifc/src/gantry_model.rs | 20 +--- mercury-app/src/hw_ifc/src/gantry_sub.rs | 108 +++++++++++++++++++-- mercury-app/src/hw_ifc/src/regmap.rs | 13 +++ 4 files changed, 127 insertions(+), 35 deletions(-) create mode 100644 mercury-app/src/hw_ifc/src/regmap.rs diff --git a/mercury-app/src/hw_ifc/src/drive_sub.rs b/mercury-app/src/hw_ifc/src/drive_sub.rs index ac22ebb..22ff019 100644 --- a/mercury-app/src/hw_ifc/src/drive_sub.rs +++ b/mercury-app/src/hw_ifc/src/drive_sub.rs @@ -3,17 +3,16 @@ use rosrust_msg::geometry_msgs::Twist; use std::sync::{Arc, Mutex}; pub mod chassis_model; +pub mod regmap; pub mod zynq; use self::chassis_model::{ChassisModel, MotorCtrlCmdGroup, WheelPositions}; +use self::regmap::{ + DRV_DIR_GPIO_ADDR, DRV_TIMER_BACK_LEFT_ADDR, DRV_TIMER_BACK_RIGHT_ADDR, + DRV_TIMER_FRONT_LEFT_ADDR, DRV_TIMER_FRONT_RIGHT_ADDR, +}; use zynq::axigpio::{GPIOChannel, AXIGPIO, SIZEOF_AXIGPIO_REG}; use zynq::axitimer::{AXITimer, SIZEOF_AXITIMER_REG}; -const TIMER_FRONT_RIGHT_ADDR: u32 = 0x4280_0000; -const TIMER_FRONT_LEFT_ADDR: u32 = 0x4281_0000; -const TIMER_BACK_RIGHT_ADDR: u32 = 0x4282_0000; -const TIMER_BACK_LEFT_ADDR: u32 = 0x4283_0000; -const DIRECTION_GPIO_ADDR: u32 = 0x4121_0000; - const MAX_LINEAR_SPEED: f64 = 10.0; /* meters/second */ const MAX_ANGULAR_SPEED: f64 = 10.0; /* radians/second */ const WHEEL_RADIUS: f64 = 10.0; /* meters */ @@ -123,19 +122,19 @@ fn main() { rosrust::init("drive_sub"); let pwm_front_right = Arc::new(Mutex::new( - AXITimer::new(TIMER_FRONT_RIGHT_ADDR, SIZEOF_AXITIMER_REG).unwrap(), + AXITimer::new(DRV_TIMER_FRONT_RIGHT_ADDR, SIZEOF_AXITIMER_REG).unwrap(), )); let pwm_front_left = Arc::new(Mutex::new( - AXITimer::new(TIMER_FRONT_LEFT_ADDR, SIZEOF_AXITIMER_REG).unwrap(), + AXITimer::new(DRV_TIMER_FRONT_LEFT_ADDR, SIZEOF_AXITIMER_REG).unwrap(), )); let pwm_back_right = Arc::new(Mutex::new( - AXITimer::new(TIMER_BACK_RIGHT_ADDR, SIZEOF_AXITIMER_REG).unwrap(), + AXITimer::new(DRV_TIMER_BACK_RIGHT_ADDR, SIZEOF_AXITIMER_REG).unwrap(), )); let pwm_back_left = Arc::new(Mutex::new( - AXITimer::new(TIMER_BACK_LEFT_ADDR, SIZEOF_AXITIMER_REG).unwrap(), + AXITimer::new(DRV_TIMER_BACK_LEFT_ADDR, SIZEOF_AXITIMER_REG).unwrap(), )); let direction_control = Arc::new(Mutex::new( - AXIGPIO::new(DIRECTION_GPIO_ADDR, SIZEOF_AXIGPIO_REG).unwrap(), + AXIGPIO::new(DRV_DIR_GPIO_ADDR, SIZEOF_AXIGPIO_REG).unwrap(), )); let drive_ctrl = DriveController::new( diff --git a/mercury-app/src/hw_ifc/src/gantry_model.rs b/mercury-app/src/hw_ifc/src/gantry_model.rs index 1483832..367f7db 100644 --- a/mercury-app/src/hw_ifc/src/gantry_model.rs +++ b/mercury-app/src/hw_ifc/src/gantry_model.rs @@ -10,7 +10,6 @@ pub enum GantryAxes { pub struct StepperCtrlCmd { pub steps: i32, - speed: f64, } pub struct StepperCtrlCmdGroup { @@ -77,18 +76,16 @@ impl GantryPosition { pub struct GantryModel { current_position: GantryPosition, - max_speed: f64, } impl GantryModel { - pub fn new(max_speed: f64) -> GantryModel { + pub fn new() -> GantryModel { GantryModel { current_position: GantryPosition { x: 0.0, y: 0.0, z: 0.0, }, - max_speed: max_speed, } } @@ -109,18 +106,9 @@ impl GantryModel { self.current_position = target_position; StepperCtrlCmdGroup { - x: StepperCtrlCmd { - steps: x_steps, - speed: self.max_speed, - }, - y: StepperCtrlCmd { - steps: y_steps, - speed: self.max_speed, - }, - z: StepperCtrlCmd { - steps: z_steps, - speed: self.max_speed, - }, + x: StepperCtrlCmd { steps: x_steps }, + y: StepperCtrlCmd { steps: y_steps }, + z: StepperCtrlCmd { steps: z_steps }, } } } diff --git a/mercury-app/src/hw_ifc/src/gantry_sub.rs b/mercury-app/src/hw_ifc/src/gantry_sub.rs index 62033b1..52c3df8 100644 --- a/mercury-app/src/hw_ifc/src/gantry_sub.rs +++ b/mercury-app/src/hw_ifc/src/gantry_sub.rs @@ -5,37 +5,108 @@ use self::gantry_model::{ GantryAxes, GantryModel, GantryPosition, StepperCtrlCmd, StepperCtrlCmdGroup, }; use std::sync::{Arc, Mutex}; +pub mod zynq; +use zynq::axigpio::{GPIOChannel, AXIGPIO, SIZEOF_AXIGPIO_REG}; pub mod msg { rosrust::rosmsg_include!(hw_srv / movegantry, hw_srv / calibrategantry); } -const MAX_SPEED: f64 = 10.0; /* meters/second */ +pub mod regmap; +use self::regmap::{ + GANTRY_DIR1_ADDR, GANTRY_DIR2_ADDR, GANTRY_DIR3_ADDR, GANTRY_RESET_ADDR, GANTRY_STEP1_ADDR, + GANTRY_STEP2_ADDR, GANTRY_STEP3_ADDR, +}; + +pub struct StepperController { + direction_control: AXIGPIO, + step_control: AXIGPIO, +} + +impl StepperController { + pub fn new(direction_control: AXIGPIO, step_control: AXIGPIO) -> StepperController { + StepperController { + direction_control: direction_control, + step_control: step_control, + } + } + + pub fn set_direction(&mut self, is_forward: bool) { + self.direction_control + .write_gpio(is_forward as u32, GPIOChannel::GpioChannel1); + } + + pub fn write_step_cmd(&mut self, num_steps: u32) { + self.step_control + .write_gpio(num_steps, GPIOChannel::GpioChannel1); + } +} pub struct GantryController { model: GantryModel, + stepper1: Arc>, + stepper2: Arc>, + stepper3: Arc>, + reset: Arc>, } impl GantryController { - pub fn new() -> Self { + pub fn new( + stepper1: Arc>, + stepper2: Arc>, + stepper3: Arc>, + reset: Arc>, + ) -> Self { GantryController { - model: GantryModel::new(MAX_SPEED), + model: GantryModel::new(), + stepper1: stepper1, + stepper2: stepper2, + stepper3: stepper3, + reset: reset, } } + fn write_steppers(&mut self, stepper_cmds: StepperCtrlCmdGroup) { + self.stepper1 + .lock() + .unwrap() + .set_direction(stepper_cmds[GantryAxes::X].steps < 0); + self.stepper1 + .lock() + .unwrap() + .write_step_cmd(i32::abs(stepper_cmds[GantryAxes::X].steps) as u32); + self.stepper2 + .lock() + .unwrap() + .set_direction(stepper_cmds[GantryAxes::Y].steps < 0); + self.stepper2 + .lock() + .unwrap() + .write_step_cmd(i32::abs(stepper_cmds[GantryAxes::Y].steps) as u32); + self.stepper3 + .lock() + .unwrap() + .set_direction(stepper_cmds[GantryAxes::Z].steps < 0); + self.stepper3 + .lock() + .unwrap() + .write_step_cmd(i32::abs(stepper_cmds[GantryAxes::Z].steps) as u32); + } + pub fn move_callback(&mut self, data: rosrust_msg::hw_srv::movegantryReq) { let stepper_cmds = self .model .calc_control_signals(GantryPosition::new(data.x, data.y, data.z)); - //stepper_cmds[GantryAxes::X]; - //stepper_cmds[GantryAxes::Y]; - //stepper_cmds[GantryAxes::Z]; + + self.write_steppers(stepper_cmds); } pub fn calibrate_callback(&mut self) { let stepper_cmds = self .model .calc_control_signals(GantryPosition::new(0.0, 0.0, 0.0)); + + self.write_steppers(stepper_cmds); } } @@ -43,12 +114,33 @@ fn main() { /* Initialize ROS node */ rosrust::init("gantry_sub"); - let gantry_ctrl = Arc::new(Mutex::new(GantryController::new())); + let stepper1 = Arc::new(Mutex::new(StepperController::new( + AXIGPIO::new(GANTRY_DIR1_ADDR, SIZEOF_AXIGPIO_REG).unwrap(), + AXIGPIO::new(GANTRY_STEP1_ADDR, SIZEOF_AXIGPIO_REG).unwrap(), + ))); + + let stepper2 = Arc::new(Mutex::new(StepperController::new( + AXIGPIO::new(GANTRY_DIR2_ADDR, SIZEOF_AXIGPIO_REG).unwrap(), + AXIGPIO::new(GANTRY_STEP2_ADDR, SIZEOF_AXIGPIO_REG).unwrap(), + ))); + + let stepper3 = Arc::new(Mutex::new(StepperController::new( + AXIGPIO::new(GANTRY_DIR3_ADDR, SIZEOF_AXIGPIO_REG).unwrap(), + AXIGPIO::new(GANTRY_STEP3_ADDR, SIZEOF_AXIGPIO_REG).unwrap(), + ))); + + let reset = Arc::new(Mutex::new( + AXIGPIO::new(GANTRY_DIR3_ADDR, SIZEOF_AXIGPIO_REG).unwrap(), + )); + + let gantry_ctrl = Arc::new(Mutex::new(GantryController::new( + stepper1, stepper2, stepper3, reset, + ))); /* Create subscriber */ let gantry_ctrl_clone = gantry_ctrl.clone(); let _service_move = rosrust::service::( - "/gantry/pose/goal", + "/services/gantry/setgoal", move |coords: rosrust_msg::hw_srv::movegantryReq| { let mut gantry_ctrl = gantry_ctrl_clone.lock().unwrap(); gantry_ctrl.move_callback(coords); diff --git a/mercury-app/src/hw_ifc/src/regmap.rs b/mercury-app/src/hw_ifc/src/regmap.rs new file mode 100644 index 0000000..2a8b603 --- /dev/null +++ b/mercury-app/src/hw_ifc/src/regmap.rs @@ -0,0 +1,13 @@ +pub const DRV_DIR_GPIO_ADDR: u32 = 0x4122_0000; +pub const DRV_TIMER_FRONT_RIGHT_ADDR: u32 = 0x4280_0000; +pub const DRV_TIMER_FRONT_LEFT_ADDR: u32 = 0x4281_0000; +pub const DRV_TIMER_BACK_RIGHT_ADDR: u32 = 0x4282_0000; +pub const DRV_TIMER_BACK_LEFT_ADDR: u32 = 0x4283_0000; + +pub const GANTRY_DIR1_ADDR: u32 = 0x8000_0000; // TODO: Double check Gantry DIR 1 behavior +pub const GANTRY_DIR2_ADDR: u32 = 0x4120_0000; +pub const GANTRY_DIR3_ADDR: u32 = 0x4121_0000; +pub const GANTRY_RESET_ADDR: u32 = 0x4126_0000; +pub const GANTRY_STEP1_ADDR: u32 = 0x4123_0000; +pub const GANTRY_STEP2_ADDR: u32 = 0x4124_0000; +pub const GANTRY_STEP3_ADDR: u32 = 0x4125_0000; From f3da418efaa315e740efbe6efd5155fab4fe18b7 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Tue, 26 Mar 2024 23:00:24 -0400 Subject: [PATCH 7/9] Pushing changes --- mercury-app/src/hw_ifc/src/gantry_sub.rs | 8 ++++++-- mercury-app/src/hw_ifc/src/regmap.rs | 16 ++++++++-------- mercury-app/src/hw_srv/srv/frontlight.srv | 3 +++ mercury-app/src/hw_srv/srv/grip.srv | 4 ++-- mercury-app/src/hw_srv/srv/release.srv | 2 ++ mercury-app/src/hw_srv/srv/worklight.srv | 5 +++-- 6 files changed, 24 insertions(+), 14 deletions(-) diff --git a/mercury-app/src/hw_ifc/src/gantry_sub.rs b/mercury-app/src/hw_ifc/src/gantry_sub.rs index 52c3df8..73a8e85 100644 --- a/mercury-app/src/hw_ifc/src/gantry_sub.rs +++ b/mercury-app/src/hw_ifc/src/gantry_sub.rs @@ -98,7 +98,9 @@ impl GantryController { .model .calc_control_signals(GantryPosition::new(data.x, data.y, data.z)); - self.write_steppers(stepper_cmds); + rosrust::ros_info!("X:{}\tY:{}\tZ:{}", data.x, data.y, data.z); + + //self.write_steppers(stepper_cmds); } pub fn calibrate_callback(&mut self) { @@ -106,7 +108,9 @@ impl GantryController { .model .calc_control_signals(GantryPosition::new(0.0, 0.0, 0.0)); - self.write_steppers(stepper_cmds); + rosrust::ros_info!("CALIBRATING..."); + + //self.write_steppers(stepper_cmds); } } diff --git a/mercury-app/src/hw_ifc/src/regmap.rs b/mercury-app/src/hw_ifc/src/regmap.rs index 2a8b603..b166baa 100644 --- a/mercury-app/src/hw_ifc/src/regmap.rs +++ b/mercury-app/src/hw_ifc/src/regmap.rs @@ -1,13 +1,13 @@ -pub const DRV_DIR_GPIO_ADDR: u32 = 0x4122_0000; +pub const DRV_DIR_GPIO_ADDR: u32 = 0x8000_0000; pub const DRV_TIMER_FRONT_RIGHT_ADDR: u32 = 0x4280_0000; pub const DRV_TIMER_FRONT_LEFT_ADDR: u32 = 0x4281_0000; pub const DRV_TIMER_BACK_RIGHT_ADDR: u32 = 0x4282_0000; pub const DRV_TIMER_BACK_LEFT_ADDR: u32 = 0x4283_0000; -pub const GANTRY_DIR1_ADDR: u32 = 0x8000_0000; // TODO: Double check Gantry DIR 1 behavior -pub const GANTRY_DIR2_ADDR: u32 = 0x4120_0000; -pub const GANTRY_DIR3_ADDR: u32 = 0x4121_0000; -pub const GANTRY_RESET_ADDR: u32 = 0x4126_0000; -pub const GANTRY_STEP1_ADDR: u32 = 0x4123_0000; -pub const GANTRY_STEP2_ADDR: u32 = 0x4124_0000; -pub const GANTRY_STEP3_ADDR: u32 = 0x4125_0000; +pub const GANTRY_DIR1_ADDR: u32 = 0x4120_0000; // TODO: Double check Gantry DIR 1 behavior +pub const GANTRY_DIR2_ADDR: u32 = 0x4121_0000; +pub const GANTRY_DIR3_ADDR: u32 = 0x4122_0000; +pub const GANTRY_RESET_ADDR: u32 = 0x4123_0000; +pub const GANTRY_STEP1_ADDR: u32 = 0x4124_0000; +pub const GANTRY_STEP2_ADDR: u32 = 0x4125_0000; +pub const GANTRY_STEP3_ADDR: u32 = 0x4126_0000; diff --git a/mercury-app/src/hw_srv/srv/frontlight.srv b/mercury-app/src/hw_srv/srv/frontlight.srv index e69de29..332aa8f 100644 --- a/mercury-app/src/hw_srv/srv/frontlight.srv +++ b/mercury-app/src/hw_srv/srv/frontlight.srv @@ -0,0 +1,3 @@ +uint32 brightness +--- +bool status \ No newline at end of file diff --git a/mercury-app/src/hw_srv/srv/grip.srv b/mercury-app/src/hw_srv/srv/grip.srv index 9d6226c..e637707 100644 --- a/mercury-app/src/hw_srv/srv/grip.srv +++ b/mercury-app/src/hw_srv/srv/grip.srv @@ -1,2 +1,2 @@ -bool brightness ---- \ No newline at end of file +--- +bool status \ No newline at end of file diff --git a/mercury-app/src/hw_srv/srv/release.srv b/mercury-app/src/hw_srv/srv/release.srv index e69de29..e637707 100644 --- a/mercury-app/src/hw_srv/srv/release.srv +++ b/mercury-app/src/hw_srv/srv/release.srv @@ -0,0 +1,2 @@ +--- +bool status \ No newline at end of file diff --git a/mercury-app/src/hw_srv/srv/worklight.srv b/mercury-app/src/hw_srv/srv/worklight.srv index 9d6226c..332aa8f 100644 --- a/mercury-app/src/hw_srv/srv/worklight.srv +++ b/mercury-app/src/hw_srv/srv/worklight.srv @@ -1,2 +1,3 @@ -bool brightness ---- \ No newline at end of file +uint32 brightness +--- +bool status \ No newline at end of file From 55ab6562fb1bdde08ed804cf6d6d9cae9e632704 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Tue, 26 Mar 2024 23:53:01 -0400 Subject: [PATCH 8/9] Adding messages to CMake --- mercury-app/src/hw_srv/CMakeLists.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/mercury-app/src/hw_srv/CMakeLists.txt b/mercury-app/src/hw_srv/CMakeLists.txt index 296c237..4a98603 100644 --- a/mercury-app/src/hw_srv/CMakeLists.txt +++ b/mercury-app/src/hw_srv/CMakeLists.txt @@ -59,6 +59,8 @@ add_service_files( worklight.srv grip.srv release.srv + movegantry.srv + calibrategantry.srv ) ## Generate actions in the 'action' folder From 50368a1cc702f24e6415bd56466798fa61113366 Mon Sep 17 00:00:00 2001 From: nwdepatie Date: Wed, 27 Mar 2024 14:20:46 -0400 Subject: [PATCH 9/9] Making some final changes --- mercury-app/src/hw_ifc/CMakeLists.txt | 2 +- mercury-hdl/mercury_proj.tcl | 214 ++++++++++++++++---------- 2 files changed, 132 insertions(+), 84 deletions(-) diff --git a/mercury-app/src/hw_ifc/CMakeLists.txt b/mercury-app/src/hw_ifc/CMakeLists.txt index 297743c..9b646e3 100644 --- a/mercury-app/src/hw_ifc/CMakeLists.txt +++ b/mercury-app/src/hw_ifc/CMakeLists.txt @@ -151,7 +151,7 @@ include_directories( add_custom_target(hw_ifc ALL - COMMAND cargo build -p mercury --release + COMMAND cargo build -p mercury --release #--target armv7-unknown-linux-gnueabihf WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/../src/hw_ifc #COMMAND ${CMAKE_COMMAND} -E copy ${CMAKE_BINARY_DIR}/cargo/release/my-project-binary ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/my-project-binary COMMENT "Build Mercury..." diff --git a/mercury-hdl/mercury_proj.tcl b/mercury-hdl/mercury_proj.tcl index 86d1c0b..908f1a2 100644 --- a/mercury-hdl/mercury_proj.tcl +++ b/mercury-hdl/mercury_proj.tcl @@ -3,7 +3,7 @@ # # mercury_proj.tcl: Tcl script for re-creating project 'mercury' # -# Generated by Vivado on Sun Mar 24 12:40:01 EDT 2024 +# Generated by Vivado on Sun Mar 24 15:41:40 EDT 2024 # IP Build 3864474 on Sun May 7 20:36:21 MDT 2023 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -23,7 +23,7 @@ # 2. The following source(s) files that were local or imported into the original project. # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) # -# "/home/nwdepatie/mercury/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp" +# "/media/nwdepatie/shared/workdir/Capstone/mercury/mercury-hdl/mercury/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp" # # 3. The following remote source files that were added to the original project:- # @@ -37,7 +37,7 @@ proc checkRequiredFiles { origin_dir} { set status true set files [list \ - "[file normalize "$origin_dir/../../../../../../../home/nwdepatie/mercury/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp"]"\ + "[file normalize "$origin_dir/mercury/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp"]"\ ] foreach ifile $files { if { ![file isfile $ifile] } { @@ -125,7 +125,7 @@ if { $::argc > 0 } { } # Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/../../../../../../../home/nwdepatie/mercury"]" +set orig_proj_dir "[file normalize "$origin_dir/mercury"]" # Check for paths and files needed for project creation set validate_required 0 @@ -351,6 +351,7 @@ set_property -name "simulator_launch_mode" -value "off" -objects $obj set_property -name "source_set" -value "sources_1" -objects $obj set_property -name "systemc_include_dirs" -value "" -objects $obj set_property -name "top" -value "stepper_pulse_tb" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj set_property -name "transport_int_delay" -value "0" -objects $obj set_property -name "transport_path_delay" -value "0" -objects $obj @@ -399,7 +400,7 @@ set_property -name "xsim.simulate.xsim.more_options" -value "" -objects $obj set obj [get_filesets utils_1] # Import local files from the original project set files [list \ - [file normalize "${origin_dir}/../../../../../../../home/nwdepatie/mercury/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp" ]\ + [file normalize "${origin_dir}/mercury/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp" ]\ ] set imported_files [import_files -fileset utils_1 $files] @@ -795,9 +796,6 @@ proc create_hier_cell_drive { parentCell nameHier } { # Create instance: axi_timer_drv2, and set properties set axi_timer_drv2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_drv2 ] - # Create instance: axi_timer_drv1, and set properties - set axi_timer_drv1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_drv1 ] - # Create instance: axi_timer_drv3, and set properties set axi_timer_drv3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_drv3 ] @@ -822,25 +820,74 @@ proc create_hier_cell_drive { parentCell nameHier } { # Create instance: xlslice_0, and set properties set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] + # Create instance: axi_timer_drv1, and set properties + set axi_timer_drv1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_drv1 ] + # Create interface connections - connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins axi_timer_drv1/S_AXI] [get_bd_intf_pins S_AXI] connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axi_timer_drv3/S_AXI] [get_bd_intf_pins S_AXI1] connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins axi_timer_drv4/S_AXI] [get_bd_intf_pins S_AXI2] connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins axi_gpio_dir/S_AXI] [get_bd_intf_pins S_AXI3] connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins axi_timer_drv2/S_AXI] [get_bd_intf_pins S_AXI4] + connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_timer_drv1/S_AXI] # Create port connections connect_bd_net -net axi_gpio_2_gpio2_io_o [get_bd_pins axi_gpio_dir/gpio2_io_o] [get_bd_pins xlslice_1/Din] connect_bd_net -net axi_gpio_2_gpio_io_o [get_bd_pins axi_gpio_dir/gpio_io_o] [get_bd_pins xlslice_0/Din] connect_bd_net -net axi_timer_0_pwm0 [get_bd_pins axi_timer_drv2/pwm0] [get_bd_pins DAC_1_INA] - connect_bd_net -net axi_timer_1_pwm0 [get_bd_pins axi_timer_drv1/pwm0] [get_bd_pins DAC_1_INB] connect_bd_net -net axi_timer_2_pwm0 [get_bd_pins axi_timer_drv3/pwm0] [get_bd_pins DAC_2_INA] connect_bd_net -net axi_timer_3_pwm0 [get_bd_pins axi_timer_drv4/pwm0] [get_bd_pins DAC_2_INB] - connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_timer_drv1/s_axi_aclk] [get_bd_pins axi_timer_drv3/s_axi_aclk] [get_bd_pins axi_timer_drv4/s_axi_aclk] [get_bd_pins axi_gpio_dir/s_axi_aclk] [get_bd_pins axi_timer_drv2/s_axi_aclk] - connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins axi_timer_drv1/s_axi_aresetn] [get_bd_pins axi_timer_drv4/s_axi_aresetn] [get_bd_pins axi_timer_drv3/s_axi_aresetn] [get_bd_pins axi_gpio_dir/s_axi_aresetn] [get_bd_pins axi_timer_drv2/s_axi_aresetn] + connect_bd_net -net s_axi_aclk_1 [get_bd_pins s_axi_aclk] [get_bd_pins axi_timer_drv3/s_axi_aclk] [get_bd_pins axi_timer_drv4/s_axi_aclk] [get_bd_pins axi_gpio_dir/s_axi_aclk] [get_bd_pins axi_timer_drv2/s_axi_aclk] [get_bd_pins axi_timer_drv1/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins axi_timer_drv4/s_axi_aresetn] [get_bd_pins axi_timer_drv3/s_axi_aresetn] [get_bd_pins axi_gpio_dir/s_axi_aresetn] [get_bd_pins axi_timer_drv2/s_axi_aresetn] [get_bd_pins axi_timer_drv1/s_axi_aresetn] connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins Drive_DIR_1] connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins Drive_DIR_3] + # Perform GUI Layout + regenerate_bd_layout -hierarchy [get_bd_cells /drive] -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"0.389126", + "Default View_TopLeft":"-144,-332", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS +# -string -flagsOSRD +preplace port S_AXI -pg 1 -lvl 0 -x 0 -y 660 -defaultsOSRD +preplace port S_AXI1 -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD +preplace port S_AXI2 -pg 1 -lvl 0 -x 0 -y 460 -defaultsOSRD +preplace port S_AXI3 -pg 1 -lvl 0 -x 0 -y 850 -defaultsOSRD +preplace port S_AXI4 -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD +preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y 870 -defaultsOSRD +preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y 890 -defaultsOSRD +preplace port port-id_DAC_1_INA -pg 1 -lvl 3 -x 620 -y 320 -defaultsOSRD +preplace port port-id_DAC_1_INB -pg 1 -lvl 3 -x 620 -y 20 -defaultsOSRD +preplace port port-id_DAC_2_INA -pg 1 -lvl 3 -x 620 -y 120 -defaultsOSRD +preplace port port-id_DAC_2_INB -pg 1 -lvl 3 -x 620 -y 520 -defaultsOSRD +preplace portBus Drive_DIR_1 -pg 1 -lvl 3 -x 620 -y 860 -defaultsOSRD +preplace portBus Drive_DIR_3 -pg 1 -lvl 3 -x 620 -y 960 -defaultsOSRD +preplace inst axi_timer_drv2 -pg 1 -lvl 2 -x 470 -y 310 -defaultsOSRD +preplace inst axi_timer_drv3 -pg 1 -lvl 2 -x 470 -y 110 -defaultsOSRD +preplace inst axi_timer_drv4 -pg 1 -lvl 2 -x 470 -y 510 -defaultsOSRD +preplace inst axi_gpio_dir -pg 1 -lvl 1 -x 180 -y 870 -defaultsOSRD +preplace inst xlslice_1 -pg 1 -lvl 2 -x 470 -y 960 -defaultsOSRD +preplace inst xlslice_0 -pg 1 -lvl 2 -x 470 -y 860 -defaultsOSRD +preplace inst axi_timer_drv1 -pg 1 -lvl 2 -x 470 -y 710 -defaultsOSRD +preplace netloc axi_gpio_2_gpio2_io_o 1 1 1 330J 900n +preplace netloc axi_gpio_2_gpio_io_o 1 1 1 NJ 860 +preplace netloc axi_timer_0_pwm0 1 2 1 NJ 320 +preplace netloc axi_timer_2_pwm0 1 2 1 NJ 120 +preplace netloc axi_timer_3_pwm0 1 2 1 NJ 520 +preplace netloc s_axi_aclk_1 1 0 2 20 740 330 +preplace netloc s_axi_aresetn_1 1 0 2 30 760 340 +preplace netloc xlslice_0_Dout 1 2 1 NJ 860 +preplace netloc xlslice_1_Dout 1 2 1 NJ 960 +preplace netloc Conn2 1 0 2 NJ 60 NJ +preplace netloc Conn3 1 0 2 NJ 460 NJ +preplace netloc Conn4 1 0 1 NJ 850 +preplace netloc Conn5 1 0 2 NJ 260 NJ +preplace netloc S_AXI_1 1 0 2 NJ 660 NJ +levelinfo -pg 1 0 180 470 620 +pagesize -pg 1 -db -bbox -sgen -150 0 790 1020 +" +} + # Restore current instance current_bd_instance $oldCurInst } @@ -1252,7 +1299,7 @@ proc create_hier_cell_drive { parentCell nameHier } { # Create instance: axi_interconnect_0, and set properties set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] set_property -dict [list \ - CONFIG.NUM_MI {12} \ + CONFIG.NUM_MI {16} \ CONFIG.NUM_SI {2} \ ] $axi_interconnect_0 @@ -1315,70 +1362,70 @@ proc create_hier_cell_drive { parentCell nameHier } { connect_bd_net -net step_clk_1 [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins gantry/step_clk] # Create address segments + assign_bd_address -offset 0x40030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_dir1/S_AXI/Reg] -force + assign_bd_address -offset 0x40040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_dir2/S_AXI/Reg] -force + assign_bd_address -offset 0x40050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_dir3/S_AXI/Reg] -force + assign_bd_address -offset 0x41220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_gpio_dir/S_AXI/Reg] -force + assign_bd_address -offset 0x41260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_rst/S_AXI/Reg] -force assign_bd_address -offset 0x41230000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_step1/S_AXI/Reg] -force assign_bd_address -offset 0x41240000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_step2/S_AXI/Reg] -force - assign_bd_address -offset 0x41220000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_gpio_dir/S_AXI/Reg] -force assign_bd_address -offset 0x41250000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_step3/S_AXI/Reg] -force - assign_bd_address -offset 0x41260000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_rst/S_AXI/Reg] -force - assign_bd_address -dict [list offset 0x7FFF8000 range 0x00008000 offset 0x80000000 range 0x00008000] -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_dir1/S_AXI/Reg] -force - assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_dir2/S_AXI/Reg] -force - assign_bd_address -offset 0x41210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs gantry/axi_gpio_dir3/S_AXI/Reg] -force - assign_bd_address -offset 0x42800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv2/S_AXI/Reg] -force - assign_bd_address -offset 0x42810000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv1/S_AXI/Reg] -force - assign_bd_address -offset 0x42820000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv3/S_AXI/Reg] -force - assign_bd_address -offset 0x42830000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv4/S_AXI/Reg] -force + assign_bd_address -dict [list offset 0x7FFF8000 range 0x00008000 offset 0x80000000 range 0x00008000] -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv1/S_AXI/Reg] -force + assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv2/S_AXI/Reg] -force + assign_bd_address -offset 0x40010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv3/S_AXI/Reg] -force + assign_bd_address -offset 0x40020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs drive/axi_timer_drv4/S_AXI/Reg] -force # Perform GUI Layout regenerate_bd_layout -layout_string { "ActiveEmotionalView":"Default View", - "Default View_ScaleFactor":"0.797945", - "Default View_TopLeft":"-108,-4", + "Default View_ScaleFactor":"0.809697", + "Default View_TopLeft":"336,0", "ExpandedHierarchyInLayout":"", "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS # -string -flagsOSRD -preplace port DDR -pg 1 -lvl 4 -x 1180 -y 60 -defaultsOSRD -preplace port FIXED_IO -pg 1 -lvl 4 -x 1180 -y 80 -defaultsOSRD -preplace port port-id_DAC_1_INA -pg 1 -lvl 4 -x 1180 -y 160 -defaultsOSRD -preplace port port-id_DAC_1_INB -pg 1 -lvl 4 -x 1180 -y 180 -defaultsOSRD -preplace port port-id_DAC_2_INA -pg 1 -lvl 4 -x 1180 -y 200 -defaultsOSRD -preplace port port-id_DAC_2_INB -pg 1 -lvl 4 -x 1180 -y 220 -defaultsOSRD +preplace port DDR -pg 1 -lvl 4 -x 1340 -y 60 -defaultsOSRD +preplace port FIXED_IO -pg 1 -lvl 4 -x 1340 -y 80 -defaultsOSRD +preplace port port-id_DAC_1_INA -pg 1 -lvl 4 -x 1340 -y 160 -defaultsOSRD +preplace port port-id_DAC_1_INB -pg 1 -lvl 4 -x 1340 -y 180 -defaultsOSRD +preplace port port-id_DAC_2_INA -pg 1 -lvl 4 -x 1340 -y 200 -defaultsOSRD +preplace port port-id_DAC_2_INB -pg 1 -lvl 4 -x 1340 -y 220 -defaultsOSRD preplace port port-id_reset_rtl -pg 1 -lvl 0 -x 0 -y 20 -defaultsOSRD -preplace port port-id_STEP_1 -pg 1 -lvl 4 -x 1180 -y 480 -defaultsOSRD -preplace port port-id_STEP_2 -pg 1 -lvl 4 -x 1180 -y 620 -defaultsOSRD -preplace port port-id_STEP_3 -pg 1 -lvl 4 -x 1180 -y 760 -defaultsOSRD -preplace portBus Drive_DIR_1 -pg 1 -lvl 4 -x 1180 -y 240 -defaultsOSRD -preplace portBus Drive_DIR_2 -pg 1 -lvl 4 -x 1180 -y 260 -defaultsOSRD -preplace portBus Drive_DIR_3 -pg 1 -lvl 4 -x 1180 -y 280 -defaultsOSRD -preplace portBus Drive_DIR_4 -pg 1 -lvl 4 -x 1180 -y 300 -defaultsOSRD -preplace portBus NENBL_1 -pg 1 -lvl 4 -x 1180 -y 440 -defaultsOSRD -preplace portBus DIR_1 -pg 1 -lvl 4 -x 1180 -y 380 -defaultsOSRD -preplace portBus M0_1 -pg 1 -lvl 4 -x 1180 -y 400 -defaultsOSRD -preplace portBus M1_1 -pg 1 -lvl 4 -x 1180 -y 420 -defaultsOSRD -preplace portBus CONFIG_1 -pg 1 -lvl 4 -x 1180 -y 360 -defaultsOSRD -preplace portBus NSLEEP_1 -pg 1 -lvl 4 -x 1180 -y 460 -defaultsOSRD -preplace portBus CONFIG_2 -pg 1 -lvl 4 -x 1180 -y 500 -defaultsOSRD -preplace portBus DIR_2 -pg 1 -lvl 4 -x 1180 -y 520 -defaultsOSRD -preplace portBus M0_2 -pg 1 -lvl 4 -x 1180 -y 540 -defaultsOSRD -preplace portBus M1_2 -pg 1 -lvl 4 -x 1180 -y 560 -defaultsOSRD -preplace portBus NENBL_2 -pg 1 -lvl 4 -x 1180 -y 580 -defaultsOSRD -preplace portBus NSLEEP_2 -pg 1 -lvl 4 -x 1180 -y 600 -defaultsOSRD -preplace portBus CONFIG_3 -pg 1 -lvl 4 -x 1180 -y 640 -defaultsOSRD -preplace portBus DIR_3 -pg 1 -lvl 4 -x 1180 -y 660 -defaultsOSRD -preplace portBus M0_3 -pg 1 -lvl 4 -x 1180 -y 680 -defaultsOSRD -preplace portBus M1_3 -pg 1 -lvl 4 -x 1180 -y 700 -defaultsOSRD -preplace portBus NENBL_3 -pg 1 -lvl 4 -x 1180 -y 720 -defaultsOSRD -preplace portBus NSLEEP_3 -pg 1 -lvl 4 -x 1180 -y 740 -defaultsOSRD +preplace port port-id_STEP_1 -pg 1 -lvl 4 -x 1340 -y 480 -defaultsOSRD +preplace port port-id_STEP_2 -pg 1 -lvl 4 -x 1340 -y 620 -defaultsOSRD +preplace port port-id_STEP_3 -pg 1 -lvl 4 -x 1340 -y 760 -defaultsOSRD +preplace portBus Drive_DIR_1 -pg 1 -lvl 4 -x 1340 -y 240 -defaultsOSRD +preplace portBus Drive_DIR_2 -pg 1 -lvl 4 -x 1340 -y 260 -defaultsOSRD +preplace portBus Drive_DIR_3 -pg 1 -lvl 4 -x 1340 -y 280 -defaultsOSRD +preplace portBus Drive_DIR_4 -pg 1 -lvl 4 -x 1340 -y 300 -defaultsOSRD +preplace portBus NENBL_1 -pg 1 -lvl 4 -x 1340 -y 440 -defaultsOSRD +preplace portBus DIR_1 -pg 1 -lvl 4 -x 1340 -y 380 -defaultsOSRD +preplace portBus M0_1 -pg 1 -lvl 4 -x 1340 -y 400 -defaultsOSRD +preplace portBus M1_1 -pg 1 -lvl 4 -x 1340 -y 420 -defaultsOSRD +preplace portBus CONFIG_1 -pg 1 -lvl 4 -x 1340 -y 360 -defaultsOSRD +preplace portBus NSLEEP_1 -pg 1 -lvl 4 -x 1340 -y 460 -defaultsOSRD +preplace portBus CONFIG_2 -pg 1 -lvl 4 -x 1340 -y 500 -defaultsOSRD +preplace portBus DIR_2 -pg 1 -lvl 4 -x 1340 -y 520 -defaultsOSRD +preplace portBus M0_2 -pg 1 -lvl 4 -x 1340 -y 540 -defaultsOSRD +preplace portBus M1_2 -pg 1 -lvl 4 -x 1340 -y 560 -defaultsOSRD +preplace portBus NENBL_2 -pg 1 -lvl 4 -x 1340 -y 580 -defaultsOSRD +preplace portBus NSLEEP_2 -pg 1 -lvl 4 -x 1340 -y 600 -defaultsOSRD +preplace portBus CONFIG_3 -pg 1 -lvl 4 -x 1340 -y 640 -defaultsOSRD +preplace portBus DIR_3 -pg 1 -lvl 4 -x 1340 -y 660 -defaultsOSRD +preplace portBus M0_3 -pg 1 -lvl 4 -x 1340 -y 680 -defaultsOSRD +preplace portBus M1_3 -pg 1 -lvl 4 -x 1340 -y 700 -defaultsOSRD +preplace portBus NENBL_3 -pg 1 -lvl 4 -x 1340 -y 720 -defaultsOSRD +preplace portBus NSLEEP_3 -pg 1 -lvl 4 -x 1340 -y 740 -defaultsOSRD preplace inst processing_system7_0 -pg 1 -lvl 1 -x 240 -y 160 -defaultsOSRD preplace inst rst_ps7_0_100M -pg 1 -lvl 1 -x 240 -y 420 -defaultsOSRD -preplace inst axi_interconnect_0 -pg 1 -lvl 2 -x 640 -y 460 -defaultsOSRD -preplace inst drive -pg 1 -lvl 3 -x 1010 -y 210 -defaultsOSRD -preplace inst gantry -pg 1 -lvl 3 -x 1010 -y 560 -defaultsOSRD +preplace inst axi_interconnect_0 -pg 1 -lvl 2 -x 730 -y 460 -defaultsOSRD +preplace inst drive -pg 1 -lvl 3 -x 1165 -y 210 -defaultsOSRD +preplace inst gantry -pg 1 -lvl 3 -x 1165 -y 560 -defaultsOSRD preplace netloc Drive_Dir1 1 3 1 NJ 220 preplace netloc drive_DAC_1_INA 1 3 1 NJ 160 preplace netloc drive_DAC_1_INB 1 3 1 NJ 180 preplace netloc drive_DAC_2_INA 1 3 1 NJ 200 -preplace netloc drive_Drive_DIR_1 1 3 1 1160 240n -preplace netloc drive_Drive_DIR_3 1 3 1 1150 260n +preplace netloc drive_Drive_DIR_1 1 3 1 1320 240n +preplace netloc drive_Drive_DIR_3 1 3 1 1310 260n preplace netloc gantry_CONFIG_1 1 3 1 NJ 360 preplace netloc gantry_CONFIG_2 1 3 1 NJ 500 preplace netloc gantry_CONFIG_3 1 3 1 NJ 640 @@ -1400,36 +1447,37 @@ preplace netloc gantry_NSLEEP_3 1 3 1 NJ 740 preplace netloc gantry_STEP_1 1 3 1 NJ 480 preplace netloc gantry_STEP_2 1 3 1 NJ 620 preplace netloc gantry_STEP_3 1 3 1 NJ 760 -preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 40 520 500 830 870 -preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 2 50 320 430 -preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 2 490 90 820 -preplace netloc step_clk_1 1 1 2 430J 70 830 -preplace netloc axi_interconnect_0_M00_AXI 1 2 1 780 150n -preplace netloc axi_interconnect_0_M01_AXI 1 2 1 790 170n -preplace netloc axi_interconnect_0_M02_AXI 1 2 1 800 190n -preplace netloc axi_interconnect_0_M03_AXI 1 2 1 850 210n -preplace netloc axi_interconnect_0_M04_AXI 1 2 1 860 230n -preplace netloc axi_interconnect_0_M05_AXI 1 2 1 860 450n -preplace netloc axi_interconnect_0_M06_AXI 1 2 1 850 470n -preplace netloc axi_interconnect_0_M07_AXI 1 2 1 840 490n -preplace netloc axi_interconnect_0_M08_AXI 1 2 1 800 510n -preplace netloc axi_interconnect_0_M09_AXI 1 2 1 790 530n -preplace netloc axi_interconnect_0_M10_AXI 1 2 1 780 550n +preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 20 520 570 70 1005 +preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 2 30 320 450 +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 2 580 90 975 +preplace netloc step_clk_1 1 1 2 450J 50 985 +preplace netloc axi_interconnect_0_M00_AXI 1 2 1 890 150n +preplace netloc axi_interconnect_0_M01_AXI 1 2 1 900 170n +preplace netloc axi_interconnect_0_M02_AXI 1 2 1 995 190n +preplace netloc axi_interconnect_0_M03_AXI 1 2 1 1015 210n +preplace netloc axi_interconnect_0_M04_AXI 1 2 1 1025 230n +preplace netloc axi_interconnect_0_M05_AXI 1 2 1 1025 450n +preplace netloc axi_interconnect_0_M06_AXI 1 2 1 1015 470n +preplace netloc axi_interconnect_0_M07_AXI 1 2 1 995 490n +preplace netloc axi_interconnect_0_M08_AXI 1 2 1 900 510n +preplace netloc axi_interconnect_0_M09_AXI 1 2 1 890 530n +preplace netloc axi_interconnect_0_M10_AXI 1 2 1 880 550n preplace netloc axi_interconnect_0_M11_AXI 1 2 1 N 570 preplace netloc processing_system7_0_DDR 1 1 3 NJ 60 NJ 60 NJ preplace netloc processing_system7_0_FIXED_IO 1 1 3 NJ 80 NJ 80 NJ -preplace netloc processing_system7_0_M_AXI_GP0 1 1 1 450 120n -preplace netloc processing_system7_0_M_AXI_GP1 1 1 1 440 140n -levelinfo -pg 1 0 240 640 1010 1180 -pagesize -pg 1 -db -bbox -sgen -120 0 1350 850 +preplace netloc processing_system7_0_M_AXI_GP0 1 1 1 470 120n +preplace netloc processing_system7_0_M_AXI_GP1 1 1 1 460 140n +levelinfo -pg 1 0 240 730 1165 1340 +pagesize -pg 1 -db -bbox -sgen -120 0 2430 2220 " } # Restore current instance current_bd_instance $oldCurInst - validate_bd_design save_bd_design +common::send_gid_msg -ssname BD::TCL -id 2050 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." + close_bd_design $design_name } # End of cr_bd_mercury() @@ -1450,7 +1498,7 @@ set_property USED_IN_SYNTHESIS "1" [get_files mercury.bd ] #call make_wrapper to create wrapper files if { [get_property IS_LOCKED [ get_files -norecurse mercury.bd] ] == 1 } { - import_files -fileset sources_1 [file normalize "${origin_dir}/../../../../../../../home/nwdepatie/mercury/mercury.gen/sources_1/bd/mercury/hdl/mercury_wrapper.v" ] + import_files -fileset sources_1 [file normalize "${origin_dir}/mercury/mercury.gen/sources_1/bd/mercury/hdl/mercury_wrapper.v" ] } else { set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse mercury.bd] -top] add_files -norecurse -fileset sources_1 $wrapper_path @@ -1497,7 +1545,7 @@ set_property -name "constrset" -value "constrs_1" -objects $obj set_property -name "description" -value "Vivado Synthesis Defaults" -objects $obj set_property -name "flow" -value "Vivado Synthesis 2023" -objects $obj set_property -name "name" -value "synth_1" -objects $obj -set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "needs_refresh" -value "1" -objects $obj set_property -name "srcset" -value "sources_1" -objects $obj set_property -name "incremental_checkpoint" -value "$proj_dir/mercury.srcs/utils_1/imports/synth_1/mercury_wrapper.dcp" -objects $obj set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj @@ -1956,7 +2004,7 @@ set_property -name "constrset" -value "constrs_1" -objects $obj set_property -name "description" -value "Default settings for Implementation." -objects $obj set_property -name "flow" -value "Vivado Implementation 2023" -objects $obj set_property -name "name" -value "impl_1" -objects $obj -set_property -name "needs_refresh" -value "0" -objects $obj +set_property -name "needs_refresh" -value "1" -objects $obj set_property -name "pr_configuration" -value "" -objects $obj set_property -name "dfx_mode" -value "STANDARD" -objects $obj set_property -name "srcset" -value "sources_1" -objects $obj