The main goal of this lab was to: create a Verilog module, create a test fixtures, analyze the waveform of a schematic, and write the equivalent operation of the schematic in source code. Through this process, the team obtained a deeper understanding of how logic gates and boolean logic interact with Verilog code.
Simulation results from the Verilog representation of this Half-Adder:
- Half-Adder Module - half_adder.v
- Half-Adder Test Bench - half_adder_test.v