From be46665336c51444f6c02ab0f3d44c4f5abdc584 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Thu, 16 Nov 2023 11:56:16 +0100 Subject: [PATCH] Adjusted FPU DIV/SQRT latency to new T-Head unit. Signed-off-by: Pascal Gouedo --- docs/source/pipeline.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/pipeline.rst b/docs/source/pipeline.rst index 516daa2e4..971a0a9e1 100644 --- a/docs/source/pipeline.rst +++ b/docs/source/pipeline.rst @@ -150,7 +150,7 @@ The cycle counts assume zero stall on the instruction-side interface and zero st | Comparison, Conversion | | If there are enough instructions between FPU one and | | or Classify | | the instruction using the result then cycle number is 1. | +------------------------+--------------------------------------+ "Enough instruction" number is either FPU_ADDMUL_LAT, | - | Single Precision | 1..12 | FPU_OTHERS_LAT or 11. | + | Single Precision | 1..19 | FPU_OTHERS_LAT or 11. | | Floating-Point | | If there are no instruction in between then cycle number is | | Division and | | the maximum value for each category. | | Square-Root | | |