From 3e8eb88e88aef15560d3d68272ebeb3894135c26 Mon Sep 17 00:00:00 2001 From: Jalali <110232072+AyoubJalali@users.noreply.github.com> Date: Mon, 27 Jan 2025 23:07:58 +0000 Subject: [PATCH 1/4] Fix UVM scoreboard check VLEN bits only (#2742) --- verif/env/uvme/uvme_cva6_sb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verif/env/uvme/uvme_cva6_sb.sv b/verif/env/uvme/uvme_cva6_sb.sv index ddc7eeeca3..cf15c8f53d 100644 --- a/verif/env/uvme/uvme_cva6_sb.sv +++ b/verif/env/uvme/uvme_cva6_sb.sv @@ -241,7 +241,7 @@ function void uvme_cva6_sb_c::check_pc_trap(uvma_isacov_instr_c instr, if (instr_prev.trap) begin if (mtvec_change) begin if(cfg.xlen == 32) begin - if (instr.rvfi.pc_rdata[31:2] == mtvec_value[31:2]) begin + if (instr.rvfi.pc_rdata[RTLCVA6Cfg.VLEN-1:2] == mtvec_value[RTLCVA6Cfg.VLEN-1:2]) begin //we only support MTVEC Direct mode `uvm_info(get_type_name(), $sformatf("After a trap, PC matches MTVEC value"), UVM_DEBUG) end From be5ac20e46c1258e66718543395c43a5d9a53460 Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Tue, 28 Jan 2025 18:37:07 +0100 Subject: [PATCH 2/4] Fix RVFI rs1/rs2 len from VLEN to XLEN (#2749) RVFI rs1 and rs2 operands were VLEN, it has been fixed to be XLEN. --- core/cva6.sv | 10 +++++++--- core/cva6_rvfi.sv | 12 ++++++------ core/cva6_rvfi_probes.sv | 8 ++++---- core/include/rvfi_types.svh | 4 ++-- core/issue_read_operands.sv | 13 ++++++++++--- core/issue_stage.sv | 22 ++++++++++------------ 6 files changed, 39 insertions(+), 30 deletions(-) diff --git a/core/cva6.sv b/core/cva6.sv index 52c32b2155..e42e6c389c 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -418,6 +418,8 @@ module cva6 // -------------- logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_id_ex; // unregistered version of fu_data_o.operanda logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_id_ex; // unregistered version of fu_data_o.operandb + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs1; + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs2; fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_id_ex; logic [CVA6Cfg.VLEN-1:0] pc_id_ex; @@ -898,7 +900,9 @@ module cva6 .stall_issue_o (stall_issue), //RVFI .rvfi_issue_pointer_o (rvfi_issue_pointer), - .rvfi_commit_pointer_o(rvfi_commit_pointer) + .rvfi_commit_pointer_o(rvfi_commit_pointer), + .rvfi_rs1_o (rvfi_rs1), + .rvfi_rs2_o (rvfi_rs2) ); // --------- @@ -1751,8 +1755,8 @@ module cva6 .decoded_instr_valid_i (issue_entry_valid_id_issue), .decoded_instr_ack_i (issue_instr_issue_id), - .rs1_forwarding_i(rs1_forwarding_id_ex), - .rs2_forwarding_i(rs2_forwarding_id_ex), + .rs1_i(rvfi_rs1), + .rs2_i(rvfi_rs2), .commit_instr_i(commit_instr_id_commit), .commit_drop_i (commit_drop_id_commit), diff --git a/core/cva6_rvfi.sv b/core/cva6_rvfi.sv index 82d7c1da17..4b4f863e4d 100644 --- a/core/cva6_rvfi.sv +++ b/core/cva6_rvfi.sv @@ -64,8 +64,8 @@ module cva6_rvfi logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_valid; logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_ack; - logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs1_forwarding; - logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs2_forwarding; + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs1; + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs2; logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_intr; @@ -132,8 +132,8 @@ module cva6_rvfi assign decoded_instr_valid = instr.decoded_instr_valid; assign decoded_instr_ack = instr.decoded_instr_ack; - assign rs1_forwarding = instr.rs1_forwarding; - assign rs2_forwarding = instr.rs2_forwarding; + assign rs1 = instr.rs1; + assign rs2 = instr.rs2; assign commit_instr_pc = instr.commit_instr_pc; assign commit_instr_op = instr.commit_instr_op; @@ -240,8 +240,8 @@ module cva6_rvfi for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin if (decoded_instr_valid[i] && decoded_instr_ack[i] && !flush_unissued_instr) begin mem_n[issue_pointer[i]] = '{ - rs1_rdata: rs1_forwarding[i], - rs2_rdata: rs2_forwarding[i], + rs1_rdata: rs1[i], + rs2_rdata: rs2[i], lsu_addr: '0, lsu_rmask: '0, lsu_wmask: '0, diff --git a/core/cva6_rvfi_probes.sv b/core/cva6_rvfi_probes.sv index cf23813c29..efd729cb2e 100644 --- a/core/cva6_rvfi_probes.sv +++ b/core/cva6_rvfi_probes.sv @@ -35,8 +35,8 @@ module cva6_rvfi_probes input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_valid_i, input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_ack_i, - input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_i, - input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_i, + input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_i, + input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_i, input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, input logic [CVA6Cfg.NrCommitPorts-1:0] commit_drop_i, @@ -76,8 +76,8 @@ module cva6_rvfi_probes instr.decoded_instr_valid = decoded_instr_valid_i; instr.decoded_instr_ack = decoded_instr_ack_i; - instr.rs1_forwarding = rs1_forwarding_i; - instr.rs2_forwarding = rs2_forwarding_i; + instr.rs1 = rs1_i; + instr.rs2 = rs2_i; instr.ex_commit_cause = ex_commit_i.cause; instr.ex_commit_valid = ex_commit_i.valid; diff --git a/core/include/rvfi_types.svh b/core/include/rvfi_types.svh index b393782461..69c552e7a3 100644 --- a/core/include/rvfi_types.svh +++ b/core/include/rvfi_types.svh @@ -104,8 +104,8 @@ logic [Cfg.NrIssuePorts-1:0] fetch_entry_valid; \ logic [Cfg.NrIssuePorts-1:0][31:0] instruction; \ logic [Cfg.NrIssuePorts-1:0] is_compressed; \ - logic [Cfg.NrIssuePorts-1:0][Cfg.VLEN-1:0] rs1_forwarding; \ - logic [Cfg.NrIssuePorts-1:0][Cfg.VLEN-1:0] rs2_forwarding; \ + logic [Cfg.NrIssuePorts-1:0][Cfg.XLEN-1:0] rs1; \ + logic [Cfg.NrIssuePorts-1:0][Cfg.XLEN-1:0] rs2; \ logic [Cfg.NrCommitPorts-1:0][Cfg.VLEN-1:0] commit_instr_pc; \ ariane_pkg::fu_op [Cfg.NrCommitPorts-1:0] commit_instr_op; \ logic [Cfg.NrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rs1; \ diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index 90cc3ad7c0..8f70016f07 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -51,9 +51,9 @@ module issue_read_operands // FU data useful to execute instruction - EX_STAGE output fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_o, // Unregistered version of fu_data_o.operanda - EX_STAGE - output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs1_forwarding_o, + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_o, // Unregistered version of fu_data_o.operandb - EX_STAGE - output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs2_forwarding_o, + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_o, // Program Counter - EX_STAGE output logic [CVA6Cfg.VLEN-1:0] pc_o, // Is zcmt - EX_STAGE @@ -122,7 +122,12 @@ module issue_read_operands // FPR write enable - COMMIT_STAGE input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i, // Issue stall - PERF_COUNTERS - output logic stall_issue_o + output logic stall_issue_o, + // Information dedicated to RVFI - RVFI + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs1_o, + // Information dedicated to RVFI - RVFI + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs2_o + ); localparam OPERANDS_PER_INSTR = CVA6Cfg.NrRgprPorts / CVA6Cfg.NrIssuePorts; @@ -253,6 +258,8 @@ module issue_read_operands for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin assign rs1_forwarding_o[i] = fu_data_n[i].operand_a[CVA6Cfg.VLEN-1:0]; //forwarding or unregistered rs1 value assign rs2_forwarding_o[i] = fu_data_n[i].operand_b[CVA6Cfg.VLEN-1:0]; //forwarding or unregistered rs2 value + assign rvfi_rs1_o[i] = fu_data_n[i].operand_a; + assign rvfi_rs2_o[i] = fu_data_n[i].operand_b; end assign fu_data_o = fu_data_q; diff --git a/core/issue_stage.sv b/core/issue_stage.sv index eb33f6af2b..68ace5dac6 100644 --- a/core/issue_stage.sv +++ b/core/issue_stage.sv @@ -159,7 +159,11 @@ module issue_stage // Information dedicated to RVFI - RVFI output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer_o, // Information dedicated to RVFI - RVFI - output logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_commit_pointer_o + output logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_commit_pointer_o, + // Information dedicated to RVFI - RVFI + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs1_o, + // Information dedicated to RVFI - RVFI + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs2_o ); // --------------------------------------------------- // Scoreboard (SB) <-> Issue and Read Operands (IRO) @@ -178,14 +182,6 @@ module issue_stage logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_valid_sb_iro; logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack_iro_sb; - logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs1_forwarding_xlen; - logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs2_forwarding_xlen; - - for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin - assign rs1_forwarding_o[i] = rs1_forwarding_xlen[i][CVA6Cfg.VLEN-1:0]; - assign rs2_forwarding_o[i] = rs2_forwarding_xlen[i][CVA6Cfg.VLEN-1:0]; - end - assign issue_instr_o = issue_instr_sb_iro[0]; assign issue_instr_hs_o = issue_instr_valid_sb_iro[0] & issue_ack_iro_sb[0]; @@ -262,8 +258,8 @@ module issue_stage .issue_ack_o (issue_ack_iro_sb), .fwd_i (fwd), .fu_data_o (fu_data_o), - .rs1_forwarding_o (rs1_forwarding_xlen), - .rs2_forwarding_o (rs2_forwarding_xlen), + .rs1_forwarding_o (rs1_forwarding_o), + .rs2_forwarding_o (rs2_forwarding_o), .pc_o, .is_zcmt_o, .is_compressed_instr_o, @@ -302,7 +298,9 @@ module issue_stage .wdata_i, .we_gpr_i, .we_fpr_i, - .stall_issue_o + .stall_issue_o, + .rvfi_rs1_o (rvfi_rs1_o), + .rvfi_rs2_o (rvfi_rs2_o) ); endmodule From 59822e7ad191df40bf384feef20e45e8402eef74 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?= <61976467+ASintzoff@users.noreply.github.com> Date: Wed, 29 Jan 2025 11:45:47 +0100 Subject: [PATCH 3/4] instr_scan.sv: remove useless condition (#2748) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit is_rvc is redundant with riscv::OpcodeC1, riscv::OpcodeC2 Signed-off-by: André Sintzoff Co-authored-by: JeanRochCoulon --- core/frontend/instr_scan.sv | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/core/frontend/instr_scan.sv b/core/frontend/instr_scan.sv index d72fc94faa..6ec09543d9 100644 --- a/core/frontend/instr_scan.sv +++ b/core/frontend/instr_scan.sv @@ -69,11 +69,8 @@ module instr_scan #( }; endfunction - logic is_rvc; - assign is_rvc = (instr_i[1:0] != 2'b11); - logic rv32_rvc_jal; - assign rv32_rvc_jal = (CVA6Cfg.XLEN == 32) & ((instr_i[15:13] == riscv::OpcodeC1Jal) & is_rvc & (instr_i[1:0] == riscv::OpcodeC1)); + assign rv32_rvc_jal = (CVA6Cfg.XLEN == 32) & ((instr_i[15:13] == riscv::OpcodeC1Jal) & (instr_i[1:0] == riscv::OpcodeC1)); logic is_xret; assign is_xret = logic'(instr_i[31:30] == 2'b00) & logic'(instr_i[28:0] == 29'b10000001000000000000001110011); @@ -90,22 +87,20 @@ module instr_scan #( assign rvi_jump_o = logic'(instr_i[6:0] == riscv::OpcodeJal) | is_xret; // opcode JAL - assign rvc_jump_o = ((instr_i[15:13] == riscv::OpcodeC1J) & is_rvc & (instr_i[1:0] == riscv::OpcodeC1)) | rv32_rvc_jal; + assign rvc_jump_o = ((instr_i[15:13] == riscv::OpcodeC1J) & (instr_i[1:0] == riscv::OpcodeC1)) | rv32_rvc_jal; // always links to register 0 logic is_jal_r; assign is_jal_r = (instr_i[15:13] == riscv::OpcodeC2JalrMvAdd) & (instr_i[6:2] == 5'b00000) - & (instr_i[1:0] == riscv::OpcodeC2) - & is_rvc; + & (instr_i[1:0] == riscv::OpcodeC2); assign rvc_jr_o = is_jal_r & ~instr_i[12]; // always links to register 1 e.g.: it is a jump assign rvc_jalr_o = is_jal_r & instr_i[12]; assign rvc_call_o = rvc_jalr_o | rv32_rvc_jal; assign rvc_branch_o = ((instr_i[15:13] == riscv::OpcodeC1Beqz) | (instr_i[15:13] == riscv::OpcodeC1Bnez)) - & (instr_i[1:0] == riscv::OpcodeC1) - & is_rvc; + & (instr_i[1:0] == riscv::OpcodeC1); // check that rs1 is x1 or x5 assign rvc_return_o = ((instr_i[11:7] == 5'd1) | (instr_i[11:7] == 5'd5)) & rvc_jr_o; From 07f19ea319c9b31d064a221c4c46839057564df9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?= <61976467+ASintzoff@users.noreply.github.com> Date: Wed, 29 Jan 2025 11:46:34 +0100 Subject: [PATCH 4/4] decoder.sv: add condition CVA6Cfg.SoftwareInterruptEn (#2747) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit to improve conditional coverage Signed-off-by: André Sintzoff Co-authored-by: JeanRochCoulon --- core/decoder.sv | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/core/decoder.sv b/core/decoder.sv index 5b2ea17687..de52e7f232 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -1667,9 +1667,11 @@ module decoder if (irq_ctrl_i.mip[riscv::IRQ_M_TIMER] && irq_ctrl_i.mie[riscv::IRQ_M_TIMER]) begin interrupt_cause = INTERRUPTS.M_TIMER; end - // Machine Mode Software Interrupt - if (irq_ctrl_i.mip[riscv::IRQ_M_SOFT] && irq_ctrl_i.mie[riscv::IRQ_M_SOFT]) begin - interrupt_cause = INTERRUPTS.M_SW; + if (CVA6Cfg.SoftwareInterruptEn) begin + // Machine Mode Software Interrupt + if (irq_ctrl_i.mip[riscv::IRQ_M_SOFT] && irq_ctrl_i.mie[riscv::IRQ_M_SOFT]) begin + interrupt_cause = INTERRUPTS.M_SW; + end end // Machine Mode External Interrupt if (irq_ctrl_i.mip[riscv::IRQ_M_EXT] && irq_ctrl_i.mie[riscv::IRQ_M_EXT]) begin