From 3824fa870f1593d37773d4698c57fc5081b2dcbd Mon Sep 17 00:00:00 2001 From: AMAN MOGAL <81488924+amanmogal@users.noreply.github.com> Date: Fri, 29 Nov 2024 12:14:12 +0530 Subject: [PATCH 1/3] Issue #27715 --- .vscode/settings.json | 2 ++ .../plugin/aarch64/debug_capabilities.hpp | 25 +++++++++++++++++++ .../aarch64/jit_uni_eltwise_generic.cpp | 5 ++++ 3 files changed, 32 insertions(+) create mode 100644 .vscode/settings.json create mode 100644 src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 00000000000000..e02aef276ea851 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,2 @@ +{ +} \ No newline at end of file diff --git a/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp b/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp new file mode 100644 index 00000000000000..7f16aef752e0b6 --- /dev/null +++ b/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp @@ -0,0 +1,25 @@ +#ifndef DEBUG_CAPABILITIES_HPP +#define DEBUG_CAPABILITIES_HPP + +#include +#include +#include // For SIMD support + +class RegPrints { +public: + // Print general-purpose registers + static void print_gpr(const uint64_t& reg_value, const char* reg_name) { + std::cout << "Register " << reg_name << ": " << std::hex << reg_value << std::endl; + } + + // Print vector registers (SIMD) + static void print_simd(const float32x4_t& reg_value, const char* reg_name) { + float values[4]; + vst1q_f32(values, reg_value); // Store SIMD register into an array + std::cout << "SIMD Register " << reg_name << ": [" + << values[0] << ", " << values[1] << ", " + << values[2] << ", " << values[3] << "]" << std::endl; + } +}; + +#endif // DEBUG_CAPABILITIES_HPP diff --git a/src/plugins/intel_cpu/src/nodes/kernels/aarch64/jit_uni_eltwise_generic.cpp b/src/plugins/intel_cpu/src/nodes/kernels/aarch64/jit_uni_eltwise_generic.cpp index cfe36f78cc40f9..06721a685be610 100644 --- a/src/plugins/intel_cpu/src/nodes/kernels/aarch64/jit_uni_eltwise_generic.cpp +++ b/src/plugins/intel_cpu/src/nodes/kernels/aarch64/jit_uni_eltwise_generic.cpp @@ -50,13 +50,18 @@ void jit_uni_eltwise_generic::generate() { if (jep.use_runtime_ptrs) { for (size_t i = 0; i < jep.inputs_number; i++) { ldr(start_to_offsets, ptr(reg_const_params, static_cast(offsetof(node::jit_eltwise_call_args_ptrs, src_offsets) + i * sizeof(size_t)))); + RegPrints::print_gpr(start_to_offsets.getIdx(), "start_to_offsets"); ldr(get_src_reg(i), ptr(reg_const_params, static_cast(offsetof(node::jit_eltwise_call_args_ptrs, src_ptr[0]) + i * sizeof(size_t)))); + RegPrints::print_gpr(get_src_reg(i).getIdx(), "src_ptr"); XReg offset_reg = get_aux_gpr(0); // X_TMP_0; XReg index_reg = get_aux_gpr(1); // X_TMP_1; for (int j = 0; j < offset_count; j++) { ldr(offset_reg, ptr(start_to_offsets, static_cast(j * sizeof(size_t)))); + RegPrints::print_gpr(offset_reg.getIdx(), "offset_reg"); ldr(index_reg, ptr(reg_indexes, static_cast(j * sizeof(size_t)))); + RegPrints::print_gpr(index_reg.getIdx(), "index_reg"); madd(get_src_reg(i), offset_reg, index_reg, get_src_reg(i)); + RegPrints::print_gpr(get_src_reg(i).getIdx(), "effective_address"); } } From 4d850efaa6e976711b142bd70f20bf7617524abe Mon Sep 17 00:00:00 2001 From: AMAN MOGAL <81488924+amanmogal@users.noreply.github.com> Date: Mon, 2 Dec 2024 17:52:35 +0530 Subject: [PATCH 2/3] Use ov::util::join for SIMD register value formatting --- .vscode/settings.json | 2 -- .../src/emitters/plugin/aarch64/debug_capabilities.hpp | 4 ++-- 2 files changed, 2 insertions(+), 4 deletions(-) delete mode 100644 .vscode/settings.json diff --git a/.vscode/settings.json b/.vscode/settings.json deleted file mode 100644 index e02aef276ea851..00000000000000 --- a/.vscode/settings.json +++ /dev/null @@ -1,2 +0,0 @@ -{ -} \ No newline at end of file diff --git a/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp b/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp index 7f16aef752e0b6..906fce65c3b107 100644 --- a/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp +++ b/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp @@ -4,6 +4,7 @@ #include #include #include // For SIMD support +#include "openvino/util/ov_string_utils.hpp" // For ov::util::join class RegPrints { public: @@ -17,8 +18,7 @@ class RegPrints { float values[4]; vst1q_f32(values, reg_value); // Store SIMD register into an array std::cout << "SIMD Register " << reg_name << ": [" - << values[0] << ", " << values[1] << ", " - << values[2] << ", " << values[3] << "]" << std::endl; + << ov::util::join(values, values + 4, ", ") << "]" << std::endl; } }; From 61cf09ecb9f6f2da034e4ef182a5cadde4f488be Mon Sep 17 00:00:00 2001 From: AMAN MOGAL <81488924+amanmogal@users.noreply.github.com> Date: Wed, 4 Dec 2024 20:36:49 +0530 Subject: [PATCH 3/3] updated src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp --- .../plugin/aarch64/debug_capabilities.hpp | 30 +++++++++++++------ 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp b/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp index 906fce65c3b107..cbde685edb64bf 100644 --- a/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp +++ b/src/plugins/intel_cpu/src/emitters/plugin/aarch64/debug_capabilities.hpp @@ -8,17 +8,29 @@ class RegPrints { public: - // Print general-purpose registers - static void print_gpr(const uint64_t& reg_value, const char* reg_name) { - std::cout << "Register " << reg_name << ": " << std::hex << reg_value << std::endl; + static void print_gpr(jit_generator &gen, const uint64_t ®_value, const char *reg_name) { + // Emit JIT code to print general-purpose register during runtime + gen.mov(gen.rdi, reg_value); // Move register value into rdi + gen.mov(gen.rsi, reinterpret_cast(reg_name)); // Pass register name as argument + gen.call(reinterpret_cast(print_runtime_gpr)); // Call runtime function } - // Print vector registers (SIMD) - static void print_simd(const float32x4_t& reg_value, const char* reg_name) { - float values[4]; - vst1q_f32(values, reg_value); // Store SIMD register into an array - std::cout << "SIMD Register " << reg_name << ": [" - << ov::util::join(values, values + 4, ", ") << "]" << std::endl; + static void print_simd(jit_generator &gen, const float32x4_t ®_value, const char *reg_name) { + // Emit JIT code to handle SIMD printing during runtime + gen.mov(gen.rdi, reinterpret_cast(®_value)); // Move SIMD value into rdi + gen.mov(gen.rsi, reinterpret_cast(reg_name)); // Pass register name as argument + gen.call(reinterpret_cast(print_runtime_simd)); // Call runtime function + } + +private: + // Runtime functions to print the registers + static void print_runtime_gpr(const char *reg_name, uint64_t value) { + std::cout << "Register " << reg_name << ": " << std::hex << value << std::endl; + } + + static void print_runtime_simd(const char *reg_name, const float *values) { + std::cout << "SIMD Register " << reg_name << ": [" + << values[0] << ", " << values[1] << ", " << values[2] << ", " << values[3] << "]" << std::endl; } };